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Manager L2 and backplane C2: stocked parts, L2 land enlarged - #16

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Oct 6, 2026
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Requested by Udara Vimarsha · project thread

Before: the manager's 33 µH aux-buck inductor L2 sat on a 1210 land, and no stocked 1210 33 µH part is rated above 0.5 A, while the design calls for 1.2 A. The backplane's 470 µF bulk cap C2 had no part picked.

After: L2 is the cjiang FNR5040S330MT (C167973, 5 × 5 × 4 mm, Isat 1.30 A min, Irms 1.20 A min, 0.244 Ω max per the cjiang FNR datasheet) on KiCad's L_Changjiang_FNR5040S land. C2 is the Nichicon UCX1H471MNS1MS (C462700, 16 × 16.5, 50 V, 70 mΩ), which fits the existing CP_Elec_16x17.5 land. Panasonic EEEFK1H471AM (C178551) is the fallback.

The manager board was changed as an ECO, without a full re-route:

  • L2 moved to (18.8, 48.4) so its courtyard clears C54, F1 and C50/C51.
  • C54/C55 are turned 180°, so 5V0 runs in one straight 0.8 mm track from L2. Their PGND pads are tied together and go to the plane through vias west of C55.
  • SW_AUX and the start of the 5V0 trunk are redrawn and locked, matching route_critical.py.
  • PRESENT1 and PRESENT4–7 are re-routed around the bigger part with finish_routes.py. This adds about 43 mm of B.Cu jumpers to the existing 570 mm.
  • gen_board.py PLACEMENT and route_critical.py ROUTES carry the same change, so a full rebuild still reproduces the board.

How

DRC on the manager board shows 0 unconnected items, 0 errors and 4 warnings (it was 5). check_netlist, check_footprints, the courtyard and keep-out checks, and bom.py --check all pass. The one plane advisory (a J3 island) was already there before this change. The fab zip, BOM, JLCPCB CSV and CPL are regenerated. Docs updated: SOURCING.md, HANDOVER.md and the manager tools README (with ECO steps).

Not in this PR: the phase-1 and phase-2 L2 parts still use a 1210 land and have the same current problem.

🤖 Generated with Claude Code

https://claude.ai/code/session_016Wr11AqV5ZRbpysgP42oHy


Generated by Claude Code

Manager L2 (33u/1.2A aux-buck inductor) had a 1210 land, and no stocked
1210 33 uH is rated above 0.5 A. It is now the 5x5 mm cjiang
FNR5040S330MT (C167973: Isat 1.30 A min, Irms 1.20 A min, 0.244 ohm)
on KiCad's L_Changjiang_FNR5040S land.

Board ECO, no full re-route:
- L2 moves to (18.8, 48.4) so its courtyard clears C54, F1 and C50/C51;
  C54/C55 turn 180 so their 5V0 pads line up with L2's 5V0 pad (one
  straight 0.8 mm run) and their PGND pads are tied and dropped to the
  plane west of C55.
- SW_AUX and the 5V0 head are redrawn locked, matching route_critical.py;
  PRESENT1/4-7 are re-routed round the bigger part by finish_routes.py.
- gen_board.py PLACEMENT and route_critical.py ROUTES carry the same
  change, so a full rebuild reproduces it.
- DRC: 0 unconnected, 0 errors, 4 warnings (was 5). Fab zip, BOM, CPL
  regenerated.

Backplane C2 (470u/50V on CP_Elec_16x17.5): Nichicon UCX1H471MNS1MS
(C462700, 16x16.5, 70 mOhm), which fits the existing land; Panasonic
EEEFK1H471AM (C178551) is the fallback. No board change.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_016Wr11AqV5ZRbpysgP42oHy
@udaravima udaravima self-assigned this Oct 5, 2026
@udaravima
udaravima marked this pull request as ready for review October 6, 2026 06:25
@udaravima
udaravima merged commit 5ad70f0 into development Oct 6, 2026
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@udaravima
udaravima deleted the claude/fix-mgr-l2-bp-c2-30z2u9 branch October 6, 2026 06:25
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