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Release v0.2.0: merge development into master - #19

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Requested by Udara Vimarsha · project thread

Before: master is at v0.1.0. On that release the Phase-1, Phase-2 and manager boards put L2 on a 1210 land that no stocked part can serve, and several BOM rows still need a decision.

After: master carries v0.2.0. All three boards use the same 5 × 5 mm L2, the backplane C2 is picked, and no CHECK: row is left in any BOM.

Merge #18 into development first. This PR then picks it up automatically, and that is when to mark it ready.

How: batched merge of #15, #16, #17 and #18, the same way as #14.

The release notes and order files for all four boards are staged outside the repo, ready for the GitHub release.

🤖 Generated with Claude Code

https://claude.ai/code/session_01Kap1Vqs6wqd3fshJdnERW7


Generated by Claude Code

claude and others added 6 commits September 29, 2026 00:31
Generated with common/cpl.py from the released boards, matching the
phase-1 and phase-2 CPL files, so all four boards ship the same order set.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_012vqeoXfZfZw2oZCwv9rjfw
Manager and backplane: add placement (CPL) files
Manager L2 (33u/1.2A aux-buck inductor) had a 1210 land, and no stocked
1210 33 uH is rated above 0.5 A. It is now the 5x5 mm cjiang
FNR5040S330MT (C167973: Isat 1.30 A min, Irms 1.20 A min, 0.244 ohm)
on KiCad's L_Changjiang_FNR5040S land.

Board ECO, no full re-route:
- L2 moves to (18.8, 48.4) so its courtyard clears C54, F1 and C50/C51;
  C54/C55 turn 180 so their 5V0 pads line up with L2's 5V0 pad (one
  straight 0.8 mm run) and their PGND pads are tied and dropped to the
  plane west of C55.
- SW_AUX and the 5V0 head are redrawn locked, matching route_critical.py;
  PRESENT1/4-7 are re-routed round the bigger part by finish_routes.py.
- gen_board.py PLACEMENT and route_critical.py ROUTES carry the same
  change, so a full rebuild reproduces it.
- DRC: 0 unconnected, 0 errors, 4 warnings (was 5). Fab zip, BOM, CPL
  regenerated.

Backplane C2 (470u/50V on CP_Elec_16x17.5): Nichicon UCX1H471MNS1MS
(C462700, 16x16.5, 70 mOhm), which fits the existing land; Panasonic
EEEFK1H471AM (C178551) is the fallback. No board change.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_016Wr11AqV5ZRbpysgP42oHy
Manager L2 and backplane C2: stocked parts, L2 land enlarged
All four boards are routed, firmware is at 0.2, and PR #16 changed the
manager L2 and backplane C2. The status tables, build guide and sourcing
notes still described the July state (phase-2 with 83 unrouted
connections, manager unrouted, 120 x 80 phase-1, unpinned Q3/Q4).

- README / HANDOVER: current board and firmware state, branch workflow,
  the five open BOM CHECK rows and the open phase-1/2 L2 question
- build guide: 100 x 80 board, the real section 3.3 decisions
- SOURCING / docs/09: parts picked since (USB-C, encoder, bus shunt,
  C2, L2, Q1-Q4 stand-in), retired placeholder-footprint notes
- LAYOUT status table, small stale lines in MECHANICAL, docs/12,
  PARTS-TO-DOWNLOAD
- BOM: drop the stale "placeholder footprint" note on L1/L3

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01Kqz15x8VgP6VUFD4sa23bR
Docs: bring README, HANDOVER, SOURCING and guides up to date
@udaravima udaravima self-assigned this Oct 6, 2026
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