Manager L2 and backplane C2: stocked parts, L2 land enlarged

HANDOVER.md

@@ -48,7 +48,7 @@ manager, CAN 2.0B @500k. Docs 01–07 are the spec; read 05 (build plan) first
 | PCB — Phase 2 | **83 unconnected, 0 copper DRC, silk clean (2026-07-26, c1a86eb)** — see the resume section; finish by hand in KiCad. Older detail below: |
 | PCB — Phase 2 (history) | **(2026-07-25, 27fb2d1).** `gen_board.py` placement green (173 comps, all pour/courtyard/edge assertions pass, 130×90 4-layer); `route_board.py` pass-1 done (power pours, In2 heat patches, both phases' gate fan-outs, Kelvin pairs, disconnect trunk). DRC: **copper down to ~19 clearance + ~11 dangling/mask/hole in 3 known clusters** (see resume section); 243 unconnected = signal nets, autoroute not yet run. Found & fixed a real LM5143 land-pattern bug in the process (see load-bearing decisions) |
 | PCB — Phase 3 backplane | **COMPLETE pass-1 (2026-07-25)**: `phase3-backplane/tools/gen_board.py` (single-script: placement + 2oz bus pours + stitching + ALL signal routing) — **0 copper DRC, 0 unconnected**; only lib-bookkeeping (39) + 1 silk nick remain. 8 slots @30mm (XT60PW-F rot-90 mates the module pad-for-pad, socket y60..77.8 = module J5 1:1), M6 lugs -> RS1‖RS2 0.5mΩ Kelvin-sensed by INA228, nested PRESENT L-bus, CAN terminated past both end slots, E-stop chain threaded per docs. Netlist from `tools/wip/bp.net` (regenerate via kicad-cli) |
-| PCB — Phase 3 manager | **Routed, 0 unconnected, 0 DRC errors (2026-09-27, draft PR into `development` from `claude/route-manager-shxsg1`)**: placement reworked (15+ passives had been placed by stale refdes, far from their pins; U8 buck re-laid tight round its pinout; U11 turned so CAN faces J1; U12 in the USB path), PGND now poured on both layers (was F.Cu 3V3 / B.Cu PGND), USB + CAN pairs and buck power copper hand-drawn and locked (`route_critical.py`), rest Freerouting 1.9 + `finish_routes.py`, 283 PGND stitch vias. DRC = 5 warnings (4 silk, 1 U8 courtyard-override lib mismatch). Antenna keep-out copper-free. Pipeline: `phase3-manager/tools/README.md` |
+| PCB — Phase 3 manager | **Routed, 0 unconnected, 0 DRC errors (2026-09-27, draft PR into `development` from `claude/route-manager-shxsg1`)**: placement reworked (15+ passives had been placed by stale refdes, far from their pins; U8 buck re-laid tight round its pinout; U11 turned so CAN faces J1; U12 in the USB path), PGND now poured on both layers (was F.Cu 3V3 / B.Cu PGND), USB + CAN pairs and buck power copper hand-drawn and locked (`route_critical.py`), rest Freerouting 1.9 + `finish_routes.py`, 283 PGND stitch vias. DRC = 5 warnings (4 silk, 1 U8 courtyard-override lib mismatch). Antenna keep-out copper-free. Pipeline: `phase3-manager/tools/README.md`. **ECO 2026-10-05:** L2 moved from the 1210 land (no stocked 33 µH above 0.5 A) to a 5×5 mm FNR5040S (FNR5040S330MT, Isat 1.3 A); C54/C55 turned 180° so 5V0 runs straight from L2; PRESENT1/4–7 re-routed round the bigger part with `finish_routes.py`. Still 0 unconnected, 0 DRC errors, 4 warnings |
 | Module firmware | v0.2 builds clean (7.1 KB): full peripheral binding + CAN dispatch around the host-tested `module_core`. 0.2 (2026-09-28) closes the two protection gaps from the bench-test review: OCP backup #2 (`lb_core_ocp_sample`: INA240 ADC or INA228 SOVL alert >110 % i_max for >5 ms) and OVP latch #4 (OVP_TRIP routed to PB4 on the 100 × 80 board; EXTI4 kills EN, tick latches). Untested on silicon (no board yet) |
 | Host tests | `cd firmware/tests && make test` — must stay green. **5 suites now**: can, core, manager, scpi, ui |
 | Manager firmware | **v0.2 COMPLETE (2026-07-25, commit 174595e)**: `scpi_core` + `ui_core` join `manager_core` as host-tested cores; ESP-IDF shell fully written (display/encoder/USB-SCPI/app_main). **First compile 2026-09-27: builds clean on IDF v5.3.2** (355 KB image, two build fixes). Untested on silicon. See docs/10 |

hardware/SOURCING.md

@@ -62,6 +62,8 @@ Decisions taken this pass (user-approved 2026-07-18):
 | Bus shunt 0.5 mΩ 3920 ×2 ∥ | C466580 | 0.60 | 2.9k | BVS-M-R0005: 2 in parallel = 0.25 mΩ (0.5 W each @62 A); verify power rating on ds. Alt: ARCS8518 100 µΩ bar $3.64/49 |
 | 220 µF 35 V hybrid ×4 | C454349 | 1.42 | **1** | Panasonic EEHZA1V221P D10×10.2, 20 mΩ / 2.5 A — fits the CP_Elec_10x10.5 land. Stocked alternative on the same land: SUNCON 35HVH220M+P (C179812, D10×12.5, 8 in stock 2026-09-28). The earlier D8 SVZ pick (C2923769) did not fit the land and is out of stock |
 | 470 µF 50 V bulk | C106666 | 0.10 | 73k | **THT radial D10×20** — cheaper + stronger than SMD; footprint changes at PCB pass |
+| 470 µF 50 V SMD (backplane C2) | C462700 | 1.63 | 633 (JLCPCB) | Nichicon UCX1H471MNS1MS, 16×16.5, 70 mΩ, 1.0 A @100 kHz, 135 °C. The board has an SMD CP_Elec_16x17.5 land (17×17 platform), not the THT D10 above; 16×16.5 cans fit it. Fallback: Panasonic EEEFK1H471AM (C178551, 131). Picked 2026-10-05 |
+| 33 µH aux-buck inductor (manager L2) | C167973 | 0.06 | 51k (JLCPCB) | cjiang FNR5040S330MT, 5×5×4 mm: **Isat 1.30 A min / Irms 1.20 A min / DCR 0.244 Ω max** (cjiang FNR datasheet). No 1210 33 µH is stocked above 0.5 A, so the manager land grew to L_Changjiang_FNR5040S (2026-10-05). Phase-1/2 L2 are still 1210 |
 | 10 µF 50 V X7S 1210 ×8+6 | C126612 | 0.144 | 43k | GCM32EC71H106KA03L; also replaces the 22 µF/50 V output MLCCs (that value barely exists) |
 | 8 MHz 3225 crystal | C400090 | 0.105 | 200k | cheap parts are CL=12 pF → C66/C67 = 18 p (APPLIED, both phases) |
 

hardware/common/lcsc_parts.py

@@ -117,6 +117,20 @@
     ({MGR: ["F1"]}, "C151091", "0297002.WXNV", "Littelfuse", 0.11,
      "2 A MINI blade fuse, soldered directly into the land (no holder)"),
 
+    # ---- Deferred picks closed 2026-10-05 (JLCPCB stock checked that day) --
+    # No 1210 33 uH is stocked above 0.5 A, so the manager's L2 land grew to
+    # the 5x5 mm FNR5040S (board re-routed round it). Datasheet: 33 uH +-20 %,
+    # DCR 0.244 ohm max, Isat 1.30 A min / 1.45 A typ, Irms 1.20 A min.
+    ({MGR: ["L2"]}, "C167973", "FNR5040S330MT", "cjiang (Changjiang Microelectronics)",
+     0.06, "5x5x4 mm shielded, KiCad L_Changjiang_FNR5040S land; Isat 1.30 A "
+     "min covers the 33u/1.2A value. Any 5040-size 33 uH >=1.2 A part with "
+     "the same 2.3 mm pad gap fits"),
+    # C2 sits on CP_Elec_16x17.5 (17 x 17 mm platform); 16 x 16.5 cans share
+    # that platform and terminal layout, so no board change.
+    ({BP: ["C2"]}, "C462700", "UCX1H471MNS1MS", "Nichicon", 1.63,
+     "SMD 16x16.5, 50 V, 70 mOhm, 1.0 A ripple at 100 kHz, 135 C rated; "
+     "fits the 16x17.5 land. Fallback: Panasonic EEEFK1H471AM (C178551)"),
+
     # ---- D. Phase-1 passives & small parts (JLCPCB catalogue, 2026-09-27) --
     ({P1: ["C1"]}, "C57112", "0603B103K500NT", "FH", 0.0108,
      ""),
@@ -231,8 +245,6 @@
     ({P1: ["F1"]}, "through-hole, hand-solder; the land is KiCad's "
      "direct-solder mini blade pattern, so a 10 A mini blade (ATM) fuse "
      "solders straight in with no holder (C3207114 does not fit it)"),
-    ({BP: ["C2"]}, "SOURCING's 470 uF part C106666 is THT D10; this board "
-     "uses a 16x17.5 SMD footprint - choose an SMD part"),
     ({P1: ["J2", "J3", "J5", "J6"]}, "through-hole pin header: hand-solder "
      "(or pay for JLCPCB THT assembly)"),
     ({MGR: ["J6"]}, "ILI9341+XPT2046 2.8in module plugs here - AliExpress, "

hardware/phase3-backplane/bom/phase3-backplane-bom.csv

@@ -1,6 +1,6 @@
 Item,Qty,References,Value,Footprint,LCSC,MPN,Manufacturer,Unit USD,Ext USD,Note
 1,2,C1 C3,100n,Capacitor_SMD:C_0603_1608Metric,,,,,,
-2,1,C2,470u/50V,Capacitor_SMD:CP_Elec_16x17.5,,,,,,SOURCING's 470 uF part C106666 is THT D10; this board uses a 16x17.5 SMD footprint - choose an SMD part
+2,1,C2,470u/50V,Capacitor_SMD:CP_Elec_16x17.5,C462700,UCX1H471MNS1MS,Nichicon,1.63,1.63,"SMD 16x16.5, 50 V, 70 mOhm, 1.0 A ripple at 100 kHz, 135 C rated; fits the 16x17.5 land. Fallback: Panasonic EEEFK1H471AM (C178551)"
 3,1,D5,SMBJ33A,Diode_SMD:D_SMB,,,,,,
 4,1,J1,MANAGER,Connector_PinHeader_2.54mm:PinHeader_1x20_P2.54mm_Vertical,,,,,,
 5,1,J2,E-STOP NC (jumper if absent),Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical,,,,,,
@@ -27,4 +27,4 @@ Item,Qty,References,Value,Footprint,LCSC,MPN,Manufacturer,Unit USD,Ext USD,Note
 26,1,R3,120R slot7-end,Resistor_SMD:R_0603_1608Metric,,,,,,
 27,2,RS1 RS2,0m5 3920,labbench:R3920_BVS,C466580,BVS-M-R0005,Isabellenhuette,0.6,1.2,2 in parallel = 0.25 mOhm; verify power rating on datasheet
 28,1,U1,INA228,Package_SO:VSSOP-10_3x3mm_P0.5mm,C5214669,INA228AQDGSRQ1,TI,17.16,17.16,"automotive grade of INA228AIDGSR, same VSSOP-10 pinout and register map (no firmware change); the AIDGSR (C2887910) was still out of stock on 2026-09-28 - swap back if it returns, it is about a quarter of the price"
-,30,,,,,,,,22.84,"11/30 placements have an LCSC number; total covers those only (qty-1, SOURCING.md 2026-07-18)"
+,30,,,,,,,,24.47,"12/30 placements have an LCSC number; total covers those only (qty-1, SOURCING.md 2026-07-18)"

hardware/phase3-backplane/bom/phase3-backplane-jlcpcb.csv

@@ -1,6 +1,6 @@
 Comment,Designator,Footprint,LCSC Part #
 100n,"C1,C3",C_0603_1608Metric,
-470u/50V,C2,CP_Elec_16x17.5,
+470u/50V,C2,CP_Elec_16x17.5,C462700
 SMBJ33A,D5,D_SMB,
 MANAGER,J1,PinHeader_1x20_P2.54mm_Vertical,
 E-STOP NC (jumper if absent),J2,PinHeader_1x02_P2.54mm_Vertical,

hardware/phase3-backplane/phase3-backplane.kicad_sch

@@ -1705,6 +1705,15 @@
     (property "Datasheet" "~" (at 173.99 62.23 0)
       (effects (font (size 1.27 1.27)) hide)
     )
+    (property "LCSC" "C462700" (at 173.99 62.23 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "MPN" "UCX1H471MNS1MS" (at 173.99 62.23 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Manufacturer" "Nichicon" (at 173.99 62.23 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
     (pin "1" (uuid 5f7aa2ef-10eb-40dd-906d-3b4b511341df))
     (pin "2" (uuid 47e9ba3f-4f28-4a72-83f5-627f8f709ea9))
     (instances

hardware/phase3-manager/bom/phase3-manager-bom.csv

@@ -18,7 +18,7 @@ Item,Qty,References,Value,Footprint,LCSC,MPN,Manufacturer,Unit USD,Ext USD,Note
 17,1,J4,UART,Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical,,,,,,
 18,1,J5,PANEL KEYS,Connector_PinHeader_2.54mm:PinHeader_1x09_P2.54mm_Vertical,,,,,,
 19,1,J6,ILI9341 LCD MODULE,Connector_PinHeader_2.54mm:PinHeader_1x14_P2.54mm_Vertical,,,,,,"ILI9341+XPT2046 2.8in module plugs here - AliExpress, confirm 3V3-VCC jumper"
-20,1,L2,33u/1.2A,Inductor_SMD:L_1210_3225Metric,,,,,,
+20,1,L2,33u/1.2A,Inductor_SMD:L_Changjiang_FNR5040S,C167973,FNR5040S330MT,cjiang (Changjiang Microelectronics),0.06,0.06,"5x5x4 mm shielded, KiCad L_Changjiang_FNR5040S land; Isat 1.30 A min covers the 33u/1.2A value. Any 5040-size 33 uH >=1.2 A part with the same 2.3 mm pad gap fits"
 21,3,Q8 Q9 Q10,2N7002,Package_TO_SOT_SMD:SOT-23,,,,,,
 22,1,Q11,AO3401A-class PMOS,Package_TO_SOT_SMD:SOT-23,,,,,,
 23,1,R50,100K 1%,Resistor_SMD:R_0603_1608Metric,,,,,,
@@ -36,4 +36,4 @@ Item,Qty,References,Value,Footprint,LCSC,MPN,Manufacturer,Unit USD,Ext USD,Note
 35,1,U11,TCAN1042HGV,Package_SO:SOIC-8_3.9x4.9mm_P1.27mm,C485806,TCAN1042VDRQ1,TI,0.57,0.57,"symbol value says TCAN1042HGV; SOURCING picked the V (VIO) variant, same SOIC-8 pinout"
 36,1,U12,TPD2E001,Package_TO_SOT_SMD:Texas_R-PDSO-N5_DRL-5,C150526,TPD2E001DRLR,TI,0.16,0.16,
 37,1,U13,TCA9535PWR,Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm,C130204,TCA9535PWR,TI,0.44,0.44,UMW clone acceptable here
-,80,,,,,,,,12.5,"10/80 placements have an LCSC number; total covers those only (qty-1, SOURCING.md 2026-07-18)"
+,80,,,,,,,,12.56,"11/80 placements have an LCSC number; total covers those only (qty-1, SOURCING.md 2026-07-18)"

hardware/phase3-manager/bom/phase3-manager-cpl.csv

@@ -4,8 +4,8 @@ C50,41.3500mm,-74.0000mm,Top,90
 C51,34.6500mm,-74.0000mm,Top,90
 C52,34.2000mm,-77.3000mm,Top,180
 C53,36.9000mm,-78.5000mm,Top,270
-C54,34.2000mm,-68.3000mm,Top,90
-C55,30.9000mm,-68.3000mm,Top,90
+C54,34.2000mm,-68.3000mm,Top,270
+C55,30.9000mm,-68.3000mm,Top,270
 C56,50.2000mm,-86.3000mm,Top,180
 C57,64.0000mm,-84.0000mm,Top,0
 C64,76.5000mm,-40.5000mm,Top,180
@@ -29,7 +29,7 @@ J3,82.0000mm,-94.8600mm,Top,0
 J4,98.5400mm,-66.0000mm,Top,90
 J5,80.1600mm,-66.0000mm,Top,90
 J6,86.5100mm,-60.0000mm,Top,90
-L2,38.0000mm,-70.0000mm,Top,90
+L2,38.8000mm,-68.4000mm,Top,90
 Q8,92.0000mm,-83.0000mm,Top,0
 Q9,97.0000mm,-83.0000mm,Top,0
 Q10,102.0000mm,-83.0000mm,Top,0

hardware/phase3-manager/bom/phase3-manager-jlcpcb.csv

@@ -18,7 +18,7 @@ USB-C,J3,USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal,C3020560
 UART,J4,PinHeader_1x03_P2.54mm_Vertical,
 PANEL KEYS,J5,PinHeader_1x09_P2.54mm_Vertical,
 ILI9341 LCD MODULE,J6,PinHeader_1x14_P2.54mm_Vertical,
-33u/1.2A,L2,L_1210_3225Metric,
+33u/1.2A,L2,L_Changjiang_FNR5040S,C167973
 2N7002,"Q8,Q9,Q10",SOT-23,
 AO3401A-class PMOS,Q11,SOT-23,
 100K 1%,R50,R_0603_1608Metric,

hardware/phase3-manager/drc-report.txt

@@ -1,22 +1,18 @@
-** Drc report for /home/claude/Lab_Bench/hardware/phase3-manager/tools/../phase3-manager.kicad_pcb **
-** Created on 2026-09-27 09:27:22 **
+** Drc report for /home/user/Lab_Bench/hardware/phase3-manager/tools/../phase3-manager.kicad_pcb **
+** Created on 2026-10-05 12:48:19 **
 
-** Found 5 DRC violations **
-[silk_overlap]: Silkscreen overlap
-    Rule: board setup constraints silk; Severity: warning
-    @(31.8000 mm, 71.9500 mm): Reference 'C54'
-    @(31.6000 mm, 74.0000 mm): Reference 'C51'
+** Found 4 DRC violations **
 [silk_overlap]: Silkscreen overlap
     Rule: board setup constraints silk; Severity: warning
     @(107.0000 mm, 69.5700 mm): Reference 'R79'
     @(107.0000 mm, 69.4300 mm): Reference 'R76'
 [silk_overlap]: Silkscreen overlap
     Rule: board setup constraints silk; Severity: warning
-    @(49.0000 mm, 29.5700 mm): Reference 'R70'
-    @(49.0000 mm, 29.4300 mm): Reference 'R69'
+    @(38.8000 mm, 71.9000 mm): Reference 'L2'
+    @(38.0000 mm, 72.3500 mm): Reference 'U8'
 [silk_over_copper]: Silkscreen clipped by solder mask
     Local override; Severity: warning
-    @(38.0000 mm, 72.0500 mm): Reference 'U8'
+    @(34.2000 mm, 64.6500 mm): Reference 'C54'
 [lib_footprint_mismatch]: Footprint 'LMR36015_RNX_VQFN-HR-12' does not match copy in library 'labbench'.
     Local override; Severity: warning
     @(38.0000 mm, 75.0000 mm): Footprint U8