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Xilinx Versal Gen2 ASU port: AES ciphers, CMAC, GMAC offload
- #10994
#10994
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JacobBarthelmeh
merged 4 commits into
wolfSSL:master
wolfSSL/wolfssl:master
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night1rider:Xilinx-ASU-Ciphers-CMAC-GMAC
night1rider/wolfssl:Xilinx-ASU-Ciphers-CMAC-GMAC
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Aug 10, 2026
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Xilinx Versal Gen2 ASU port: AES ciphers, CMAC, GMAC offload
#10994
JacobBarthelmeh
merged 4 commits into
wolfSSL:master
wolfSSL/wolfssl:master
from
night1rider:Xilinx-ASU-Ciphers-CMAC-GMAC
night1rider/wolfssl:Xilinx-ASU-Ciphers-CMAC-GMAC
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Commits
Commits on Aug 8, 2026
Xilinx Versal Gen2 ASU port: AES ciphers, CMAC, GMAC offload
night1rider
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8f5137c
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Xilinx Versal Gen2 ASU port: split AES-CTR at the 32-bit counter wrap and carry in software to keep it on hardware
night1rider
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0066461
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Xilinx Versal Gen2 ASU port: fold the one-shot CMAC input into the buffer at final
night1rider
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52d5698
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Xilinx Versal Gen2 ASU port: decline unsupported AES-GCM IV lengths to software
night1rider
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a08952b
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