Xilinx Versal Gen2 ASU port: AES ciphers, CMAC, GMAC offload - #10994
Xilinx Versal Gen2 ASU port: AES ciphers, CMAC, GMAC offload#10994night1rider wants to merge 4 commits into
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Fenrir Automated Review — PR #10994
Scan targets checked: wolfcrypt-port-bugs, wolfcrypt-rs-bugs, wolfssl-bugs, wolfssl-src
Findings: 3
3 finding(s) posted as inline comments (see file-level comments below)
This review was generated automatically by Fenrir. Findings are non-blocking.
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Fenrir Automated Review — PR #10994
Scan targets checked: wolfcrypt-port-bugs, wolfcrypt-rs-bugs, wolfssl-bugs, wolfssl-src
Findings: 2
2 finding(s) posted as inline comments (see file-level comments below)
This review was generated automatically by Fenrir. Findings are non-blocking.
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Fenrir Automated Review — PR #10994
Scan targets checked: wolfcrypt-port-bugs, wolfcrypt-rs-bugs, wolfssl-bugs, wolfssl-src
Findings: 3
3 finding(s) posted as inline comments (see file-level comments below)
This review was generated automatically by Fenrir. Findings are non-blocking.
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Fenrir Automated Review — PR #10994
Scan targets checked: wolfcrypt-port-bugs, wolfcrypt-rs-bugs, wolfssl-bugs, wolfssl-src
Findings: 3
3 finding(s) posted as inline comments (see file-level comments below)
This review was generated automatically by Fenrir. Findings are non-blocking.
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| /* Single-call generate (key, message and output all supplied). A whole-block | ||
| * message goes to the ASU; anything else runs in wolfSSL software. */ | ||
| if (info->cmac.key != NULL && info->cmac.out != NULL) { |
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There is a case where "key" could be NULL but both "in" and "out" are set. Looking through the conditions here I think that edge case would cause an incorrect CMAC tag to be created with the last input block not accounted for. Try with:
wc_InitCmac_ex()
wc_AesCmacGenerate_ex() // where 'key == NULL'
… and carry in software to keep it on hardware
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rebased off master to fix some CI test issues |
4 participants
Add AES, CMAC, and GMAC offload for Xilinx ASU port