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Phase-1 board: shrink to 100 × 80 mm, with the BOM's L1 and U7 lands - #9
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Placement, pours and pass-1 copper for the 100 x 80 board; routing to follow. Also corrects the Phase-1 F1 BOM note (direct-solder mini blade land). Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017ZrT5TjsLMQoxTZy1jabew
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017ZrT5TjsLMQoxTZy1jabew
Shrinks the module from 120 x 80 to 100 x 80 mm for JLCPCB's <=100 x 100 tier. The 120 x 80 layout stays on branch phase1-120x80. - Re-placed from the netlist, so L1 gets the 17 mm MWSA1707S/XAL1510 superset land and U7 the SC-70-5 land the BOM orders (the old board had XAL1350 and SOT-23-5 lands). - Output bank tightened round L1; R27 moved to the top strip. - R30, U4, U5 and the Kelvin pair moved as one block, same geometry. - Q3/Q4, J4 and the LTC7004 stack down the right edge; U6 now below the seam, so the AGND pocket is gone. - gen_board checks real courtyard polygons, not bounding boxes. - Routed: 0 unconnected, 0 DRC errors, 11 silk warnings. Fab zip, CPL and BOM regenerated; F1 BOM note corrected (direct-solder mini blade). Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017ZrT5TjsLMQoxTZy1jabew
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017ZrT5TjsLMQoxTZy1jabew
Freerouting ran VOUT_INT's FB run 0.25 mm past the SW island. fb_reroute.py rips it and re-routes with SW copper grown by 5.5 mm as a keep-out on every layer: now 52 mm, >= 5.56 mm from SW. DRC unchanged (0 errors, 11 silk warnings). Fab zip and CPL regenerated. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017ZrT5TjsLMQoxTZy1jabew
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September 27, 2026 12:30
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Sep 27, 2026
Conflict: the Phase-1 F1 BOM note. PR #9 made the same correction in its own wording, so this keeps development's text. The manager rows are unchanged; BOMs regenerated and bom.py --check passes. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01Ekhw9jYnrfxihP7yvxax5H
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Requested by Udara Vimarsha · project thread
Before: the Phase-1 module was 120 × 80 mm, above JLCPCB's ≤100 × 100 mm price tier. Its L1 land was the 13 mm XAL1350 and its U7 land was SOT-23-5, but the BOM orders the 17.2 mm Sunlord MWSA1707S-100MT (C5240401) and the SC-70-5 TLV7011DCKR (C193688). Neither ordered part would have fit.
After: the board is 100 × 80 mm and re-routed, with 0 unconnected and 0 DRC errors (11 silk warnings). It is generated from the netlist, so L1 gets the schematic's 17 mm MWSA1707S/XAL1510 superset land and U7 gets SC-70-5. The 120 × 80 layout is kept on branch
phase1-120x80.How
tools/fb_reroute.pyre-routes it with SW copper, grown by 5.5 mm, as a keep-out.gen_board.pynow checks real courtyard polygons, not bounding boxes. This removes 4 false overlaps the old check reported.tools/README.md: pass 1,fanout.py, Freerouting 1.9,finish_routes.py,fb_reroute.py, silk and planes, then DRC.🤖 Generated with Claude Code
https://claude.ai/code/session_017ZrT5TjsLMQoxTZy1jabew