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Phase-1 and phase-2 L2 (33u/1.2A aux-buck inductor) sat on 1210 lands, and no stocked 1210 33 uH is rated above 0.5 A. Both now use the manager's part, cjiang FNR5040S330MT (C167973, Isat 1.30 A min), on L_Changjiang_FNR5040S, as an ECO on each routed board: - phase-1: L2 at (32.6, 61.25); the SW_AUX diagonal is re-ended on the new pad and a 0.4 mm F.Cu 5V0 link joins L2's via to C54's. - phase-2: L2 at (68.4, 57.45) r270; its SW_AUX and 5V0 vias now sit in the pads, the two stubs that reached them are gone, and a 0.3 mm stub ties C55's 5V0 via to pad 2. - common/eco_swap_fp.py does the in-place footprint swap (nets, fields and path carried over). sheets_common.py, both gen_board.py PLACEMENT tables and the aux-rails sheets carry the change, so a rebuild matches. - DRC unchanged: phase-1 10 silk warnings, phase-2 19 warnings, 0 errors and 0 unconnected on both. Fab zips, BOMs and CPLs regenerated. The other CHECK rows (stock checked 2026-10-06): - Phase-1 C20/C75-C77: no 22 uF 50 V 1210 is stocked, so the design value is now 10u/50V X7R (~0.3 Vpp input ripple at 8 A, 350 kHz). - Phase-1 Q1-Q4: CSD18563Q5A still out of stock; NTMFS5C670NLT1G stays. Its case 488AA terminals land within 0.14 mm of the TI part's on the Q5A land. - Phase-2 U3: LM5143QRHARQ1 is the LM5143A-Q1, same pin map; RHA0040N matches the RHA0040P land (EP 3.3, 0.5 pitch, 5.8 span). No CHECK row is left in any BOM. INA228AQDGSRQ1 stock is down to 5, now on the order-early list. README, HANDOVER, SOURCING, the build guide and the tools READMEs are updated. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01Kap1Vqs6wqd3fshJdnERW7
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Requested by Udara Vimarsha · project thread
Before: Phase-1 and Phase-2 L2 sat on 1210 lands that no stocked 33 µH part can serve above 0.5 A, and four BOM rows were still marked
CHECK:waiting on a decision.After: both L2s use the manager's 5 × 5 mm FNR5040S330MT (C167973, Isat 1.3 A), and no
CHECK:row is left in any BOM.How:
hardware/common/eco_swap_fp.pyswaps a footprint in place, keeping nets and fields. Phase-1: L2 at (32.6, 61.25), SW_AUX stub re-ended on the new pad, a 0.4 mm F.Cu 5V0 link from L2's via to C54's. Phase-2: L2 at (68.4, 57.45) r270, the old SW_AUX/5V0 vias now sit inside the bigger pads, a 5V0 stub to C55's via.sheets_common.py, bothgen_board.pyPLACEMENT tables and the aux-rails sheets carry the change, and a freshgen_board.pyrun reproduces the positions.check_netlist/check_footprintspass on both. Fab zips, BOMs and CPLs are regenerated, andbom.py --checkpasses.🤖 Generated with Claude Code
https://claude.ai/code/session_01Kap1Vqs6wqd3fshJdnERW7
Generated by Claude Code