Docs: bring README, HANDOVER, SOURCING and guides up to date

README.md

@@ -65,20 +65,21 @@ firmware/
   tools/lbcan.py              Bench helper: build cansend frames, decode candump
 ```
 
-## Status (2026-09-27)
+## Status (2026-10-06)
 
-Nothing has run on silicon yet; the first board to be built is the Phase-1 module.
+Nothing has run on silicon yet; the first board to be built is the Phase-1
+module. v0.1.0 was released from `master` on 2026-09-29.
 
 | Area | State |
 |---|---|
 | Design docs | Complete: 01–10, plus the build guide (11) and Phase-1 bench test procedure (12) |
-| Phase-1 module (150 W) | Schematic verified and audited; **board routed, 0 unconnected, 0 DRC errors**, fab zip committed. Layout review fixes in PR #5. Next: settle the open BOM items (Q3/Q4 part, R30 shunt, the BOM `CHECK:` rows), then order and run [docs/12](docs/12-phase1-bench-tests.md) |
-| Phase-2 module (600 W) | Schematic verified and audited; board placed and pass-1 routed, **83 connections left** to finish by hand in KiCad |
-| Phase-3 backplane | Board fab-ready; gated on the XT60 polarity buzz-out ([MECHANICAL.md](hardware/MECHANICAL.md)) |
-| Phase-3 manager | Schematic verified; board placed, signal routing not started |
-| Module firmware | v0.1 builds (~6 KB, bare-metal STM32G431); control core host-tested |
+| Phase-1 module (150 W) | 100 × 80 mm, **routed, 0 unconnected, 0 DRC errors**, fab zip and CPL committed. OVP_TRIP routed to the MCU (PB4) for the firmware 0.2 OVP latch. Next: the owner picks the four Phase-1 BOM `CHECK:` rows, then order and run [docs/12](docs/12-phase1-bench-tests.md). The older 120 × 80 layout on branch `phase1-120x80` has wrong L1/U7 lands: do not order it |
+| Phase-2 module (600 W) | 130 × 90 mm, **routed, 0 unconnected, 0 DRC errors**, fab zip and CPL committed; pre-order review closed (HANDOVER) |
+| Phase-3 backplane | 330 × 100 mm, fab-ready; gated on the XT60 polarity buzz-out ([MECHANICAL.md](hardware/MECHANICAL.md)) |
+| Phase-3 manager | 100 × 80 mm, **routed, 0 unconnected, 0 DRC errors**; L2 moved to a 5 × 5 mm land (2026-10-05) |
+| Module firmware | v0.2 builds (~7 KB, bare-metal STM32G431) with the OCP backup and OVP latch; control core host-tested |
 | Manager firmware | v0.2 builds on ESP-IDF 5.3.2; manager, SCPI and UI cores host-tested |
-| BOM / sourcing | LCSC numbers in the schematics and per-board BOM CSVs (`hardware/common/bom.py`); five `CHECK:` part mismatches await a pick; generic R/C parts not yet numbered |
+| BOM / sourcing | LCSC numbers in the schematics and per-board BOM and CPL files (`hardware/common/bom.py`); five `CHECK:` rows await the owner's pick (four Phase-1, one Phase-2); generic R/C parts not yet numbered |
 | CI | GitHub Actions: host tests, module and manager firmware builds on every PR |
 
 Complete Phase-1 build (parts, five PCBs, stencil, shipping) ≈ US$100–125.

docs/09-phase3-circuit-design.md

@@ -174,19 +174,22 @@ header (generic 1×14).
 | MCU module | ESP32-S3-WROOM-1-N8R2 | quad PSRAM keeps IO35–37 (§3) |
 | I/O expander | TCA9535PWR (TSSOP-24) | 16 ch: PRESENT + keys |
 | USB ESD | TPD2E001DRLR | SOT-5X3 |
-| USB-C | 16-pin USB2.0 receptacle (GCT USB4105-class) | verify at sourcing |
-| Bus shunt | 250 µΩ ±1 % ≥8 W bolt/bar | WSBS8518-class, verify at sourcing |
+| USB-C | GCT USB4105-GF-A (C3020560) | picked 2026-09-28 to match the routed land; backup USB4105-GF-A-120 (C5184243) |
+| Bus shunt | 2 × BVS-M-R0005 (0.5 mΩ 3920, C466580) in parallel = 250 µΩ | chosen at sourcing (hardware/SOURCING.md); verify the power rating on the datasheet |
+| Backplane bulk C2 | Nichicon UCX1H471MNS1MS 470 µF 50 V SMD (C462700) | picked 2026-10-05, fits the CP_Elec_16x17.5 land; fallback Panasonic EEEFK1H471AM (C178551) |
+| Manager aux-buck L2 | cjiang FNR5040S330MT 33 µH (C167973) | 2026-10-05: 5 × 5 mm land, Isat 1.30 A; no stocked 1210 33 µH is rated above 0.5 A |
 | Display | 2.8" ILI9341+XPT2046 SPI module | off-the-shelf, header-mounted |
-| Encoder | EC11 w/ switch | panel part |
+| Encoder | Alps EC11E18244A5 (C255515) | EC11 with switch, panel part |
 | E-stop | NC mushroom switch (panel) | + shipped bench jumper |
 | P-FET | SOT-23 PMOS (AO3401A-class) | backlight switch, verify at sourcing |
 | Everything else | Phase-1/2 BOM carries over | |
 
 ## 6. Open items → resolve at capture / bring-up
 
-1. Backplane slot connector family — decided at the batch PCB pass
-   together with the module edge (docs/08 §12); schematic uses the same
-   generic 1×04 + 1×08 pair per slot.
+1. ~~Backplane slot connector family~~ — resolved at sourcing
+   (2026-07-18): Amass XT60PW-F per slot (XT60PW-M on the module) plus the
+   2.54 mm signal row. The XT60 polarity buzz-out (MECHANICAL.md) still
+   gates the backplane order.
 2. Encoder RC values + TCA9535 key debounce (firmware) **(bench)**.
 3. NCP1117 thermal under Wi-Fi soak **(bench)**, escape hatches in §3.
 4. Display module VCC jumper convention varies by vendor — confirm the

docs/11-build-guide.md

@@ -6,8 +6,8 @@ it up the first time without letting the smoke out. When the board passes the
 first power-up in §7, [docs/12-phase1-bench-tests.md](12-phase1-bench-tests.md)
 takes over and checks that it actually meets the spec.
 
-> **Read this first — honest status (2026-09-27).** Nothing in this repository
-> has run on real silicon yet. The Phase-1 board is routed and DRC-clean, the
+> **Read this first — honest status (2026-10-06).** Nothing in this repository
+> has run on real silicon yet. All four boards are routed and DRC-clean, the
 > firmware builds and passes its host tests in CI, but the first board has not
 > been built. You would be building alongside the project owner, not after a
 > proven design. Expect to debug; the bench-test doc is written with that in
@@ -17,10 +17,10 @@ takes over and checks that it actually meets the spec.
 
 | Board | What it is | Can you order it? |
 |---|---|---|
-| **Phase-1 module** (`hardware/phase1-module/`) | Single 150 W channel: 24 V in, 0–20 V / 0–8 A out, CAN controlled | **Yes, once PR #5 is merged** (layout review fixes, regenerated fab zip) and the parts in §3.3 are settled |
-| Phase-2 module (`hardware/phase2-module/`) | 600 W channel, 0–28 V / 0–30 A, hot-swap input | No. 83 connections are still unrouted |
+| **Phase-1 module** (`hardware/phase1-module/`) | Single 150 W channel: 24 V in, 0–20 V / 0–8 A out, CAN controlled | **Yes, once the parts in §3.3 are settled.** Order the 100 × 80 board on `development`/`master`; the 120 × 80 layout on branch `phase1-120x80` has wrong L1/U7 lands |
+| Phase-2 module (`hardware/phase2-module/`) | 600 W channel, 0–28 V / 0–30 A, hot-swap input | Routed and fab-ready (2026-09-27). Wait for Phase-1 to pass its bench tests (docs/05 exit criteria) and settle the U3 `CHECK:` row |
 | Phase-3 backplane (`hardware/phase3-backplane/`) | 8-slot bus with CAN, E-stop and bus metering | Fab-ready, but gated on the XT60 polarity check and only useful with Phase-2 modules and a manager |
-| Phase-3 manager (`hardware/phase3-manager/`) | ESP32-S3 with display, encoder, USB SCPI | No. Placement is done, signal routing is not |
+| Phase-3 manager (`hardware/phase3-manager/`) | ESP32-S3 with display, encoder, USB SCPI | Routed and fab-ready. Confirm the fab quotes 0.2 mm drilling on 2 layers; regenerate the order files if yours predate 2026-10-06 (L2 changed) |
 
 So today this guide is about the **Phase-1 module**. It is the "learning
 board": every risky part of the design (analog CV/CC loops, sensing,
@@ -29,7 +29,7 @@ cheap. §9 says what changes for the later boards.
 
 ## 2. Skills and tools
 
-The board is 4-layer, 120 × 80 mm, almost all SMD, and hand-assembled. The
+The board is 4-layer, 100 × 80 mm, almost all SMD, and hand-assembled. The
 hard parts are small leadless packages:
 
 | Part | Package | Why it is hard |
@@ -71,7 +71,7 @@ file. Upload the zip as is.
 | Setting | Value |
 |---|---|
 | Layers | 4 |
-| Size | 120 × 80 mm |
+| Size | 100 × 80 mm |
 | Thickness | 1.6 mm |
 | Copper | 1 oz outer (JLCPCB standard stackup `JLC04161H-7628` is what the design assumes) |
 | Stencil | Yes, top side |
@@ -126,9 +126,11 @@ tolerance matters in a few places:
 
 | Item | What to decide |
 |---|---|
-| **Q3, Q4 (output disconnect FETs)** | The BOM says only "60V NFET" on the 5 × 6 mm SON footprint. No part is pinned. The CSD18563Q5A used for Q1/Q2 fits the footprint and the 60 V rating (inferred from the footprint and docs/06, not yet checked against its gate-drive needs with the LTC7004) |
+| **Q1–Q4 (power and disconnect FETs)** | The CSD18563Q5A was out of stock on 2026-09-27; the BOM orders onsemi NTMFS5C670NLT1G (60 V, 6.1 mΩ, Qg 20 nC) with the same S-S-S-G / tab pinout. Confirm the pad overlay in the JLCPCB preview, or buy CSD18563Q5A if it is back |
+| **C20, C75–C77 (input ceramics)** | No 22 µF 50 V 1210 is stocked; the BOM orders 10 µF 50 V, which drops the input ceramic from 88 to 40 µF (C21 is the bulk). Accept it or source 22 µF elsewhere |
+| **L2 (5V0 aux buck inductor)** | The 1210 land only takes 33 µH parts rated about 0.5 A; the value asks for 1.2 A. Fine if the 5V0 load (fan included) stays well under ~0.4 A. A bigger 5 × 5 mm land, as on the manager, is an open option |
 | **R30 (2 mΩ shunt)** | The LCSC part (C2994640) is cheap but its TCR is unverified. The CC accuracy depends on it. A Vishay WSLP-class part (~US$1.50) is the safe choice |
-| **U8, U11 variants** | The BOM flags that the LCSC variants (LMR36015ARNXR, TCAN1042VDRQ1) differ from the symbol values. Both are the right function (adjustable buck, VIO-capable CAN transceiver); confirm the footprint |
+| **U8, U11 variants** | The LCSC variants (LMR36015ARNXR, TCAN1042VDRQ1) differ from the symbol values. Both are the right function (adjustable buck, VIO-capable CAN transceiver) in the same package |
 | **J1, J4 terminal blocks** | The footprint is a 5.0 mm Phoenix PT; SOURCING.md lists 5.08 mm 2EDG plugs. Buy a header that matches the 5.0 mm footprint |
 | **Order-early parts** | LTC7004EMSE had only 5 in stock at LCSC. Put it in the cart first |
 
@@ -177,7 +179,7 @@ is cheap; a short at 24 V is not.
 | J2 SWD | 1 = 3V3, 2 = SWDIO, 3 = SWCLK, 4 = NRST, 5 = GND | See the note on pin 1 below |
 | J3 UART | 1 = GND, 2 = TX (from MCU), 3 = RX (to MCU) | 115200 8N1, 3.3 V |
 | J5 BACKPLANE | 1 = CAN_H, 2 = CAN_L, 3 = HW_EN, 4–6 = SLOT_ID0–2, 7–8 = PGND | The bench harness plugs in here |
-| J6 FAN | 1 = +5 V, 2 = fan return (switched low side) | Small 5 V fan; keep it under ~200 mA, the 5 V rail is sized for 0.5 A total |
+| J6 FAN | 1 = +5 V, 2 = fan return (switched low side) | Small 5 V fan; keep it under ~200 mA. The 5 V rail is sized for 0.5 A total, and the 1210 L2 the BOM fits is rated about 0.5 A, so keep the whole 5V0 load under ~0.4 A (§3.3) |
 
 **J2 pin 1:** a genuine ST-Link only senses target voltage on this pin. Many
 clone ST-Link V2 dongles *drive* 3.3 V onto it, which then fights the board's
@@ -267,13 +269,15 @@ ADC sampling on the high-impedance V_MEAS divider, then the DAC80502 gain.
 - **Phase-2 module (600 W)** reuses the Phase-1 control, sensing, disconnect,
   aux and MCU blocks, with a 2-phase LM5143 power stage and LM5069 hot-swap
   input. Its assembly is the same as above plus heavier soldering on the power
-  stage. It becomes orderable when its last 83 connections are routed and the
-  BOM `CHECK:` items for the LM5143 land pattern and the 220 µF caps are
-  settled.
+  stage. The board is routed and the 220 µF caps are settled (EEHZA1V221P);
+  the one open BOM item is the LM5143 Q1-variant land check (U3), plus the
+  1210 L2 question that Phase-1 has too.
 - **Phase-3 backplane and manager** turn modules into a rack. Before ordering
   the backplane, mate one XT60PW-M/F pair and buzz out which pad connects to
   which, and which cavity is marked "+" ([hardware/MECHANICAL.md](../hardware/MECHANICAL.md)).
-  Pads 1 = + on both sides is still an assumption. The manager firmware builds
+  Pads 1 = + on both sides is still an assumption. The manager board is
+  routed; its order files changed on 2026-10-06 (L2 on a 5 × 5 mm land), so
+  use ones generated from `development` or later. The manager firmware builds
   in CI (`firmware/manager/idf`, ESP-IDF 5.3.2); its bring-up knobs are in
   [docs/10](10-manager-firmware.md).
 

docs/12-phase1-bench-tests.md

@@ -407,8 +407,8 @@ Setpoint 12 V / 4 A, load at 3 A.
 - 750 Ω: T_fet reads ≥ 100 °C, output off, FAULT `OTP` latched. With the
   resistor still fitted, `reset clear` must not leave the module running (the
   fault re-latches on the next tick). Remove the resistor, then `reset clear`
-  clears it. docs/04 says clearing needs < 70 °C; firmware 0.1 only re-latches
-  at ≥ 100 °C, so note the actual behaviour.
+  clears it. docs/04 says clearing needs < 70 °C; firmware 0.2 (like 0.1) only
+  re-latches at ≥ 100 °C, so note the actual behaviour.
 - Record the reported temperature, the bits, and the output current at each
   step.
 

hardware/LAYOUT.md

@@ -1,6 +1,6 @@
 # PCB layout guide — placement rules per board
 
-Status of layout work as of 2026-07-19, and per-cluster placement guidance for
+Status of layout work (table refreshed 2026-10-06), and per-cluster placement guidance for
 hand-layout in KiCad. Net names below are exactly as in the verified netlists
 (`check_netlist.py` green on phase-2 and backplane). Pin numbers were verified
 against the footprints + netlist, not memory.
@@ -9,14 +9,15 @@ against the footprints + netlist, not memory.
 
 | Board | Schematic | Netlist check | PCB |
 |---|---|---|---|
-| phase1-module | done | green | **done** — `phase1-module.kicad_pcb`: placement, pours, planes, critical routes, 0 DRC copper errors; some signal nets unrouted (autoroute.py is WIP) |
-| phase2-module | done (hand-arranged) | green (173 comps, 116 nets) | not started — this doc is the placement plan |
-| phase3-backplane | done | green (30 comps) | not started |
-| phase3-manager | done | green (80 comps, 86 nets) | **routed** 2026-09-27: 0 unconnected, 0 DRC errors (see `phase3-manager/tools/README.md`) |
+| phase1-module | done | green | **routed** 2026-09-27 at 100 × 80 mm: 0 unconnected, 0 DRC errors (see `phase1-module/tools/README.md`) |
+| phase2-module | done (hand-arranged) | green (173 comps, 116 nets) | **routed** 2026-09-27 at 130 × 90 mm: 0 unconnected, 0 DRC errors; the placement plan below is what was built |
+| phase3-backplane | done | green (30 comps) | **fab-ready** 2026-07-26: 0 unconnected, 0 DRC errors |
+| phase3-manager | done | green (80 comps, 86 nets) | **routed** 2026-09-27: 0 unconnected, 0 DRC errors; L2 moved to a 5 × 5 mm land 2026-10-05 (see `phase3-manager/tools/README.md`) |
 
 Phase-1's board is the reference implementation: open it next to this doc —
 every rule below is applied there and visible (input band → FET straddle →
-SW island → inductor → output band; the ground seam; the AGND pocket).
+SW island → inductor → output band; the ground seam. The 100 × 80 board has
+no AGND pocket: the LTC7004 cluster sits on the AGND side of the seam).
 
 ---
 

hardware/MECHANICAL.md

@@ -24,7 +24,7 @@ component + airflow:
 
 | Board | Size | Layers/copper | Notes |
 |---|---|---|---|
-| phase2-module | **130 × 90 mm** | 4-layer (stackup below) | grows from P1's 120×80 for hot-swap + 4 FETs; XT60PW-M + signal row on the bottom edge (power connector proud by ~2 mm for power-first mating) |
+| phase2-module | **130 × 90 mm** | 4-layer (stackup below) | grows from P1's original 120×80 for hot-swap + 4 FETs; XT60PW-M + signal row on the bottom edge (power connector proud by ~2 mm for power-first mating) |
 | phase1-module | **100 × 80 mm** (was 120 × 80; that layout is kept on branch `phase1-120x80`) | 4-layer | shrunk to fit JLCPCB's ≤100 × 100 mm tier; gets the same bottom-edge connector pair so it can plug the backplane too |
 | phase3-backplane | **~330 × 100 mm** | 2-layer 2 oz | 8 × 30 mm slots + end margins + manager header zone; M6 lug bolts at entry; bus rails solder-reinforced |
 | phase3-manager | **100 × 80 mm** | 2-layer 1 oz | display module on standoffs above (or panel-mounted via ribbon); encoder/keys wired to panel |