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Manager and backplane: add placement (CPL) files - #15

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Sep 29, 2026
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Requested by Udara Vimarsha · project thread

Before: only the Phase-1 and Phase-2 boards had JLCPCB placement files in the repo; the manager and backplane ones were generated just for the v0.1.0 release assets.

After: all four boards carry a bom/*-cpl.csv, generated with python3 common/cpl.py <board>.kicad_pcb from the boards merged in v0.1.0. No board file changed.

🤖 Generated with Claude Code

https://claude.ai/code/session_012vqeoXfZfZw2oZCwv9rjfw


Generated by Claude Code

Generated with common/cpl.py from the released boards, matching the
phase-1 and phase-2 CPL files, so all four boards ship the same order set.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_012vqeoXfZfZw2oZCwv9rjfw
@udaravima udaravima self-assigned this Sep 29, 2026
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udaravima marked this pull request as ready for review September 29, 2026 00:33
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udaravima merged commit 1c8e4ca into development Sep 29, 2026
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udaravima deleted the claude/release-prep-x5qsbu branch September 29, 2026 03:38
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