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Release v0.1.0: merge development into master - #14
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- C28 (PS_VIN 100n) moved onto U3 pin 20: pad 1 lands on the PS_VIN feed 0.85 mm from the pin, pad 2 in the PGND bar beside a PGND via. PS_VIN copper 24.8 -> 17.7 mm. - VBUS divider R60/R61/C62 moved from the far right edge to beside U10.14 (ADC), so the long run is the low-impedance VBUS_F side and C62 filters next to the pin. High-impedance VBUS_SNS copper 63.7 -> 19.3 mm; the VBUS_F feed to R60 is 79 -> 61 mm. - VOUT_INT FB sense run left as routed: 5.5 mm or more from SW copper on every layer, and its long end is the output side of the divider. - All part offsets folded into gen_board.py PLACEMENT (C25, C26, R3, R6 from the first pass, plus the moves above); fanout.py NUDGES is now empty. PLACEMENT matches every footprint on the board. New eco_move.py moves parts on the routed board and peels their old routes; finish_routes.py gains a fallback that joins the other islands first when the largest one is boxed in. DRC: 0 unconnected, 0 errors, same 9 silk warnings. Fab zip regenerated. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017ZrT5TjsLMQoxTZy1jabew
Pull requests already trigger CI whatever their base, so PRs into development are covered; this adds direct pushes to development. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01GayDV6JMjvVbsrqxsaLzXg
CI: also run on pushes to development
…efresh README status - docs/11-build-guide.md: ordering, assembly, J5 bench harness (HW_EN is pulled low on the board), firmware flashing and a staged first power-up. - docs/12-phase1-bench-tests.md: calibration and every docs/05 Phase-1 exit test, with the probe points the board actually has and two predicted gaps (OCP backup alert never configured; OVP does not disable EN or latch). - docs/test-results/phase1-results-template.md: record sheet. - firmware/tools/lbcan.py: builds cansend frames and decodes candump. - README: status table as of 2026-09-27, doc index, layout. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MJC8uRcPhk4YegfjYUhyuD
common/cpl.py writes <board>/bom/<board>-cpl.csv in JLCPCB's columns (Designator, Mid X, Mid Y, Layer, Rotation), in the gerbers' frame (page mm, Y up). Mid X/Y is the body centre from the Fab outline, so headers and terminal blocks are not placed on pin 1. Rotations are KiCad's, unmodified, to be checked in JLCPCB's placement preview. DNP parts are skipped by the same rule as bom.py, so the CPL and the JLCPCB BOM list the same 134 parts. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017ZrT5TjsLMQoxTZy1jabew
…fqpbq Build guide and Phase-1 bench test procedure
Q3/Q4 (output disconnect, 60 V NFET on the SON5x6 GDS land) get the same part as Q1/Q2: CSD18563Q5A, LCSC C77239, already verified in SOURCING.md for this footprint. The through-hole parts (J1-J6, F1) are marked hand-solder in the BOM notes. bom.py --check passes. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017ZrT5TjsLMQoxTZy1jabew
Fill the 109 missing Phase-1 placements from the JLCPCB catalogue (checked 2026-09-27, Basic parts where one fits), so 127 of 136 placements carry an LCSC number. J1-J6 and F1 stay hand-solder; C17 and R17 are DNP. Out-of-stock swaps: Q1-Q4 CSD18563Q5A -> NTMFS5C670NLT1G (SO-8FL, same pinout), P1 U5 INA228AIDGSR -> INA228AQDGSRQ1. Y1 moves to the CL = 12 pF version of the same crystal (C400090 was the 10 pF one). Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013uVohQZFdivAh43gw4mZtf
Phase-1 board: routing review fixes and JLCPCB assembly BOM
Hand-drawn locked copper for the USB pair (through U12 into J3), the CAN pair and the U8 buck power stage (route_critical.py), then Freerouting with B.Cu weighted expensive, phase-1's finish_routes with 2-layer settings, and PGND stitching between the two ground pours. PGND is now poured on both layers (3V3 runs as 0.4 mm tracks). Placement in gen_board.py was reworked against the netlist and U8 gets an IPC-size board-local courtyard. Fab outputs regenerated. phase1 finish_routes.py gains FILL_AROUND/B_COST hooks (defaults keep phase-1 behaviour), skips rule areas, and loads the base board first so LoadBoard no longer resets the project rules. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01KfJo5gk19gMQupM6RFmYmb
Route the phase-3 manager board
Placement, pours and pass-1 copper for the 100 x 80 board; routing to follow. Also corrects the Phase-1 F1 BOM note (direct-solder mini blade land). Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017ZrT5TjsLMQoxTZy1jabew
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017ZrT5TjsLMQoxTZy1jabew
Shrinks the module from 120 x 80 to 100 x 80 mm for JLCPCB's <=100 x 100 tier. The 120 x 80 layout stays on branch phase1-120x80. - Re-placed from the netlist, so L1 gets the 17 mm MWSA1707S/XAL1510 superset land and U7 the SC-70-5 land the BOM orders (the old board had XAL1350 and SOT-23-5 lands). - Output bank tightened round L1; R27 moved to the top strip. - R30, U4, U5 and the Kelvin pair moved as one block, same geometry. - Q3/Q4, J4 and the LTC7004 stack down the right edge; U6 now below the seam, so the AGND pocket is gone. - gen_board checks real courtyard polygons, not bounding boxes. - Routed: 0 unconnected, 0 DRC errors, 11 silk warnings. Fab zip, CPL and BOM regenerated; F1 BOM note corrected (direct-solder mini blade). Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017ZrT5TjsLMQoxTZy1jabew
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017ZrT5TjsLMQoxTZy1jabew
Freerouting ran VOUT_INT's FB run 0.25 mm past the SW island. fb_reroute.py rips it and re-routes with SW copper grown by 5.5 mm as a keep-out on every layer: now 52 mm, >= 5.56 mm from SW. DRC unchanged (0 errors, 11 silk warnings). Fab zip and CPL regenerated. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017ZrT5TjsLMQoxTZy1jabew
Phase-1 board: shrink to 100 × 80 mm, with the BOM's L1 and U7 lands
- ENC1: C2831776 was a 100 uF/50 V electrolytic, not an encoder. Now Alps EC11E18244A5 (C255515), the EC11E with push switch the footprint is for. - F1: C3207114 was a 6.35 mm cylindrical fuse clip. The land is a direct-solder MINI blade, so F1 is now the 2 A fuse itself, Littelfuse 0297002.WXNV (C151091). The Phase-1 F1 note is corrected the same way. - BZ1: MLT-8530 is rated 2.5-4.5 V but runs from 5V0. Now YX-SMD8530P (C781886), rated 2-5 V, with the same vendor land and pad-1 (+) corner. Schematic LCSC/MPN fields and BOM CSVs regenerated with common/bom.py. No footprint or layout change. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01Ekhw9jYnrfxihP7yvxax5H
Move C28 below U3 and the compensation cluster east of the NE B.Cu corridor so U3's control pins escape cleanly; hand-route the right-column lanes and the top-row via fan-out in route_board.py. Drop the old PS_VIN and PH_CS_B F.Cu corridors (now routed on In2). Port fanout.py and finish_routes.py (adds --inner In2 routing, --only, --first, --budget), and the phase-1 DSN export / SES import. Board file is regenerated and routed in a follow-up commit. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01CT7ZUC1wFK39SLj4Qnh9qy
Join U3 PGND pins 14/17 under the body and drop 17 into the pour; feed C22/C23 PS_VCC from a via between them. Escape VOUT2 (pin 5) west to In2. Turn C25 so COMP meets R24 directly and its AGND pad gets a pocket via. Gather U4/C31/C33 AGND on F.Cu to one via, link C33 5V0, and tie the output-cap PGND pads (C15/C47/C16) down to In1/B.Cu PGND. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01CT7ZUC1wFK39SLj4Qnh9qy
Conflict: the Phase-1 F1 BOM note. PR #9 made the same correction in its own wording, so this keeps development's text. The manager rows are unchanged; BOMs regenerated and bom.py --check passes. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01Ekhw9jYnrfxihP7yvxax5H
Manager BOM: fix ENC1, F1 and BZ1 part numbers
VOUT2 (pin 5) joins VOUT1 (pin 26) through the channel between U3's pad ring and exposed pad; COMP2 dives there on a 0.5 mm via. PGND pins 14/17 link outside the pad row with G_LS_B moved west of the link. RT1 gets its own AGND and NTC_FET vias; C25's AGND via moves to free the RES lane. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01CT7ZUC1wFK39SLj4Qnh9qy
The grid margin was 0.6 mm to the track centre, so a 0.3 mm power track landed 0.45 mm from Edge.Cuts against the 0.5 mm board-edge rule. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01CT7ZUC1wFK39SLj4Qnh9qy
… outputs Freerouting plus finish_routes closed all but EAI_INJ; CAN_TX's router copper fenced the MCU area, so it was stripped and re-routed after EAI_INJ. Silk, planes (PS-002 clear), DRC, gerbers/drill zip and the JLCPCB CPL are regenerated. Adds tools/README.md and strip_routes.py, and updates HANDOVER. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01CT7ZUC1wFK39SLj4Qnh9qy
The manager board's USB breakout is drawn to the USB4105 land, but the BOM listed the HRO TYPE-C-31-M-12, whose signal pads are 0.3 mm longer and whose shell stakes sit elsewhere. Dropping it onto the routed board gives 38 DRC errors round J3, so the part follows the copper instead: USB4105-GF-A, C3020560, held in JLCPCB assembly stock (1.1k) though LCSC retail shows none. USB4105-GF-A-120 (C5184243, 4.7k) is the backup. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_012vqeoXfZfZw2oZCwv9rjfw
U5 (phase-2) and the backplane U1 move to INA228AQDGSRQ1, the automotive grade Phase-1 already uses: same VSSOP-10 pinout and register map, in stock where the AIDGSR is not. C15/16/36/37 become Panasonic EEHZA1V221P (D10x10.2, 20 mOhm), which fits the CP_Elec_10x10.5 land; the old D8 pick did not, and SUNCON 35HVH220M+P is noted as the same-land fallback. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01CT7ZUC1wFK39SLj4Qnh9qy
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01CT7ZUC1wFK39SLj4Qnh9qy
Manager board: pick the USB-C part (GCT USB4105-GF-A)
Route the Phase-2 600 W module and generate fab outputs
Row 2: lb_core_ocp_sample latches OCP_BACKUP when the INA240 current (ADC, every 1 ms) exceeds 110 % of i_max, or the INA228 ALERT is low, for more than 5 ms with the output closed. ina228.c now programs SOVL to the same limit (1.25 uV/LSB at ADCRANGE=1) and DIAG_ALRT to transparent, active-low, per-conversion compare. Host-tested. Row 4: PB4 reads OVP_TRIP (TLV7011 output). Its EXTI4 rising edge sets PS_OFF and clears OUT_REQ within microseconds; the 1 ms tick latches OVP_HW, and re-latches after RESET while the comparator is still high. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01NmR2rbcK8CFj3PgzqsaRtW
The TLV7011 output only reached Q9 (disconnect), so an overvoltage opened the output but left the LM5145 running and nothing latched. OVP_TRIP now also goes to U10 pin 41 (PB4, a spare pin), where the firmware 0.2 EXTI handler kills EN and latches OVP_HW. Schematic: surgical edits (OVP_TRIP local labels -> global, PB4 no-connect -> OVP_TRIP label); gen_phase1.py / sheets_common.py mirror it (ovp_to_mcu param, EXPECTED_NETS). check_netlist and check_footprints pass. Board: 21 signal nets in the U10-U7 region ripped and re-routed with Freerouting 1.9 + finish_routes, fb_reroute rerun, three overlap stubs trimmed. DRC: 0 unconnected, 0 errors, 10 silk warnings (was 11). Fab zip regenerated; placement and BOM unchanged. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01NmR2rbcK8CFj3PgzqsaRtW
docs/04 matrix rows 2 and 4 and a design note on where the OVP latch lives; docs/07 pin map (PB4) and tick order; docs/12 bench-test predictions for rows 2 and 4 now expect a latch; HANDOVER firmware row. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01NmR2rbcK8CFj3PgzqsaRtW
Phase-1: close the OCP backup and OVP latch protection gaps (firmware 0.2 + OVP_TRIP to PB4)
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Requested by Udara Vimarsha · project thread
Before: master stopped at the CI workflow (#4), with the Phase-1 board at 120 × 80 mm and the manager, Phase-2 and backplane boards unrouted or without order files.
After: master carries all four routed boards with their fab, BOM and placement files, the Phase-1 protection fixes (module firmware 0.2), the build guide and bench tests, and CI on development pushes. This is the batch for the v0.1.0 release.
How: a merge commit of
development(#5 to #13) into master. There are no conflicts.🤖 Generated with Claude Code
https://claude.ai/code/session_012vqeoXfZfZw2oZCwv9rjfw
Generated by Claude Code