[JaxCalder]

Problem

The STM32F7 USART has no RX FIFO, so at 921600 baud a byte arrives every ~11 µs. The RX interrupt runs at dmosi's minimum priority, because it signals the ring's semaphore. When it ran late the byte was lost to an overrun: on the STM32F746G-DISCO console about 2 in 60 bytes sent back to back were lost.

Change

RX by DMA (src/port/stm32f7/port.c). A UART with an RX ring now receives into a circular 1 KiB DMA buffer:

• The buffer comes from the dma heap (dmod-boot's DTCM, uncached) when there is one. Otherwise it is Dmod_AlignedMalloc with the D-cache invalidated before reading.
• The USART's idle line and the DMA's half / end events drain it into the ring. The read position is taken from NDTR.
• The stream is leased from dmdma (dmdma_lease_*), from the two the UART can use (table rx_dma_map, RM0385). If neither is free, the UART receives by interrupt as before, with a warning.
• _set_interrupt_trigger keeps RXNE masked and IDLE on while DMA receives. _set_rx_ring(NULL) and _deinit stop the stream and free the buffer.
• New dependencies of the F7 port: dmdma@>=0.4, dmheap.

Ring size (configs/board/* for F7). The ring now holds what arrives while the reader is not scheduled. 256 bytes are 2.8 ms at 921600, and a reader behind a busy display thread overran it: the oldest bytes were dropped. The F7 boards' consoles get 4096 (~44 ms). See docs/configuration.md, section "Receiving by DMA".

Tested on STM32F746G-DISCO

• 20 × 200 bytes sent back to back to the console: 0 lost (2/60 lost before).
• After a burst and a pause, NDTR always matches the drained position: no bytes left in the DMA buffer (40 bursts of 1–2000 bytes).
• YMODEM (dmell's ymodem), 1024-byte blocks, no pacing: 8 × 300 KB with no block sent again, ~31 KiB/s.

Related

• Fix reads waiting for all data in the some-data mode dm_sw_ring#8: some_data reads waited for all the requested data. Readers of this ring need it to get bytes as they come.
• dmuart requires dmuart_port@>=1.1<2.0, so the port's release has to be at least 1.1.

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