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Openframe GPIO configurator - #14

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@marwaneltoukhy

@marwaneltoukhy marwaneltoukhy commented Sep 24, 2026 •

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Why

The wrapper configured its 44 pads with hand-written CF_gpio_config instances and generate loops. Changing the pinout meant editing pad-level Verilog, with no validation and no record of the pinout outside the RTL. cf-cli 2.7 adds a project.openframe spec and a generator (cf-cli PR). This template needs to consume that output and ship a spec that reproduces today's example.

What

  • Wrapper: openframe_project_wrapper.v instantiates the generated openframe_gpio module and wires the timer to its named ports (clk, rst, out[10:0]) instead of 44 hand-written CF_gpio_config instances.
  • Seed spec: .cf/openframe_default.json is seeded into .cf/project.json by cf init. It reproduces the timer pinout:
    • pad 0: input clk
    • pad 1: input with pull-up rst
    • pads 2-12: output out[10:0]
    • pads 13-43: analog (unused)
    • power: vccd1, with mprj on vccd1
  • Generated files, committed: verilog/rtl/openframe_gpio.v and openlane/openframe_project_wrapper/power.json.
  • Config and includes: openframe_gpio.v is added to the wrapper config.json and to the RTL includes, because both the flow and the simulation need the new module.
  • IP pin: ip/dependencies.json moves CF_gpio_config from v1.1.4 to v1.2.0, which adds the pad override parameters that the spec can set.
  • Timer fix: the trailing comma in the user_proj_timer.v port list is removed. iverilog and verilator reject it, which blocked lint and the equivalence check; yosys tolerated it.
  • README: documents the configure, generate and harden flow.

Testing

  • Formal equivalence: the old wrapper and the new wrapper plus openframe_gpio.v are formally equivalent. This used a yosys miter plus SAT with the timer macro cut out.
    • It holds with CF_gpio_config v1.1.4 and with v1.2.0.
    • The proof correctly fails on a deliberately mutated pad mode.
  • Simulation: a random comparison had 0 mismatches. It randomized pad inputs and the loopback constants and forced out[10:0].
  • Lint: verilator -Wall and iverilog -Wall are clean on openframe_gpio.v. The only wrapper warnings are for unused padframe ports.
  • Generate check: cf openframe generate --check passes against the committed generated files.

Follow-ups

  • CF_gpio_config v1.2.0 release: it is not released yet, and IPM needs the GitHub release asset and catalog entry. Until then, ipm install-dep fails because dependencies.json points to v1.2.0. The timer spec uses no overrides, so the RTL also works with v1.1.4.
  • power.json consumer: it is not read by the LibreLane 2.4.x flow on this branch. The PDN PR (stacked on this one) makes the wrapper consume it.

- openframe_project_wrapper.v instantiates the generated openframe_gpio module
  instead of hand-written CF_gpio_config instances.
- Add .cf/openframe_default.json (seeded by cf init) reproducing the timer
  pinout, plus the generated verilog/rtl/openframe_gpio.v and
  openlane/openframe_project_wrapper/power.json.
- Add openframe_gpio.v to the wrapper config and RTL includes.
- Bump CF_gpio_config to v1.2.0 (pad override parameters).
- Fix trailing comma in the user_proj_timer port list (rejected by iverilog).
- README: configure, generate and harden flow.

The refactored wrapper is formally equivalent to the previous one (yosys miter +
SAT, timer macro cut out) with both CF_gpio_config v1.1.4 and v1.2.0.
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