LibreLane 3 (CI2609) and native multi-domain wrapper PDN; remove bridge macros

[marwaneltoukhy]

Why

• Bridge macros: Power reached the core through two empty bridge macros, vccd1_connection and vssd1_connection, placed by macro.cfg and hooked in with FP_PDN_MACRO_HOOKS.
• Only one domain: Only vccd1/vssd1 worked, so users could not power a macro from vccd2 or the analog supplies.
• Workarounds: The bridges forced several workarounds:
  • LVS_FLATTEN on the bridge cells, with RUN_LVS: 0 on the wrapper
  • permissive DEF template matching and power-pin copy hacks
  • a user macro that had to match the wrapper's met4/met5 strap pitch
• Stale files: Legacy OpenLane 1 files (interactive.tcl, CustomApplyDEFTemplate) were still in the tree.
• New flow: The PDN now needs to be driven by the spec's power domains (power.json from cf-cli) and to build natively on LibreLane 3.

What

• LibreLane 3 migration.
  • Pin CI2609 (LibreLane 3.0.14) in openlane/Makefile.
  • config.json moves to meta version: 2 with the Classic flow, PDN_*, MACROS (in place of MACRO_PLACEMENT_CFG/EXTRA_*) and IO_PIN_ORDER_CFG. It loads with no deprecation warnings.
  • openlane/Makefile passes power.json before config.json. LibreLane has no config include and the last file's meta wins.
• Native PDN (pdn_cfg.tcl).
  • Builds one core ring per PDN net plus a met4/met5 mesh (3.1 µm straps at 180 µm pitch; 5 µm rings; 60 µm core inset, enough for 8 nets).
  • Adds a hook around pdngen:
    1. It marks the padframe power pins FIRM, because pdngen deletes non-FIXED pins. It errors if a PDN net has no pin.
    2. It grows the padframe signal pins 2 µm into the die. Without this, the LibreLane 3 router fails with DRT-1231 on 26 off-grid pins. The cf-precheck XOR only compares geometry outside the die.
    3. It blocks met4/met5 inside each macro's core ring during pdngen. Otherwise wrapper straps thread through holes in the macro abstract.
    4. It ties every padframe pin of each net to that net's ring with a met3 strap and a generated via array, and fails on any short.
  • check_power_grid then verifies pad → ring → mesh → macro.
• Why this approach (the spike tried all three candidates):
  • PDN_CORE_RING_CONNECT_TO_PADS only handles pad instance terminals, not block pins.
  • Plain pdngen cannot reach met3 pin stubs.
  • A Python LibreLane step in the fork would never reach Docker users, because --dockerized runs the upstream image.
• Step reorder: meta.substituting_steps moves Odb.ApplyDEFTemplate before OpenROAD.GeneratePDN, so the padframe power pins exist while the PDN is built. Strict template matching now works.
• User macros use the core-ring method. user_proj_timer is re-hardened with PDN_MULTILAYER and PDN_CORE_RING, so it no longer has to match the wrapper's strap pitch. The README documents the hierarchical method as an alternative.
• LVS isolation. Ground domains share the p-substrate, so flat extraction merged vssd1 and vssd2. The wrapper therefore uses MAGIC_EXT_ABSTRACT_CELLS: ["^user_proj_timer$"] (with macro netlists excluded), and the precheck LVS config uses EXTRACT_CREATE_SUBCUT. Each macro is LVS-checked when it is hardened.
• DRT_ANTENNA_REPAIR_ITERS: 0. The wrapper has no rails or taps, so router-inserted diodes caused nwell DRC and LVS errors. The old wrapper ran no antenna repair either.
• Removed:
  • all views of vccd1_connection/vssd1_connection (rtl, gl, lef, gds, mag, maglef, spi)
  • macro.cfg, interactive.tcl and CustomApplyDEFTemplate/
  • LVS_FLATTEN and permissive template matching
  • the bridge netlists in the LVS config
• LVS enabled: RUN_LVS: true on the wrapper.
• Resizer flags: the wrapper uses the LibreLane 3 names, and PL_RANDOM_GLB_PLACEMENT is dropped.
• Views: the wrapper and the timer are re-hardened, and the README documents the power flow.

Testing

Design	LibreLane 3.0.14 (Magic DRC / KLayout DRC / LVS / XOR / PDN / route DRC)	cf precheck (mpw_precheck:latest, cf-precheck 1.3.7, --magic-drc)
user_proj_timer	0 / 0 / 0 / 0 / 0 / 0	n/a
wrapper, vccd1	0 / 0 / 0 / 0 / 0 / 0	13/13 PASS, LVS "Circuits match uniquely", CVC 0

• cf-cli harden: cf harden openframe_project_wrapper --use-docker with cf-cli 2.7.1 gave the same clean signoff.
• pdnmulti: cf-precheck limits it to gf180 digital projects, so it did not run.
• Netgen log: it still prints "Top level cell failed pin matching" for layout-only pins (unused padframe supply copies). All LVS metrics are 0, and precheck LVS matches uniquely.

Follow-ups

• CI2609 tag: it must be created in chipfoundry/openlane-2 (see the openlane-2 PR). Until then, install LibreLane 3.0.14 locally or from PyPI.
• open_pdks pin: cf-cli versions.json pins 3e0e31dc…, which is not in the ciel releases. Verification used LibreLane 3.0.14's pinned sky130 8afc8346….
• Per-macro LVS lists: MAGIC_EXT_ABSTRACT_CELLS (wrapper config.json) and EXTRACT_CREATE_SUBCUT (lvs/openframe_project_wrapper/lvs_config.json) must name every user macro master, and MACROS must list the macro views and placement. The cf-cli generator could fill these if the spec recorded macro masters.
• vdda1/vdda2 signoff: these domains are not signed off. A PDN-only run with vccd1 + vdda1 tied all 14 pins with every net connected, but it has not been through full DRC, LVS and precheck.
• pdngen hook dependency: the hook relies on LibreLane's pdn.tcl calling pdngen after sourcing PDN_CFG, which is true in 3.0.14. Re-check this on upgrades.
• Timer slow-corner warnings: 25 max-slew and 1 max-cap warnings in the slow corner. There are no setup or hold violations, and precheck does not gate on timing.
• CF_gpio_config v1.2.0: it must be released (see the configurator PR, openframe_user_project Openframe GPIO configurator #14).