sha1-checked: implement hardware acceleration on arm64 and x86_64

[srijs]

re #909

Implements hardware acceleration for sha1-checked on both arm64 and x86_64 architectures.

Tried to take sha1 as an example and match how this works as best as possible (e.g. using cpufeatures and cfg-if). Let me know where you'd like me to adjust this.

In general, the way this works is by running the happy path via the specialized hardware instructions, and falling back to the scalar implementation only if a potential collision is detected.

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Measured with the crate's own bench suite:

	before	after	speedup
aarch64 (dedicated Apple Silicon)	928 MB/s	1996 MB/s	2.15x
x86_64 (AMD EPYC, sha_ni, cloud sandbox)	~300 MB/s	~640 MB/s	~2.1x

For comparison, performance relative to plain sha1 on the same backend, i.e. what fraction of un-checked SHA-1's speed detection reaches:

	scalar	hardware-accelerated
aarch64	64%	63%
x86_64 (sha_ni)	~55%	~38%

Note: On aarch64, hardware acceleration speeds up sha1 and sha1-checked by about the same factor, so the relative gap to plain SHA-1 barely moves. On x86_64 it doesn't, instead the gap actually widens (but of course still improving the absolute performance). My theory is that sha1's own SHA-NI backend gets more speedup than sha1-checked's fixed per-block bookkeeping (ubc_check, etc., which isn't accelerated) does.

[srijs]

This is existing code, moved over from compress.rs.