sha1-checked: hardware acceleration on arm64

[srijs]

Hi everyone!

For a project I'm currently working with sha1-checked and have integrated the hardware acceleration available on arm64 for about ~2.2-2.4x better performance compared to the baseline, and landing within ~25% of plain unchecked SHA-1.

The downside is that it needs a little bit of unsafe code around the core::arch::aarch64 instrinsics, as well as a bit more complexity due to the runtime feature detection and branching.

Would there be interest in me upstreaming these changes?

[newpavlov]

Could you share a repo with current code?

The downside is that it needs a little bit of unsafe code around the core::arch::aarch64 instrinsics, as well as a bit more complexity due to the runtime feature detection and branching.

Use of intrinsics themselves is safe on functions marked with appropriate #[target_feature(enable = "..")], we would still need unsafe to call such function, but it should be just one line. Though we would need to slightly bump MSRV for this.

Would there be interest in me upstreaming these changes?

Yes, but I think it's better to do after the new version is released (see #908).

[srijs]

Thanks for the response, @newpavlov!

Certainly happy to share the code, just wanted to see if there’s interest at all before putting in the work to clean up the code.

If you want me to bump msrv part of the change I’m happy to, alternatively what I usually do with crc32fast (which I maintain) is to do rustc version checks in build.rs and trigger a cfg feature based on that. Here’s an example.

I’ll go and prep a draft PR, will circle back shortly.

[srijs]

@newpavlov please find the PR here: #910.