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NUC126_ST_IRQ_PRIORITY defaulted to 8, out of range on the two priority bits of the Cortex-M0, and nothing checked it. Default it to 2 and stop the build when the ST or USB IRQ priority is out of range.
CLK_EnablePLL passed NO, NR and NF to CLK_PLLCTL in the wrong order, so PLLCTL got PD and OE set, the PLL never became stable and HCLK stayed on HIRC. CLK_SetCoreClock also switched HCLK to the PLL with divider 1, which with a running PLL gives twice the requested frequency, and CLK_PLLCTL_72MHz_HIRC selected HXT. Pass the arguments in the macro's order, use divider 2 as the BSP does, and select HIRC.
_pal_lld_setgroupmode set every mode other than input, push-pull and open drain to quasi-bidirectional, so PAL_MODE_INPUT_PULLDOWN and PAL_MODE_INPUT_ANALOG got a pull-up, and it wrote the mode before DOUT, so the pin was driven low while DOUT was 0. Map each mode explicitly: analog input uses input mode, DOUT is set before quasi mode, and pull-down, which the chip lacks, is ignored. Remove the PAL_MODE_NUC126_ALTERNATE_* values, which equal PAL_MODE_RESET to PAL_MODE_INPUT_PULLUP, and make PAL_WHOLE_PORT 0xFFFF instead of (2^16)-1. SystemCoreClockUpdate now takes the HXT frequency from NUC126_HSECLK when HSE is enabled instead of the fixed 12 MHz __HXT.
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A follow-on to @doombadroid's #454: three fixes to the NUC126 platform code, found while reviewing the port that runs QMK on a Ducky One 3 RGB keyboard (NUC1261SG4AE; qmk/qmk_firmware#26499). References: NUC126 TRM Rev 1.04 and Nuvoton's NUC126 BSP.
One commit per fix:
NUC126_ST_IRQ_PRIORITYof 8 is out of range on the Cortex-M0 (0–3) and becomes priority 0. The default is now 2, and an out-of-range ST or USB priority stops the build.stable-21.11.x). ST priority 8 and USB priority 4 give the#error.CLK_SetCoreClock.CLK_PLLCTLgot its arguments in the wrong order, which set PD and OE, so HCLK stayed on HIRC. Divider 1 would then give 144 MHz, andCLK_PLLCTL_72MHz_HIRCselected HXT. This is the HAL's default configuration.clk.c,clk.h.INPUT_PULLDOWNgot a pull-up. Each mode is now mapped; pull-down and unknown modes are ignored, as the PAL contract says.PAL_MODE_NUC126_ALTERNATE_*removed: unused, and equal toPAL_MODE_RESET…PAL_MODE_INPUT_PULLUP.PAL_WHOLE_PORTwas 0x11 (^is XOR); now 0xFFFF.SystemCoreClockUpdateusesNUC126_HSECLK, not the fixed 12 MHz__HXT.Both NUC126 testhal projects build without warnings. NUC123 (
TIMv1,GPIOv1) has the same code; I have no NUC123 hardware, so it's unchanged.I made the review and these patches with Claude Code, an AI coding agent. The tests ran on my keyboard.