Xilinx asu rsa standalone - #11052

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night1rider wants to merge 13 commits into

wolfSSL:masterfrom

night1rider:Xilinx-ASU-RSA-standalone

Commits on Aug 11, 2026

Xilinx Versal Gen2 ASU port: RSA offload
night1rider
committed
0ce2b19
Benchmark: RSA raw, PKCS#1 v1.5, PSS and OAEP across 2048/3072/4096
night1rider
committed
6d3f1ae
Xilinx Versal Gen2 ASU port: decline raw RSA input that is not the key width
night1rider
committed
53c6189
Xilinx Versal Gen2 ASU port: reject an RSA output buffer smaller than the key width
night1rider
committed
6c46a2c
Xilinx Versal Gen2 ASU port: auto-enable WOLF_CRYPTO_CB_RSA_PAD with the RSA engine
night1rider
committed
fc5306c
Xilinx Versal Gen2 ASU port: guard RSA private-key paths with WOLFSSL_RSA_PUBLIC_ONLY
night1rider
committed
e530e0c
Xilinx Versal Gen2 ASU port: return WC_HW_E on an RSA-PSS verify hardware fault
night1rider
committed
9c93780
Xilinx Versal Gen2 ASU port: correct the RSA scratch buffer comment
night1rider
committed
4b61f5f
Xilinx Versal Gen2 ASU port: decline RSA-OAEP messages larger than the OAEP capacity
night1rider
committed
f126e13
Benchmark: initialize outLen before wc_RsaDirect in bench_rsa_pad
night1rider
committed
5794d0a
Benchmark: guard bench_rsa_pad on WC_RSA_PSS and raw-RSA availability
night1rider
committed
14e8e13

Commits on Aug 12, 2026