Register Bank conflict fix

[jel221]

Performance improvement

MNK = 32x32
Operand bank conflicts (TCU): 0x280 => 0x100
PERF: instrs=3088, cycles=10596, IPC=0.291
PERF: instrs=3088, cycles=9661, IPC=0.320

MNK = 128x128
Operand bank conflicts (TCU): 0xa000=>0x4000
PERF: instrs=142864, cycles=534563, IPC=0.267
PERF: instrs=142864, cycles=405638, IPC=0.352

The remaining conflicts are unavoidable

Request if you want the perf counter code

mx meta registers do not seem to be used in the current RTL, so either

1. microops for future mx may need to be hardcoded
2. the current changes may need to be refactored

[tinebp]

Thanks for tracking this down, @jel221. The register-bank conflict this targets has since been fixed on master via the bank-conflict-free register permutation (bcfree/rb_idx) merged in e1e7715 from the wmma_fixes work, which permutes the B-fragment data→register mapping rather than shifting TCU_RB. The surrounding code has also moved (kernel header → sw/kernel/include/, SimX WMMA → macro-op sequencer), so this patch no longer applies. Closing as already-resolved — appreciated the catch.