SimX updates for VM support#304
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Bring in latest docs, to update in this branch
Toggle the RISC-V Vector Extension on and off
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workaroud fix for opencl kernel include in POCL
regression fix
- Add TLB configuration parameters to VX_config.vh (TLB_SIZE, TLB_LINE_SIZE, etc.) - Create TlbSim wrapper around CacheSim for TLB modeling - Integrate TLB into CacheCluster with manual request/response flow - Implement pending request tracking using HashTable - Add internal ports (tlb_req_ports_, cache_rsp_ports_) for pipeline staging - Performance impact: ~75% more cycles, 43% IPC reduction with VM enabled Tested: Both VM_ENABLE and non-VM modes pass blackbox tests
…odeling - Create ptw.h: Simplified sequential page table walker - Sequential PT walks: One walk at a time (no complex MSHR) - Multi-level support: PT_LEVEL memory accesses (2 for SV32, 3 for SV39) - Correct VPN extraction and PTE address calculation per level - Each PTE read goes through memory/cache hierarchy (realistic timing) - Simple 2-state FSM: IDLE -> READING_PTE (per level) -> IDLE - Integrate PTW into TlbSim between TLB and memory Performance impact vs no-VM: - Baseline (no VM): 12,086 cycles, IPC 0.356 - With VM + PTW: 33,764 cycles (+179%), IPC 0.128 - Realistic VM overhead modeling with sequential PT walks Code: 185 lines (vs 310 in complex version), much simpler and clearer
- Add physical address return parameter to MemoryUnit read/write functions - Enhance PTW with proper SATP base PPN tracking and traversal logic - Improve TLB integration with set_satp() method for SATP propagation - Refactor cache_cluster.h for cleaner VM request handling - Update system integration for physical address tracking throughout pipeline Total: 15 files changed, +281 insertions, -108 deletions
- Fix PTW memory request tag handling: initialize next_mem_tag_ to 1 to prevent duplicate requests for tag 0 - Remove duplicate memory access counter increment in PTW issue_pte_read - Simplify PTW perf_stats() method to directly return perf_stats_ member - Update cache cluster to properly aggregate PTW performance statistics - Update VX_config.vh and VX_types.vh with TLB and PTW related definitions - Update runtime utils to properly read and report PTW performance counters - Improve emulator and socket handling for TLB/PTW operations All changes verified with performance counter validation: - PTW walks correctly tracked - PTW memory accesses show perfect 2.0 ratio per walk (2-level page table) - TLB hit/miss statistics properly reported
SimX changes for VM support
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Thanks @Tachyon01 for this work. SimX VM support has since landed on This PR targets |
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