Route the phase-3 manager board

[udaravima]

Requested by Udara Vimarsha · project thread

Before: the ESP32-S3 manager board (hardware/phase3-manager) had its parts placed, but about 173 connections were still unrouted and there were no fab outputs.

After: the board is fully routed in KiCad 7 format, with 0 unconnected items and 0 DRC errors (drc-report.txt), and phase3-manager-fab.zip has been regenerated.

How. The routing reuses the Phase-1 pipeline. It is documented in hardware/phase3-manager/tools/README.md and runs in four passes:

1. route_critical.py hand-draws locked copper for three things. The USB pair is 0.25/0.2 mm, coupled, and runs through the U12 ESD clamp into J3. The CAN pair runs from J1 to U11. The LMR36015 buck gets its hot loops, SW, 5V0 trunk and VBUS_F.
2. export_dsn.py feeds headless Freerouting with freerouting.rules. B.Cu costs 4-6x F.Cu, so B.Cu stays a ground plane with short jumpers.
3. Phase-1's finish_routes.py runs with two-layer settings.
4. stitch.py adds 283 PGND vias between the two ground pours.

Placement lives entirely in gen_board.py PLACEMENT. No later pass moves a part.

Phase-1's finish_routes.py gains FILL_AROUND and B_COST hooks. Their defaults leave phase-1 behaviour unchanged. It also skips rule areas now, and it loads the base board first, because loading it second reset the .kicad_pro rules to defaults.

Review before ordering

• The USB-C part is still an open owner decision. The J3 breakout is drawn for the USB4105 land pattern, so a different connector means redrawing the last few mm of the pair.
• Ground is now PGND on both layers. It was a 3V3 plane on F.Cu before. 3V3 draws under 0.5 A and runs as 0.4 mm tracks.
• The USB pair is not length-perfect. Skew is about 4.9 mm (DP 69.4 mm, DN 74.3 mm). 13 slow nets cross under the pair on B.Cu. Both are acceptable at full speed (12 Mbit/s). CAN crosses once, at J1.
• The buck has a jumper under U8. VBUS_F reaches C51 through an 18 mm, 0.6 mm B.Cu jumper along its south side. U8 uses a board-local IPC-size courtyard, which causes the one lib_footprint_mismatch warning.
• Four silk warnings remain (3 reference overlaps and the U8 reference over copper). They are cosmetic.
• U10 has 12 thermal vias at 0.2 mm drill. The fab's minimum drill still needs checking.
• There is a 0.8 mm² ground sliver at J3 A1/B12. Those pads are tied to the shell by a track, so this is advisory only.
• Freerouting is not deterministic. A rerun gives a different result that is also DRC-clean.

🤖 Generated with Claude Code

https://claude.ai/code/session_01KfJo5gk19gMQupM6RFmYmb

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Generated by Claude Code