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sysprog21
shecc
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Replace the SSA middle end with VIR
- #344
#344
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jserv
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Oct 15, 2026
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Replace the SSA middle end with VIR
#344
jserv
merged 20 commits into
master
sysprog21/shecc:master
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new-ir
sysprog21/shecc:new-ir
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Commits on Oct 11, 2026
Fix malloc chunk reuse and libc error checks
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Reach every RISC-V call beyond JAL range
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Share ELF header serialization
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Add standalone VIR core with verifier
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Commits on Oct 12, 2026
Compile all targets through native VIR
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Recover native throughput on x64 and ARM64
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Remove quadratic scans from VIR compilation
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Shrink branches, frames and edge copies
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Document VIR and the native pipeline
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Fold the phase 2 IR into VIR's machine layer
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Drop redundant and legacy VIR tests
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Cut peak memory of self-compilation
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Reject invalid declarations and runaway nesting
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Index VIR lookups and rank pin candidates once
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Remove dead code and signed shift overflow
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Shorten loop chains and weight pins by loop depth
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Commits on Oct 14, 2026
Shrink ARM64 code and align short loops
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Shrink x86-64 code and align small loops
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Commits on Oct 15, 2026
Halve the compiler's peak memory
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Keep parameters of loops no entry reaches
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