[#941] NVIC: Correct ICSR RETTOBASE behavior

[PhysicistJohn]

Related issue

Fixes renode/renode#941

Description

Corrects the read-only ICSR.RETTOBASE bit for Armv7-M and Armv8-M Mainline cores.

After this PR was opened, master independently implemented RETTOBASE in bd7f752f. That implementation counts only active SystemException values, so it ignores active external interrupts (exception numbers 16 and above). This version counts the complete active exception stack: the bit is set for zero or one active exception and clear for nested active exceptions.

Cortex-M0, Cortex-M0+, Cortex-M1, and Cortex-M23 keep bit 11 at zero. Armv6-M reserves the field, and Armv8-M Baseline does not implement it without the Main Extension.

The explicit model check is needed because Renode currently exposes Armv7 compatibility features for the Cortex-M0 family.

Regression tests cover zero, one, and two active external interrupts.

Usage example

The reproduction from renode/renode#941 reports bit 11 set for an idle Cortex-M4 NVIC. A native matrix also verifies every currently supported Cortex-M model.

Additional information

Validated on macOS Arm64 with .NET 8:

• targeted NVICTests: 3 passed, 0 failed
• full headless Release build: succeeded with 0 errors
• full managed solution: 1,115 passed, 17 existing skips, 0 failures
• scoped dotnet format --verify-no-changes on both changed files: passed
• native Cortex-M0/M0+/M1/M23/M3/M4/M4F/M7/M33/M52/M55/M85 matrix: passed; bit 11 is zero on M0/M0+/M1/M23 and set for the remaining idle models

[CLAassistant]

All committers have signed the CLA.