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Document the CPHA=0 inter-frame gap in spi_set_format() - #3285
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With CPHA=0 the PL022 pulses chip select high and idles for 1.5 SCK periods between frames, even with a full TX FIFO, so sustained throughput is data_bits / (data_bits + 1.5) of the SCK rate. Measured with DMA on an RP2350: 84.21% (8-bit) and 91.43% (16-bit) at 9.4 to 75 MHz, against 100% with CPHA=1.
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Hello developers, just a heads up
The
spi.hdocuments how chip select behaves with CPHA=1 (the notes added after #3141), but not that CPHA=0 costs throughput. This adds a\notetospi_set_format().With CPHA=0 the PL022 returns to idle between frames, even when the TX FIFO never empties. It pulses SSPFSSOUT high between words, as described in the PL022 documentation and discussed in #941. It also leaves 1.5 SCK periods between consecutive frames, so sustained throughput is
data_bits / (data_bits + 1.5)of the SCK rate. With CPHA=1, frames go back to back.These are the measurement summary with setup
Setup: an RP2350 (Pico 2) with
clk_sys=clk_peri= 150 MHz, SPI0 TX only. DMA from RAM paced by the TX DREQ, so the CPU can't starve the FIFO. 64 KiB per run, timed untilspi_is_busy()clears. Efficiency is the wire time (bits ÷ SCK) over the measured time.The gap works out to exactly 1.50 SCK periods per frame at every clock: 8/9.5 = 84.21%, 16/17.5 = 91.43%. CPOL makes no difference.
I measured this on the RP2350 only. The RP2040 has the same PL022, so I'd expect the same result, but I haven't run it there.
In practice: ST7789 displays sample on the rising edge in both mode 0 and mode 3. Driving one in mode 3 cut the full-screen 320×240 transfer from 39.1 ms to 33.0 ms at 37.5 MHz, which was enough to keep 24 FPS video with room to spare.
Test program (Pico SDK, prints CSV over USB serial)
measure()is exactly what produced the table above. The original started each run when the host sent a byte; this version simply starts once USB is connected.