Cortex-M: Support avg_pool2d ceil_mode lowering#21039
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Cortex-M avg_pool2d quantized lowering rejected ceil_mode=True and left the graph on the fallback aten.avg_pool2d path. That preserved correctness but prevented optimized Cortex-M lowering for cases that CMSIS-NN can execute from statically known output shapes. This patch threads ceil_mode through the cortex_m::quantized_avg_pool2d schema, fake implementation, lowering, and C++ kernel wrapper. The wrapper validates the static output shape against ceil-mode pooling semantics before dispatching to CMSIS-NN. The avg_pool2d tests now cover optimized ceil_mode lowering, padded ceil_mode, count_include_pad with ceil_mode, non-square multi-channel ceil_mode, and divisor_override fallback behavior. Signed-off-by: Baris Demir <baris.demir@arm.com> Change-Id: Ib856e7cc0cc4a29ec6ede7d379b03ef7a98cb12f
🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/21039
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rascani
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Jul 20, 2026
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Can we add a test case with kernel_size =< stride with count_include_pad & ceil_mode? I think we might wind up with the wrong output size in that case: H=5, kernel=3, stride=3, pad=1, ceil_mode=True, count_include_pad=True
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Cortex-M avg_pool2d quantized lowering rejected ceil_mode=True and left the graph on the fallback aten.avg_pool2d path. That preserved correctness but prevented optimized Cortex-M lowering for cases that CMSIS-NN can execute from statically known output shapes.
This patch threads ceil_mode through the cortex_m::quantized_avg_pool2d schema, fake implementation, lowering, and C++ kernel wrapper. The wrapper validates the static output shape against ceil-mode pooling semantics before dispatching to CMSIS-NN.
The avg_pool2d tests now cover optimized ceil_mode lowering, padded ceil_mode, count_include_pad with ceil_mode, non-square multi-channel ceil_mode, and divisor_override fallback behavior.
cc @digantdesai @freddan80 @per @zingo @oscarandersson8218 @mansnils @Sebastian-Larsson @robell @rascani