Rebase/cache refactoring onto main#20
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- wire DataPartSplit/folded params through cluster/group/tile - implement skewed folded data SRAM mapping in cachepool_tile - adjust cluster wrapper tb for the new configuration
- add scalar cache tests that run basic and stress patterns without crossing 128-bit parts - add vector cache tests that use RVV loads/stores on 128-bit chunks and verify data integrity - integrate both tests into the test CMake and keep patterns aligned to folded-cache part size
Select a single part per column/bank per cycle and prioritize write parts over read parts to avoid clobbering bank signals.
- cachepool_tile: use EffectiveCoalFactor=1 in folded mode; pass to cache ctrl. - cachepool_cc: size Spatz response FIFO with NumSpatzOutstandingLoads; add overflow assert. - tcdm_cache_interco: add non-synthesis outstanding scoreboard/asserts for req/rsp matching.
…he access interleaving.
Bump insitu-cache to the folded/hash-way revision, thread UseHashWaySelect through cluster/tile, and queue Spatz memory responses through the local response FIFO instead of bypassing write acks.
cachepool_cc: per-port sb_q[user.req_id] slot table for out-of-order rsp matching; watchdog dumps stuck ids. Gated by parameter (default off, +define+ENABLE_SPATZ_REQ_SCOREBOARD to enable).
The skew-bank arbiter at (col, bank_sel) picks writes over reads without exposing the loser; a hardwired l1_data_bank_gnt=1 caused the upstream to consume stale rdata when another way wrote the same column. Compute any_other_write_in_col (loop-free, depends only on part_we) and gate gnt by it: writes always granted, reads granted iff no OTHER way writes the same (col, bank_sel). Excludes own way's writes so own idle words aren't spuriously stalled. Fixes multi-core coherence in rlc-mimic and unlocks AllowReadDuringWrite=1 on data banks.
- l1cache: flush+wait before xbar commit so the reconfig doesn't leave dirty lines bound to the old hash layout. - mcs-lock: move cluster barrier before the non-zero-core spin loop (otherwise cores 1+ never barrier and core 0 deadlocks). - load-store: print the correct buffer name (B/C, not A) in the B/C error messages; add c_ptr to the pointer dump. - idotp-32b: include got/expected in Check Failed! print.
…rw} tests Register five new cache-focused tests in CMakeLists.txt: - cache-line-rw-smoke single-core line-granular RW smoke - cache-rlc-mimic RLC traffic mimic (vector load/store) - cache-vector-rw multi-iteration vector load-store kernel - cache-coverage 12-phase multi-core cache stress / coverage - cache-coverage-min minimal phase-06 writeback-loss repro
- Bender.lock: bump insitu-cache to the rev with the wrapper/coalescer SBs and the SYNC_CTRL_CHECK_PEND fix. - Makefile: define ENABLE_SPATZ_REQ_SCOREBOARD so the in-RTL Spatz req/rsp watchdog is on by default. - cachepool_tile.sv: per-port pre-strip TCDM req tracer (+sb_pretrace_addr_lo/hi) and byte-granular shadow-memory model (+mm_enable) that $errors on DATA / TYPE / ORPHAN_RSP mismatches. Both passive, off by default, sim-only.
- config.mk: derive axi_user_width as base + 2*(idx_width(num_tiles)-1). Previous widths truncated bank_id MSB on the AXI loopback, routing cache_ctrl refill responses to the icache bypass slot. - cachepool_group.sv: use the source tile id `t` (not target_tile) for the request destination slot, so the response (routed by user.tile_id mod NumRemotePortCore) lands on the same xbar mst port as the request.
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