feat: add Kunlunxin XPU support - #289
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loveleaves wants to merge 4 commits into
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loveleaves wants to merge 4 commits into
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added 4 commits
September 17, 2026 20:34
Introduce the XPU platform (inherits GPU for the cuda-alike route), detect it via xpu-smi, and neutralize torch's native Intel-XPU stub through ensure_xpu_compat(). Provide a device-UUID fallback chain for vLLM (current_platform -> xpu-smi -q Bus Id -> xpu-smi -L UUID -> sha1).
Ray cannot autodetect XPUs (no nvidia-smi), so register the cuda-alike GPU count through ray.init(num_gpus=N) instead of the resources= dict, which rejects the reserved 'GPU' key.
Direct ProcessGroupNCCL deadlocks on XPU when ranks share a local device index. XCCLCheckpointEngine exchanges (host, local_dev_idx) via the store, builds a stateless ProcessGroupXCCL, and relays colliding ranks over TCP sockets. Manager/mixin route XPU to this engine.
Add user-facing XPU-Support guide (EN/ZH) and XCCLCheckpointEngine docs, register them in the toctrees, and list Kunlunxin XPU in the hardware and checkpoint-engine tables.
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Summary
Adds Kunlunxin XPU (P800) support to Twinkle via the cuda-alike route (
torch_xmlirrewritestorch.cuda, BKCL mounted as thenccl/XCCL backend). TheXPUplatform inherits fromGPU, so most GPU code paths work unchanged; only a few CUDA-specific assumptions are adapted.Commits follow the adaptation order:
XPUplatform,xpu-smidetection,ensure_xpu_compat, vLLM device-UUID fallback)ray.init(num_gpus=N))XCCLCheckpointEnginefor weight sync (statelessProcessGroupXCCL+ relay for duplicate local device indices)XCCLCheckpointEnginedocs, toctree/hardware/engine tables)Verified on P800 (single-host, 8-card)
enforce_eager=True, text models)merge_and_sync=True), relay ~0.7 GB/sKnown limitations (vendor stack, not Twinkle)
enforce_eager=True)XCCLCheckpointEnginemulti-host not yet validated (single-host relay verified)See
docs/.../XPU-Support.mdfor details.