ComputerArchitectureProject-CPU

A CPU made with Verilog code and schematic files using Quartus II, with RISC architecture and Pipe line data path

Name		Name	Last commit message	Last commit date
Latest commit History 52 Commits
db		db
greybox_tmp		greybox_tmp
incremental_db		incremental_db
output_files		output_files
simulation		simulation
src		src
work		work
.gitignore		.gitignore
ADDER_SUB.bsf		ADDER_SUB.bsf
ADDER_SUB.qip		ADDER_SUB.qip
ADDER_SUB.v		ADDER_SUB.v
ADDER_SUB_bb.v		ADDER_SUB_bb.v
ALU-schematic.pdf		ALU-schematic.pdf
CMP.bsf		CMP.bsf
CMP.qip		CMP.qip
CMP.v		CMP.v
CMP_bb.v		CMP_bb.v
CPUProject.bdf		CPUProject.bdf
CPUProject.qpf		CPUProject.qpf
CPUProject.qsf		CPUProject.qsf
DIV.bsf		DIV.bsf
DIV.qip		DIV.qip
DIV.v		DIV.v
DIV_bb.v		DIV_bb.v
FP_DIV.bsf		FP_DIV.bsf
FP_DIV_altfp_div_oul.bsf		FP_DIV_altfp_div_oul.bsf
FP_DIV_altfp_div_pst_39j.bsf		FP_DIV_altfp_div_pst_39j.bsf
JUMP_ADDER.bsf		JUMP_ADDER.bsf
LICENSE		LICENSE
MULT.bsf		MULT.bsf
MULT.qip		MULT.qip
MULT.v		MULT.v
MULTIPLEXER.bsf		MULTIPLEXER.bsf
MULT_bb.v		MULT_bb.v
PC_ADDER.bsf		PC_ADDER.bsf
README.md		README.md
ROTATE.bsf		ROTATE.bsf
ROTATE.qip		ROTATE.qip
ROTATE.v		ROTATE.v
ROTATE_bb.v		ROTATE_bb.v
SHIFT.bsf		SHIFT.bsf
SHIFT.qip		SHIFT.qip
SHIFT.v		SHIFT.v
SHIFT2.bsf		SHIFT2.bsf
SHIFT_bb.v		SHIFT_bb.v
and_two.bsf		and_two.bsf
co-processor-schematic.pdf		co-processor-schematic.pdf
control_unit.bsf		control_unit.bsf
instructionMemoryInstructions.hex		instructionMemoryInstructions.hex
instruction_interpreter.bsf		instruction_interpreter.bsf
pc.bsf		pc.bsf
register_array.bsf		register_array.bsf
schematic.pdf		schematic.pdf
sign_extender.bsf		sign_extender.bsf
xor_two.bsf		xor_two.bsf
zero_extender.bsf		zero_extender.bsf
پروژه درس معماری کامپیوتر.pdf		پروژه درس معماری کامپیوتر.pdf

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