Issues

• For loops in Nmigen

  m-labs/nmigen#350 · Filter by author ParasVekariya opened on Sep 4, 2022

• No clk being generated

  m-labs/nmigen#349 · Filter by author mayank-kabra2001 opened on Dec 30, 2021

• Want to know some details of the back

  m-labs/nmigen#346 · Filter by author ekikun opened on May 27, 2021
  1

• Improve readability of assignments and add contexts for clock domains

  m-labs/nmigen#345 · Filter by author ildus opened on Apr 5, 2021

• Signal decoder inference for Enums doesn't work for Layout members

  m-labs/nmigen#333 · Filter by author shawnanastasio opened on May 26, 2020

• lambdasoc analysis & synthesis got error on intel platform.

  m-labs/nmigen#331 · Filter by author franz-git opened on May 21, 2020

• Generating async negedge reset

  m-labs/nmigen#329 · Filter by author tariqafzal opened on May 15, 2020

• Hierarchical Redundancy in emitted Verilog

  m-labs/nmigen#328 · Filter by author BracketMaster opened on May 6, 2020
  1

• Installation fails if wheel not installed

  m-labs/nmigen#323 · Filter by author alanvgreen opened on Apr 3, 2020
  3

• hdl.ast.Value.word_select() works incorrectly on actual platform (ECP5 Versa)

  bug
  m-labs/nmigen#310 · Filter by author ghost opened on Jan 23, 2020
  5

• Support Platforms that include an existing design and expose interface to that design as Resource

  feature
  m-labs/nmigen#308 · Filter by author smunaut opened on Jan 19, 2020

• Add EnableSignal, useful for making Instances compatible with EnableInserter

  feature
  m-labs/nmigen#285 · Filter by author Fatsie opened on Dec 25, 2019 · 0.2
  21

• Find solution to translate values to strings for Symbiyosys vcd files

  improvementupstream
  m-labs/nmigen#254 · Filter by author XekriRedmane opened on Oct 14, 2019
  19

• Windows Batch is horrible; PowerShell is nicer

  improvement
  m-labs/nmigen#252 · Filter by author emilazy opened on Oct 13, 2019
  1

• A tutorial

  improvement
  m-labs/nmigen#247 · Filter by author XekriRedmane opened on Oct 12, 2019
  2

• Reliable installation on Windows

  improvement
  m-labs/nmigen#244 · Filter by author whitequark opened on Oct 3, 2019

• Specifying logical signal direction for ports of an elaboratable

  feature
  m-labs/nmigen#243 · Filter by author Ravenslofty opened on Sep 30, 2019
  1

• Reconsider simulator interface

  backend:simulatorimprovement
  m-labs/nmigen#228 · Filter by author whitequark opened on Sep 23, 2019 · 0.2
  42

• Memory with async read ports can synthesize to a BRAM on Xilinx platforms

  improvementplatform:xilinx-7seriesplatform:xilinx-spartan-3/6
  m-labs/nmigen#218 · Filter by author whitequark opened on Sep 20, 2019

• r_data is undefined after a simultaneous write to an empty AsyncFIFO

  bugplatform:all
  m-labs/nmigen#217 · Filter by author whitequark opened on Sep 20, 2019
  1

• Memory port transparency model is flawed

  bugupstream
  m-labs/nmigen#216 · Filter by author whitequark opened on Sep 20, 2019
  6

• flow graph analysis and automation

  feature
  m-labs/nmigen#213 · Filter by author jordens opened on Sep 20, 2019
  13

• Enhancing the FSM sub-language

  improvement
  m-labs/nmigen#206 · Filter by author whitequark opened on Sep 14, 2019
  12

• ASIC support tracking issue

  improvement
  m-labs/nmigen#184 · Filter by author whitequark opened on Aug 22, 2019
  3

• Reconsidering AsyncFIFO and resets

  improvement
  m-labs/nmigen#180 · Filter by author whitequark opened on Aug 22, 2019
  7