[rstmgr,dv] Reset Manager DV ported to mocha#506
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martin-velay
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| - files_rtl | ||
| - files_dv | ||
| default_tool: vcs | ||
| default_tool: xcelium |
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This is the source of your issue with the src file being not generated. The .src file is your file list generated from FuseSoc. I know that confusing, I went into this trap earlier too.
The VCS backend generates a .scr file, which is an identical format to a more standard .f format. We are only running FuseSoc up to the point it generates the filelist file (.scr in this case).
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| // Wait till rst_lc_n is inactive for non-aon. | ||
| `DV_WAIT(cfg.rstmgr_vif.resets_o.rst_lc_n[1]) | ||
| // Wait till rst_por_aon_n is inactive for non-aon. | ||
| `DV_WAIT(cfg.rstmgr_vif.resets_o.rst_por_aon_n[1]) |
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I think this should be the same reset as the one fed into the reset manager block in the top which is rst_por_io_n
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In rstmgr.sv line 351 constant zero is assigned to it:
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Probably makes sense to switch rst_*lc* with rst_por_io_n everywhere (and Marno agrees as well).
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Okay, but then it is DomainAonSel right?
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rst_lc_n[1] -> rst_por_io_n[1] so this is going to be Domain0Sel?
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Yes, DomainAonSel is 0, Domain0Sel is 1.
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marnovandermaas
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marnovandermaas
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Some comments from my end.
| - `CASCADED_ASSERTS(CascadeLcToLc, rst_lc_src_n[rstmgr_pkg::Domain0Sel], | ||
| - resets_o.rst_lc_n[rstmgr_pkg::Domain0Sel], SysCycles, clk_main_i) | ||
| - | ||
| - // Controlled by rst_sys_src_n. |
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There are a few resets controlled by SYS SRC in Mocha, such as rst_{main,io,spi_device,spi_host,i2c}_n
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It would be good to investigate whether we should have cascade asserts for those.
| else: | ||
| assert 0, "No preferred clock available" | ||
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| -preferred_rst_n = f"rst_lc_{preferred_domain}_n" |
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Can't we just update the preferred domain? This also fixes the power on reset preference below.
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Is it ready to be re-reviewed? |
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KinzaQamar,
elliotb-lowrisc,
marnovandermaas and
martin-velay
Yes it is ready for a final review. |
I think I had a similar issue which was resolved by rebasing onto the latest origin/main |
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Some notes for reviewers: As we don't have Lifecycle control in Mocha, all the relevant LC related resets are replace with the following mapping: LC related Cascaded Asserts are removed from For |
| `CASCADED_ASSERTS(CascadeSysToIO_A, rst_sys_src_n[rstmgr_pkg::Domain0Sel], | ||
| resets_o.rst_io_n[rstmgr_pkg::Domain0Sel], PeriCycles, clk_io_i) | ||
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| `CASCADED_ASSERTS(CascadeSysToSpiHosts_A, rst_sys_src_n[rstmgr_pkg::Domain0Sel], |
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Replace CascadeSysToSpiHosts_A with CascadeSysToSPIHost_A as SPI is a abbreviation and there is only one SPI Host
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@engdoreis / @machshev Do you know what is wrong with the |
It's because the nix app that computes the bitstream hash is failing with the following error: fusesoc --cores-root=. run --target=synth --setup lowrisc:mocha:chip_mocha_genesys2
ERROR: Failed to resolve dependencies. Conflicting requirements:
Requirements: 'lowrisc_mocha_chip_mocha_genesys2 == 0-0' <- 'lowrisc_prim_xilinx_all >= 0-0'
+lowrisc_mocha_chip_mocha_genesys2-0-0 was ignored because it depends on missing packages
Requirements: 'lowrisc_mocha_chip_mocha_genesys2 == 0-0'
Install command rule (+lowrisc_mocha_chip_mocha_genesys2-0-0)I opened a PR improving the logs. |
And how could be the root problem resolved? |
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Sorry @KolosKoblasz-Semify, I meant to reply to your comment, no edit it. I'll try to revert it. Here is my comment:
Looks like it is because the Xilinx prims got removed by commit 771b9f0 of this PR |
| // Primitives. | ||
| {from: "hw/ip/prim", to: "ip/prim", patch_dir: "prim"}, | ||
| {from: "hw/ip/prim_generic", to: "ip/prim_generic"}, | ||
| {from: "hw/ip/prim_xilinx", to: "ip/prim_xilinx", patch_dir: "prim_xilinx"}, |
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Your issue might come from here, why have you deleted this line?
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* open titan specific paths changed to mocha specific ones in the template files * 0001_Fix_Paths_And_Tools.patch file created with the changes * rstmgr_cascading_sva_if.sv.tpl updated with new domain names Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>
* The patched config and template config files added to the source code Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>
* rstmgr added to hw/top_chip/dv/mocha_sim_cfgs.hjson Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>
* 0002 patch fixes the auto generated reset manager's dv files therefore enabling block level simulations to be run Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>
* These modifications will enable to run block level simulations on rstmgr while using correct reset signals and domains in the UVM tb. Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>
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* These modifications will enable to run block level simulations on autogenerated rstmgr while using correct reset signals and domains in the UVM tb. * Both source and testbench files regenerated Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>
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6 participants
This PR ports Reset Manager Controller DV code from Opentitan to Mocha.
This PR will address: #433 --- Close #433
Project specific tests:
dvsim hw/top_chip/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson -i all --cov
Test Results
Coverage Results
Coverage Dashboard
Failure Buckets
UVM_FATAL (rstmgr_leaf_rst_cnsty_vseq.sv:159) [rstmgr_leaf_rst_cnsty_vseq] Timeout waiting for alert fatal_cnsty_faulthas 26 failures:0.rstmgr_leaf_rst_cnsty.3893774066561404286679873924707946454294933251846102894542716694214554564731
Line 105, in log /home/kkoblasz/projects/mocha/scratch/kk_rst_mgr_dv/rstmgr.sim.xcelium/0.rstmgr_leaf_rst_cnsty/latest/run.log
2.rstmgr_leaf_rst_cnsty.112716547968608135960797656090285886938387398042950550123403654793875186327527
Line 107, in log /home/kkoblasz/projects/mocha/scratch/kk_rst_mgr_dv/rstmgr.sim.xcelium/2.rstmgr_leaf_rst_cnsty/latest/run.log
... and 24 more failures.
[ legend ]: [S: scheduled, Q: queued, R: running, P: passed, F: failed, K: killed, T: total]
00:01:14 [ build ]: [S: 000, Q: 000, R: 000, P: 002, F: 000, K: 000, T: 002] 100%
00:02:38 [ run ]: [S: 000, Q: 000, R: 000, P: 594, F: 026, K: 000, T: 620] 100%
00:03:12 [ cov_merge ]: [S: 000, Q: 000, R: 000, P: 001, F: 000, K: 000, T: 001] 100%
00:03:19 [ cov_report ]: [S: 000, Q: 000, R: 000, P: 001, F: 000, K: 000, T: 001] 100%
Top level tests:
dvsim hw/top_chip/dv/mocha_sim_cfgs.hjson --select-cfgs rstmgr -i smoke --cov
Test Results
Coverage Results
Coverage Dashboard
TOP_MOCHA_BATCH_SIM Simulation Results (Summary)
Tuesday May 26 2026 08:04:01 UTC
Github Revision:
351f095Branch: kk_rst_mgr_dv
00:00:06 [ build ]: [S: 0, Q: 0, R: 0, P: 2, F: 0, K: 0, T: 2] 100%
00:00:08 [ run ]: [S: 0, Q: 0, R: 0, P: 3, F: 0, K: 0, T: 3] 100%
00:00:11 [ cov_merge ]: [S: 0, Q: 0, R: 0, P: 1, F: 0, K: 0, T: 1] 100%
00:00:16 [ cov_report ]: [S: 0, Q: 0, R: 0, P: 1, F: 0, K: 0, T: 1] 100%