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Fix SM90 WY input buffer reuse before WGMMA completion - #130
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The dq, dw, and dk inter-chunk loops release their current input pipeline stages while the newest WGMMA group may still be reading shared memory. The first iteration skips the wait entirely; subsequent iterations use wait_group(1), which permits the current group to remain outstanding. A producer can then overwrite an input stage before its consumer finishes.
Wait for all outstanding WGMMA groups with wait_group(0) before these three releases. Preserve the existing h-buffer lifetime across dq/dw, and update the now-stale overlap comment. This conservative fix sacrifices some overlap between V iterations to make stage reuse safe; it does not change the output epilogue handshake or backward intra kernel.
Validation: Python syntax, Ruff lint/format, and git diff --check passed. The equivalent fix was previously exercised on H200 with CuTeDSL 4.6.2–4.8.0 as part of a broader synchronization patch; GPU tests have not been rerun on this public-tree port. No claim is made that this alone resolves every previously observed dq discrepancy.
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