Fix for 130437#130534
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Pull request overview
This PR adjusts ARM64 JIT codegen for the “base + large imm” address materialization helper so the generated add is encodable when the base register is SP (which cannot appear as the third operand in the register form of add).
Changes:
- Swap the operand order of the register-form
addininstGen_Set_Reg_To_Base_Plus_ImmsoSP(when used) is placed in the encodable operand position. - Add an explanatory comment about the
SPoperand restriction for the encoding.
Comment on lines
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| instGen_Set_Reg_To_Imm(size, dstReg, imm); | ||
| GetEmitter()->emitIns_R_R_R(INS_add, size, dstReg, dstReg, baseReg); | ||
| // baseReg might be SP, which must be reg2 | ||
| // an "add R0, R1, SP" is not encodable | ||
| GetEmitter()->emitIns_R_R_R(INS_add, size, dstReg, baseReg, dstReg); | ||
| } |
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Assertion failed 'isGeneralRegister(reg3)' in jitstress-random.
STRESS_SPLIT_TREES_RANDOMLYforced both a mask and a 4096b struct into locals that get spilled.Hit assertion when we try to spill the mask to [SP+4120]. 4120 isn't encodable for a predicate store, so we need
instGen_Set_Reg_To_Base_Plus_Imm. This tried to create an add where SP was the last operand - this is not allowed to be encoded.Fix to swap the order of the operands on the add. We get this now: