Implement production dmsdio driver for STM32F4/F7 with 64-bit block I/O #4

Objective

Deliver a production SD memory stack for SDSC, SDHC, and SDXC cards on STM32F4/SDIO and STM32F7/SDMMC, including full 64-bit access, DMA, interrupts, hot-plug, error recovery, documentation, packaging, and real-hardware validation.

This issue is the tracking epic. Implementation details and acceptance criteria live in the stage issues below.

Stages

Repository setup

• [dmsdio 0/9] Add the dmsdio repository to dmod-ecosystem #5

Shared foundations

These can proceed independently:

• [dmsdio 1/9] Introduce 64-bit dmdrvi 2.0 and core file offsets #6
• [dmsdio 4/9] Correct STM32 CLK48 generation and expose peripheral clock frequency #9
• [dmsdio 5/9] Add centrally arbitrated DMA leases to dmdma #10

Ecosystem migration

Start after #6:

• [dmsdio 2/9] Migrate dmfsi, dmvfs, and dmdevfs to 64-bit I/O #7
• [dmsdio 3/9] Migrate all existing dmdrvi implementations to API 2.0 #8

Driver implementation

• [dmsdio 6/9] Implement the SD memory protocol and dmdrvi device model #11 — depends on [dmsdio 1/9] Introduce 64-bit dmdrvi 2.0 and core file offsets #6, [dmsdio 4/9] Correct STM32 CLK48 generation and expose peripheral clock frequency #9, and [dmsdio 5/9] Add centrally arbitrated DMA leases to dmdma #10
• [dmsdio 7/9] Implement STM32F4 SDIO and STM32F7 SDMMC ports #12 — depends on [dmsdio 4/9] Correct STM32 CLK48 generation and expose peripheral clock frequency #9, [dmsdio 5/9] Add centrally arbitrated DMA leases to dmdma #10, and [dmsdio 6/9] Implement the SD memory protocol and dmdrvi device model #11

Validation and release

• [dmsdio 8/9] Validate dmsdio automatically and on STM32F4/F7 hardware #13 — depends on [dmsdio 2/9] Migrate dmfsi, dmvfs, and dmdevfs to 64-bit I/O #7, [dmsdio 3/9] Migrate all existing dmdrvi implementations to API 2.0 #8, [dmsdio 6/9] Implement the SD memory protocol and dmdrvi device model #11, and [dmsdio 7/9] Implement STM32F4 SDIO and STM32F7 SDMMC ports #12
• [dmsdio 9/9] Publish the coordinated release and registry integration #14 — final coordinated release and integration

Scope

Included:

• SDSC v1/v2, SDHC, and SDXC memory cards
• 1-bit and 4-bit buses
• default-speed and High-Speed operation
• STM32F407G-DISC1 with an external microSD breakout
• STM32F746G-DISCO on-board microSD
• dmdrvi 2.0 and end-to-end 64-bit VFS access
• centrally managed DMA and correct CLK48 generation
• automated and real-hardware tests

Excluded:

• SDIO I/O cards
• MMC/eMMC
• FAT or another filesystem implementation

Global definition of done

• Every stage issue is closed.
• Both target boards pass the complete hardware matrix.
• SDXC I/O above 4 GiB works through the device filesystem.
• No required path contains a stub, TODO, silent fallback, or unverified hardware assumption.
• A clean environment installs and builds the released modules through standard DMOD tooling.