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Make cf verify work and add a timer test for the example design - #15
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- Add a cocotb test for the example 7-segment timer that checks the reset display and the seconds digit counting from 0 to 1. - Add the user_proj_tests lists that `cf verify --all` expects, plus cocotb_tests.py so the runner can find the tests. - Fix hello_world to import from caravel_cocotb. - Replace the stale RTL include list (PicoSoC files) with the real sources, and fill in the empty GL include lists. - Drop the trailing comma in user_proj_timer's port list, which Icarus Verilog rejects. - Ignore the generated sim/ output and design_info.yaml. - README: explain the cf init link/create choice and how cf verify --all picks its tests. Co-authored-by: Cursor <cursoragent@cursor.com>
Pin CF_gpio_config to v1.1.0, the latest version in the IP index. v1.1.4 is not published there, so ipm installed nothing and LibreLane failed looking for the missing RTL. Fail the job if that file is absent. Install caravel_cocotb from caravel-sim-infrastructure and pass --openframe, so CI runs the cocotb tests instead of compiling Caravel firmware. Co-authored-by: Cursor <cursoragent@cursor.com>
v1.1.4 is published on the ChipFoundry catalog. CI was forcing the GitHub verified_IPs.json, which only lists v1.1.0, so the install failed. Drop --local-file and keep the v1.1.4 dependency. Co-authored-by: Cursor <cursoragent@cursor.com>
The RTL job compiles CF_gpio_config.v but never installed it, so Icarus aborted and reported a missing caravel_top. Co-authored-by: Cursor <cursoragent@cursor.com>
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cf verify --allexpects, plus cocotb_tests.py so the runner can find the tests.