cranelift: don't emit FEAT_FP16 instructions without the feature, and support f16 in the interpreter

[dsecurity49]

Two f16 fixes for AArch64, plus interpreter support so f16 can be tested.

f16 arithmetic on AArch64 was emitting half-precision instructions without FEAT_FP16, which are UNDEFINED (Arm ARM, C7.2.73 FCVT). fadd.f16 on plain target aarch64 compiled to fadd h0, h0, h1 and trapped at run time. Adds a ty_scalar_float_with_fp16 extractor mirroring the RISC-V Zfh gate, makes the four fma constructors partial so the negated forms report instead of panicking, and lowers fcopysign.f16 in integer registers, which previously panicked.

The interpreter only handled F32/F64, so test interpret failed on f16 and fuzzgen had no oracle for it. Adds Ieee16::to_f32 and from_f32_rne/from_f64_rne, with fma widening to f64 so the exact product and sum survives.

Includes precise-output filetests for the new lowerings, and test interpret on the f16 runtests.

[github-actions]

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cc @avanhatt, @cfallin, @fitzgen, @mmcloughlin

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