atomic: hwspinlock backend for cxd56, rp2040, lc823450 - #19868
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please split the PR in separate PRs
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Use irq-based critical sections instead of spinlock_irq to avoid potential deadlock in atomic contexts. Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
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| #include <stdint.h> | ||
| #include <nuttx/irq.h> | ||
| #include <nuttx/macro.h> | ||
| #if defined(CONFIG_LIBC_ATOMIC_HWSPINLOCK) |
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where you add LIBC_ATOMIC_HWSPINLOCK?
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done， now in libc/machine/kconfig file
🔗 Cross-repo PR dependenciesThe read-only Build run reported the following dependent PR(s) and fetched head SHA(s): CI run: https://github.com/apache/nuttx/actions/runs/32701216081 |
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❌ Cross-repo dependency could not be appliedThe Build report says the declared dependency PR(s) could not be applied, so CI did not run against the combined code: Reason: cherry-pick failed (if your PR has merge commits, rebase instead) CI run: https://github.com/apache/nuttx/actions/runs/32726917623 |
Add hardware spinlock driver implementations for cxd56, rp2040, and lc823450 chips. These drivers provide the hwspinlock_ops_s interface used by the atomic hwspinlock backend. Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Implement atomic_lock/atomic_unlock using hwspinlock when CONFIG_LIBC_ATOMIC_HWSPINLOCK is selected, and using up_irq_save/ up_irq_restore when CONFIG_LIBC_ATOMIC_IRQ is selected. Rename arch_atomic_irq.c to arch_atomic.c. The 64-bit atomic operations use spinlock (spin_lock_irqsave) regardless of the selected backend, ensuring multi-core safety. Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Add per-chip atomic hwspinlock device definitions for cxd56, rp2040, and lc823450. Replace CXD56_TESTSET with CXD56_ATOMIC_WITH_HWSEM which selects LIBC_ATOMIC_HWSPINLOCK. RP2040: Cortex-M0+ no atomic, IRQ for non-SMP, hwspinlock for SMP. CXD56XX: CXD56_USE_SYSBUS controls hwsem usage in SMP. LC823450: toolchain supports atomic, hwspinlock optional for SMP. Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
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Summary
Add hwspinlock-based atomic backend for multi-core capable chips:
LIBC_ATOMIC_HWSPINLOCKis selectedarch_atomic_irq.cback toarch_atomic.cwith combined IRQ + hwspinlock implementationThis PR depends on #19867 (multi-backend framework + builtin + API rename).
Stacked PR chain
Depends on #19867. This is PR 3 of 3:
Test
testbuild across RP2040/CXD56XX/LC823450