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asavonic merged 1 commit into from
Jul 2, 2026
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[dxsa][mlir] Port LIT tests from dxilconv #196

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37 changes: 37 additions & 0 deletions mlir/test/Target/DXSA/asm/call2.test
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// RUN: mlir-translate --import-dxsa-bin %S/inputs/call2.shex | FileCheck %s
// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py


// CHECK-LABEL: dxsa.dcl_global_flags <refactoringAllowed>
// CHECK: dxsa.dcl_input_ps linear v<0, <x>>
// CHECK: dxsa.dcl_input_ps constant v<1, <x, y, z>>
// CHECK: dxsa.dcl_output o<0, <x>>
// CHECK: dxsa.dcl_temps 1
// CHECK: dxsa.mov r<0, <x, y, z>>, v<1, <x, y, z, z>>
// CHECK: dxsa.call label<0>
// CHECK: dxsa.callc_nz r<0, <x>>, label<0>
// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32}
// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32}
// CHECK: dxsa.instruction "switch" %[[OPERAND_0]]
// CHECK: dxsa.case l(0x1)
// CHECK: dxsa.call label<2>
// CHECK: dxsa.callc_nz r<0, <y>>, label<1>
// CHECK: dxsa.break
// CHECK: dxsa.default
// CHECK: dxsa.callc_nz r<0, <z>>, label<2>
// CHECK: dxsa.break
// CHECK: dxsa.case l(0x2)
// CHECK: dxsa.break
// CHECK: dxsa.endswitch
// CHECK: dxsa.add o<0, <x>>, r<0, <x>>, l(0x3F800000)
// CHECK: dxsa.ret
// CHECK: dxsa.label label<0>
// CHECK: dxsa.mov r<0, <x>>, l(0x40A00000)
// CHECK: dxsa.ret
// CHECK: dxsa.label label<1>
// CHECK: dxsa.mov r<0, <x>>, v<0, <x>>
// CHECK: dxsa.ret
// CHECK: dxsa.label label<2>
// CHECK: dxsa.mov r<0, <x>>, l(0x40400000)
// CHECK: dxsa.ret

42 changes: 42 additions & 0 deletions mlir/test/Target/DXSA/asm/cs3.test
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// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs3.shex | FileCheck %s
// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py


// CHECK-LABEL: dxsa.dcl_global_flags <refactoringAllowed>
// CHECK: dxsa.dcl_constant_buffer <id = 0, size = 1>, <immediateIndexed>
// CHECK: dxsa.dcl_input vThreadIDInGroup<<x, y, z>>
// CHECK: dxsa.dcl_temps 3
// CHECK: dxsa.dcl_tgsm_raw g<0>, 1024
// CHECK: dxsa.dcl_thread_group <x = 4, y = 2, z = 3>
// CHECK: dxsa.ishl r<0, <x>>, vThreadIDInGroup<<z>>, l(0x2)
// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 48 : i32, num_components = 4 : i32, type = 31 : i32}
// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32}
// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[3, 2, 1, 0]> : vector<4xi32>, type = 8 : i32}
// CHECK: dxsa.instruction "store_raw" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]]
// CHECK: dxsa.sync <tgsm>
// CHECK: dxsa.sync <uav_group>
// CHECK: dxsa.sync <uav_global>
// CHECK: dxsa.sync <tgsm|threads>
// CHECK: dxsa.sync <uav_group|threads>
// CHECK: dxsa.sync <uav_global|threads>
// CHECK: dxsa.sync <uav_group|tgsm>
// CHECK: dxsa.sync <uav_global|tgsm>
// CHECK: dxsa.sync <uav_group|tgsm|threads>
// CHECK: dxsa.sync <uav_global|tgsm|threads>
// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_4]] {mask = 80 : i32, num_components = 4 : i32, type = 0 : i32}
// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32}
// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, swizzle = dense<[2, 0, 3, 1]> : vector<4xi32>, type = 31 : i32}
// CHECK: dxsa.instruction "ld_raw" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]]
// CHECK: dxsa.imm_atomic_iadd r<2, <x>>, g<0>, r<1, <x, y, x, x>>, vThreadIDInGroup<<x>>
// CHECK: dxsa.atomic_or g<0>, r<1, <x, y, x, x>>, vThreadIDInGroup<<x>>
// CHECK: dxsa.atomic_cmp_store g<0>, r<1, <x, y, x, x>>, vThreadIDInGroup<<y>>, vThreadIDInGroup<<x>>
// CHECK: dxsa.imm_atomic_cmp_exch r<1, <x>>, g<0>, r<1, <x, y, x, x>>, vThreadIDInGroup<<y>>, vThreadIDInGroup<<x>>
// CHECK: dxsa.ret

11 changes: 11 additions & 0 deletions mlir/test/Target/DXSA/asm/cyclecounter.test
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// RUN: mlir-translate --import-dxsa-bin %S/inputs/cyclecounter.shex | FileCheck %s
// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py


// CHECK-LABEL: dxsa.dcl_temps 1
// CHECK: dxsa.dcl_output o<0>
// CHECK: dxsa.dcl_input cycleCounter<<x>>
// CHECK: dxsa.mov r<0>, l(0x0)
// CHECK: dxsa.mov r<0, <z>>, cycleCounter<<x>>
// CHECK: dxsa.mov o<0>, r<0>

93 changes: 93 additions & 0 deletions mlir/test/Target/DXSA/asm/hs3.test
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// RUN: mlir-translate --import-dxsa-bin %S/inputs/hs3.shex | FileCheck %s
// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py


// CHECK-LABEL: dxsa.hs_decls
// CHECK: dxsa.dcl_input_control_point_count 4
// CHECK: dxsa.dcl_output_control_point_count 32
// CHECK: dxsa.dcl_tessellator_domain domain_quad
// CHECK: dxsa.dcl_tessellator_partitioning partitioning_fractional_odd
// CHECK: dxsa.dcl_tessellator_output_primitive output_triangle_cw
// CHECK: dxsa.dcl_hs_max_tessfactor 6.400000e+01
// CHECK: dxsa.hs_control_point_phase
// CHECK: dxsa.dcl_input v<[4, 0]>
// CHECK: dxsa.dcl_input v<[4, 1], <x, y>>
// CHECK: dxsa.dcl_input v<[4, 2], <x, y, z>>
// CHECK: dxsa.dcl_input vOutputControlPointID<none>
// CHECK: dxsa.dcl_input vPrim<none>
// CHECK: dxsa.dcl_output o<0>
// CHECK: dxsa.dcl_output o<1, <x, y>>
// CHECK: dxsa.dcl_output o<2, <x, y, z>>
// CHECK: dxsa.dcl_temps 1
// CHECK: dxsa.udiv null, r<0, <x>>, vOutputControlPointID, l(0x4)
// CHECK: dxsa.mov o<0>, v<[r<0, <x>>, 0]>
// CHECK: dxsa.mov o<1, <x, y>>, v<[r<0, <x>>, 1], <x, y, x, x>>
// CHECK: dxsa.mov o<2, <x, y, z>>, v<[r<0, <x>>, 2], <x, y, z, x>>
// CHECK: dxsa.hs_fork_phase
// CHECK: dxsa.dcl_input vicp<[4, 0]>
// CHECK: dxsa.dcl_input vicp<[4, 1], <x, y>>
// CHECK: dxsa.dcl_input vicp<[4, 2], <x, y, z>>
// CHECK: dxsa.dcl_input vocp<[32, 0]>
// CHECK: dxsa.dcl_input vocp<[32, 1], <x, y>>
// CHECK: dxsa.dcl_input vocp<[32, 2], <x, y, z>>
// CHECK: dxsa.dcl_hs_fork_phase_instance_count 4
// CHECK: dxsa.dcl_input vForkInstanceID<none>
// CHECK: dxsa.dcl_input vPrim<none>
// CHECK: dxsa.dcl_index_range o<0>, 4
// CHECK: dxsa.dcl_temps 1
// CHECK: dxsa.dcl_indexable_temp x<0>[4], 1
// CHECK: dxsa.dcl_output_siv o<0, <x>>, <finalQuadUeq0EdgeTessFactor>
// CHECK: dxsa.dcl_output_siv o<1, <x>>, <finalQuadVeq0EdgeTessFactor>
// CHECK: dxsa.dcl_output_siv o<2, <x>>, <finalQuadUeq1EdgeTessFactor>
// CHECK: dxsa.dcl_output_siv o<3, <x>>, <finalQuadVeq1EdgeTessFactor>
// CHECK: dxsa.mov x<[0, 0], <x>>, l(0x40000000)
// CHECK: dxsa.mov x<[0, 1], <x>>, l(0x40800000)
// CHECK: dxsa.mov x<[0, 2], <x>>, l(0x41700000)
// CHECK: dxsa.mov x<[0, 3], <x>>, l(0x40C00000)
// CHECK: dxsa.mov r<0, <x>>, vForkInstanceID<none>
// CHECK: dxsa.mov o<r<0, <x>>, <x>>, x<[0, r<0, <x>>], <x>>
// CHECK: dxsa.hs_fork_phase
// CHECK: dxsa.dcl_input vicp<[4, 0]>
// CHECK: dxsa.dcl_input vicp<[4, 1], <x, y>>
// CHECK: dxsa.dcl_input vicp<[4, 2], <x, y, z>>
// CHECK: dxsa.dcl_input vocp<[32, 0]>
// CHECK: dxsa.dcl_input vocp<[32, 1], <x, y>>
// CHECK: dxsa.dcl_input vocp<[32, 2], <x, y, z>>
// CHECK: dxsa.dcl_hs_fork_phase_instance_count 4
// CHECK: dxsa.dcl_input vForkInstanceID<none>
// CHECK: dxsa.dcl_input vPrim<none>
// CHECK: dxsa.dcl_index_range o<0>, 4
// CHECK: dxsa.dcl_temps 1
// CHECK: dxsa.dcl_indexable_temp x<0>[4], 1
// CHECK: dxsa.dcl_output o<0, <y>>
// CHECK: dxsa.dcl_output o<1, <y>>
// CHECK: dxsa.dcl_output o<2, <y>>
// CHECK: dxsa.dcl_output o<3, <y>>
// CHECK: dxsa.mov x<[0, 0], <x>>, l(0x41400000)
// CHECK: dxsa.mov x<[0, 1], <x>>, l(0x42000000)
// CHECK: dxsa.mov x<[0, 2], <x>>, l(0x41700000)
// CHECK: dxsa.mov x<[0, 3], <x>>, l(0x40A00000)
// CHECK: dxsa.mov r<0, <x>>, vForkInstanceID<none>
// CHECK: dxsa.mov o<r<0, <x>>, <y>>, x<[0, r<0, <x>>], <x>>
// CHECK: dxsa.hs_join_phase
// CHECK: dxsa.dcl_input vicp<[4, 0]>
// CHECK: dxsa.dcl_input vicp<[4, 1], <x, y>>
// CHECK: dxsa.dcl_input vicp<[4, 2], <x, y, z>>
// CHECK: dxsa.dcl_input vocp<[32, 0]>
// CHECK: dxsa.dcl_input vocp<[32, 1], <x, y>>
// CHECK: dxsa.dcl_input vocp<[32, 2], <x, y, z>>
// CHECK: dxsa.dcl_input vpc<0, <x, y>>
// CHECK: dxsa.dcl_input vpc<1, <x, y>>
// CHECK: dxsa.dcl_input vpc<2, <x, y>>
// CHECK: dxsa.dcl_input vpc<3, <x, y>>
// CHECK: dxsa.dcl_index_range vpc<0>, 4
// CHECK: dxsa.dcl_output_siv o<4, <x>>, <finalQuadUInsideTessFactor>
// CHECK: dxsa.dcl_output_siv o<5, <x>>, <finalQuadVInsideTessFactor>
// CHECK: dxsa.dcl_output o<4, <y>>
// CHECK: dxsa.dcl_output o<5, <y>>
// CHECK: dxsa.dcl_input vPrim<none>
// CHECK: dxsa.mov o<4, <x>>, l(0x41400000)
// CHECK: dxsa.mov o<5, <x>>, l(0x40C00000)
// CHECK: dxsa.mov o<4, <y>>, l(0x0)
// CHECK: dxsa.mov o<5, <y>>, l(0x0)

19 changes: 19 additions & 0 deletions mlir/test/Target/DXSA/asm/indexabletemp4.test
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// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp4.shex | FileCheck %s
// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py


// CHECK-LABEL: dxsa.dcl_global_flags <refactoringAllowed>
// CHECK: dxsa.dcl_constant_buffer <id = 0, size = 12>, <dynamicIndexed>
// CHECK: dxsa.dcl_input_ps constant v<1, <x>>
// CHECK: dxsa.dcl_input_ps constant v<1, <y>>
// CHECK: dxsa.dcl_output o<0, <x>>
// CHECK: dxsa.dcl_temps 1
// CHECK: dxsa.dcl_indexable_temp x<0>[4], 2
// CHECK: dxsa.mov r<0, <x>>, v<1, <x>>
// CHECK: dxsa.mov x<[0, 0], <x>>, cb<[0, r<0, <x>>], vector, <x>>
// CHECK: dxsa.mov x<[0, 1], <x>>, cb<[0, 4 + r<0, <x>>], vector, <x>>
// CHECK: dxsa.mov r<0, <x>>, v<1, <y>>
// CHECK: dxsa.mov x<[0, 1], <y>>, r<0, <x>>
// CHECK: dxsa.mov o<0, <x>>, x<[0, 77 + x<[0, 1], <y>>], <x>>
// CHECK: dxsa.ret

21 changes: 21 additions & 0 deletions mlir/test/Target/DXSA/asm/indexabletemp6.test
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// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp6.shex | FileCheck %s
// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py


// CHECK-LABEL: dxsa.dcl_global_flags <refactoringAllowed|enableMinimumPrecision>
// CHECK: dxsa.dcl_constant_buffer <id = 0, size = 12>, <dynamicIndexed>
// CHECK: dxsa.dcl_input_ps constant v<1, <x>>
// CHECK: dxsa.dcl_input_ps constant v<1, <y>>
// CHECK: dxsa.dcl_output o<0, min16f, <x>>
// CHECK: dxsa.dcl_temps 1
// CHECK: dxsa.dcl_indexable_temp x<0>[4]
// CHECK: dxsa.mov r<0, <x>>, v<1, <x>>
// CHECK: dxsa.mov x<[0, 0], <x>>, cb<[0, 4 + r<0, <x>>], vector, <x>>
// CHECK: dxsa.mov r<0, <y>>, x<[0, 0], <x>>
// CHECK: dxsa.mov x<[0, 0], min16f, <x>>, cb<[0, r<0, <x>>], vector, min16f, <x>>
// CHECK: dxsa.mov x<[0, 1], min16f, <x>>, cb<[0, 4 + r<0, <x>>], vector, min16f, <x>>
// CHECK: dxsa.mov r<0, <x>>, v<1, <y>>
// CHECK: dxsa.add x<[0, r<0, <x>>], min16f, <x>>, x<[0, r<0, <x>>], min16f, <x>>, r<0, min16f, <y>>
// CHECK: dxsa.mov o<0, min16f, <x>>, x<[0, r<0, <x>>], min16f, <x>>
// CHECK: dxsa.ret

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10 changes: 10 additions & 0 deletions mlir/test/Target/DXSA/hlsl/abs1.test
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// RUN: mlir-translate --import-dxsa-bin %S/inputs/abs1.shex | FileCheck %s
// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py


// CHECK-LABEL: dxsa.dcl_global_flags <refactoringAllowed>
// CHECK: dxsa.dcl_input_ps linear v<0, <x, y>>
// CHECK: dxsa.dcl_output o<0>
// CHECK: dxsa.mov o<0>, |v<0, <y, x, x, x>>|
// CHECK: dxsa.ret

10 changes: 10 additions & 0 deletions mlir/test/Target/DXSA/hlsl/abs2.test
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// RUN: mlir-translate --import-dxsa-bin %S/inputs/abs2.shex | FileCheck %s
// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py


// CHECK-LABEL: dxsa.dcl_global_flags <refactoringAllowed>
// CHECK: dxsa.dcl_input_ps constant v<0, <x, y>>
// CHECK: dxsa.dcl_output o<0>
// CHECK: dxsa.imax o<0>, -v<0, <y, x, x, x>>, v<0, <y, x, x, x>>
// CHECK: dxsa.ret

51 changes: 51 additions & 0 deletions mlir/test/Target/DXSA/hlsl/atomics.test
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// RUN: mlir-translate --import-dxsa-bin %S/inputs/atomics.shex | FileCheck %s
// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py


// CHECK-LABEL: dxsa.dcl_global_flags <refactoringAllowed>
// CHECK: dxsa.dcl_uav_typed <id = 0, dim = buffer, lbound = 0, ubound = 0, space = 0>, <x = uint, y = uint, z = uint, w = uint>
// CHECK: dxsa.dcl_uav_raw <id = 1, lbound = 1, ubound = 1, space = 0>
// CHECK: dxsa.dcl_uav_raw <id = 2, lbound = 2, ubound = 29, space = 0>
// CHECK: dxsa.dcl_uav_typed <id = 3, dim = texture2d, lbound = 30, ubound = 30, space = 0>, <x = uint, y = uint, z = uint, w = uint>
// CHECK: dxsa.dcl_uav_typed <id = 4, dim = texture3d, lbound = 31, ubound = 31, space = 0>, <x = uint, y = uint, z = uint, w = uint>
// CHECK: dxsa.dcl_uav_typed <id = 5, dim = texture2darray, lbound = 32, ubound = 32, space = 0>, <x = uint, y = uint, z = uint, w = uint>
// CHECK: dxsa.dcl_uav_typed <id = 6, dim = texture3d, lbound = 33, ubound = 64, space = 0>, <x = uint, y = uint, z = uint, w = uint>
// CHECK: dxsa.dcl_input_ps constant v<0>
// CHECK: dxsa.dcl_output o<0>
// CHECK: dxsa.dcl_temps 2
// CHECK: dxsa.atomic_iadd u<[0, 0]>, v<0, <z>>, v<0, <z>>
// CHECK: dxsa.atomic_umin u<[0, 0]>, v<0, <z>>, v<0, <z>>
// CHECK: dxsa.atomic_umax u<[0, 0]>, v<0, <z>>, v<0, <z>>
// CHECK: dxsa.atomic_and u<[0, 0]>, v<0, <z>>, v<0, <z>>
// CHECK: dxsa.atomic_or u<[0, 0]>, v<0, <z>>, v<0, <z>>
// CHECK: dxsa.atomic_xor u<[0, 0]>, v<0, <z>>, v<0, <z>>
// CHECK: dxsa.imm_atomic_iadd r<0, <x>>, u<[0, 0]>, v<0, <z>>, v<0, <z>>
// CHECK: dxsa.iadd r<0, <x>>, r<0, <x>>, v<0, <z>>
// CHECK: dxsa.atomic_iadd u<[3, 30]>, v<0, <x, y, x, x>>, r<0, <x>>
// CHECK: dxsa.atomic_iadd u<[4, 31]>, v<0, <y, w, z, y>>, r<0, <x>>
// CHECK: dxsa.atomic_iadd u<[5, 32]>, v<0, <x, y, z, x>>, r<0, <x>>
// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32}
// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<30> : vector<1xi32>}
// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<2> : vector<1xi32>}
// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32}
// CHECK: %[[OPERAND_4:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>}
// CHECK: dxsa.instruction "bfi" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]], %[[OPERAND_3]], %[[OPERAND_4]]
// CHECK: dxsa.atomic_iadd u<[6, 33 + r<0, <y>>]>, v<0, <x, y, z, x>>, r<0, <x>>
// CHECK: dxsa.imm_atomic_cmp_exch r<0, <x>>, u<[0, 0]>, v<0, <z>>, v<0, <w>>, r<0, <x>>
// CHECK: dxsa.imm_atomic_iadd r<0, <x>>, u<[1, 1]>, v<0, <x>>, v<0, <z>>
// CHECK: dxsa.iadd r<0, <x>>, v<0, <y>>, l(0xE)
// CHECK: dxsa.imm_atomic_iadd r<0, <x>>, u<[2, 2 + r<0, <x>>]>, v<0, <x>>, v<0, <z>>
// CHECK: dxsa.imm_atomic_umin r<0, <x>>, u<[1, 1]>, v<0, <x>>, v<0, <z>>
// CHECK: dxsa.imm_atomic_umax r<0, <x>>, u<[1, 1]>, v<0, <x>>, v<0, <z>>
// CHECK: dxsa.imm_atomic_and r<0, <x>>, u<[1, 1]>, v<0, <x>>, v<0, <z>>
// CHECK: dxsa.imm_atomic_or r<0, <x>>, u<[1, 1]>, v<0, <x>>, v<0, <z>>
// CHECK: dxsa.imm_atomic_xor r<0, <x>>, u<[1, 1]>, v<0, <x>>, v<0, <z>>
// CHECK: dxsa.imm_atomic_exch r<1, <x>>, u<[1, 1]>, v<0, <z>>, r<0, <x>>
// CHECK: dxsa.iadd r<0, <x>>, r<0, <x>>, r<1, <x>>
// CHECK: dxsa.imm_atomic_cmp_exch r<1, <x>>, u<[1, 1]>, v<0, <z>>, v<0, <w>>, r<0, <x>>
// CHECK: dxsa.iadd r<0, <x>>, r<0, <x>>, r<1, <x>>
// CHECK: dxsa.utof o<0>, r<0, <x, x, x, x>>
// CHECK: dxsa.ret

11 changes: 11 additions & 0 deletions mlir/test/Target/DXSA/hlsl/bad_ftoi.test
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// RUN: mlir-translate --import-dxsa-bin %S/inputs/bad_ftoi.shex | FileCheck %s
// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py


// CHECK-LABEL: dxsa.dcl_global_flags <refactoringAllowed|skipOptimization>
// CHECK: dxsa.dcl_output o<0>
// CHECK: dxsa.ftou o<0, <z>>, l(0x7F7FFFFF)
// CHECK: dxsa.ftou o<0, <w>>, l(0xFF7FFFFF)
// CHECK: dxsa.ftoi o<0, <x, y>>, l(0x7F7FFFFF, 0xFF7FFFFF, 0x0, 0x0)
// CHECK: dxsa.ret

17 changes: 17 additions & 0 deletions mlir/test/Target/DXSA/hlsl/binary1.test
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// RUN: mlir-translate --import-dxsa-bin %S/inputs/binary1.shex | FileCheck %s
// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py


// CHECK-LABEL: dxsa.dcl_global_flags <refactoringAllowed>
// CHECK: dxsa.dcl_input_ps linear v<0, <x>>
// CHECK: dxsa.dcl_input_ps linear v<0, <y>>
// CHECK: dxsa.dcl_input_ps linear v<0, <z, w>>
// CHECK: dxsa.dcl_output o<0, <x>>
// CHECK: dxsa.dcl_temps 1
// CHECK: dxsa.add r<0, <x>>, v<0, <x>>, v<0, <x>>
// CHECK: dxsa.div r<0, <x>>, r<0, <x>>, v<0, <x>>
// CHECK: dxsa.mul r<0, <x>>, r<0, <x>>, v<0, <y>>
// CHECK: dxsa.max r<0, <x>>, r<0, <x>>, v<0, <z>>
// CHECK: dxsa.min o<0, <x>>, r<0, <x>>, v<0, <w>>
// CHECK: dxsa.ret

20 changes: 20 additions & 0 deletions mlir/test/Target/DXSA/hlsl/bool1.test
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// RUN: mlir-translate --import-dxsa-bin %S/inputs/bool1.shex | FileCheck %s
// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py


// CHECK-LABEL: dxsa.dcl_global_flags <refactoringAllowed>
// CHECK: dxsa.dcl_input_ps constant v<0, <x>>
// CHECK: dxsa.dcl_output o<0, <x>>
// CHECK: dxsa.dcl_temps 1
// CHECK: dxsa.firstbit_hi r<0, <x>>, v<0, <x>>
// CHECK: dxsa.iadd r<0, <x>>, -r<0, <x>>, l(0x1F)
// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32}
// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32}
// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32}
// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<-1> : vector<1xi32>}
// CHECK: dxsa.instruction "movc" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]], %[[OPERAND_3]]
// CHECK: dxsa.ret

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