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Fixed hard-coded addr bus in memory read/write statements #20

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maliberty merged 1 commit into from
Jul 30, 2026
Merged

Fixed hard-coded addr bus in memory read/write statements #20

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8 changes: 4 additions & 4 deletions test/au/dpsram_256x256.au
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Original file line number Diff line number Diff line change
Expand Up @@ -8898,7 +8898,7 @@ cell(dpsram_256x256) {
bus(din_a) {
bus_type : dpsram_256x256_DATA;
memory_write() {
address : addr_in;
address : addr_a;
clocked_on : "clk_a";
}
direction : input;
Expand Down Expand Up @@ -8971,7 +8971,7 @@ cell(dpsram_256x256) {
direction : output;
max_capacitance : 0.500000;
memory_read() {
address : addr_in;
address : addr_a;
}
timing() {
related_pin : "clk_a" ;
Expand Down Expand Up @@ -9132,7 +9132,7 @@ cell(dpsram_256x256) {
bus(din_b) {
bus_type : dpsram_256x256_DATA;
memory_write() {
address : addr_in;
address : addr_b;
clocked_on : "clk_b";
}
direction : input;
Expand Down Expand Up @@ -9205,7 +9205,7 @@ cell(dpsram_256x256) {
direction : output;
max_capacitance : 0.500000;
memory_read() {
address : addr_in;
address : addr_b;
}
timing() {
related_pin : "clk_b" ;
Expand Down
8 changes: 4 additions & 4 deletions test/au/dpsram_256x32.au
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Original file line number Diff line number Diff line change
Expand Up @@ -1621,7 +1621,7 @@ cell(dpsram_256x32) {
bus(din_a) {
bus_type : dpsram_256x32_DATA;
memory_write() {
address : addr_in;
address : addr_a;
clocked_on : "clk_a";
}
direction : input;
Expand Down Expand Up @@ -1694,7 +1694,7 @@ cell(dpsram_256x32) {
direction : output;
max_capacitance : 0.500000;
memory_read() {
address : addr_in;
address : addr_a;
}
timing() {
related_pin : "clk_a" ;
Expand Down Expand Up @@ -1855,7 +1855,7 @@ cell(dpsram_256x32) {
bus(din_b) {
bus_type : dpsram_256x32_DATA;
memory_write() {
address : addr_in;
address : addr_b;
clocked_on : "clk_b";
}
direction : input;
Expand Down Expand Up @@ -1928,7 +1928,7 @@ cell(dpsram_256x32) {
direction : output;
max_capacitance : 0.500000;
memory_read() {
address : addr_in;
address : addr_b;
}
timing() {
related_pin : "clk_b" ;
Expand Down
8 changes: 4 additions & 4 deletions test/au/dpsram_256x32_h.au
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Original file line number Diff line number Diff line change
Expand Up @@ -1639,7 +1639,7 @@ cell(dpsram_256x32_h) {
bus(din_a) {
bus_type : dpsram_256x32_h_DATA;
memory_write() {
address : addr_in;
address : addr_a;
clocked_on : "clk_a";
}
direction : input;
Expand Down Expand Up @@ -1712,7 +1712,7 @@ cell(dpsram_256x32_h) {
direction : output;
max_capacitance : 0.500000;
memory_read() {
address : addr_in;
address : addr_a;
}
timing() {
related_pin : "clk_a" ;
Expand Down Expand Up @@ -1873,7 +1873,7 @@ cell(dpsram_256x32_h) {
bus(din_b) {
bus_type : dpsram_256x32_h_DATA;
memory_write() {
address : addr_in;
address : addr_b;
clocked_on : "clk_b";
}
direction : input;
Expand Down Expand Up @@ -1946,7 +1946,7 @@ cell(dpsram_256x32_h) {
direction : output;
max_capacitance : 0.500000;
memory_read() {
address : addr_in;
address : addr_b;
}
timing() {
related_pin : "clk_b" ;
Expand Down
4 changes: 2 additions & 2 deletions test/au/sssram_64x256.au
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Original file line number Diff line number Diff line change
Expand Up @@ -4563,7 +4563,7 @@ cell(sssram_64x256) {
bus(din_i) {
bus_type : sssram_64x256_DATA;
memory_write() {
address : addr_in;
address : addr_i;
clocked_on : "clk";
}
direction : input;
Expand Down Expand Up @@ -4636,7 +4636,7 @@ cell(sssram_64x256) {
direction : output;
max_capacitance : 0.500000;
memory_read() {
address : addr_in;
address : addr_i;
}
timing() {
related_pin : "clk" ;
Expand Down
26 changes: 17 additions & 9 deletions utils/liberty_exporter.py
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Original file line number Diff line number Diff line change
Expand Up @@ -258,7 +258,7 @@ def write_cell_constraint(
out_fh.write(" }\n")

def write_output_bus(
self, out_fh, name, pin_name, clk_pin_name, include_memory_read
self, out_fh, name, pin_name, clk_pin_name, include_memory_read, addr_bus_name
):
"""Writes the output bus definition"""

Expand All @@ -279,7 +279,7 @@ def write_output_bus(
# Based on 32x inverter being a common max (or near max) inverter
if include_memory_read:
out_fh.write(" memory_read() {\n")
out_fh.write(" address : addr_in;\n")
out_fh.write(f" address : {addr_bus_name};\n")
out_fh.write(" }\n")
out_fh.write(" timing() {\n")
out_fh.write(f' related_pin : "{clk_pin_name}" ;\n')
Expand Down Expand Up @@ -356,7 +356,14 @@ def write_address_bus(self, out_fh, name, bus_name, clk_pin_name):
out_fh.write(" }\n")

def write_data_bus(
self, out_fh, name, bus_name, we_pin_name, clk_pin_name, include_memory_write
self,
out_fh,
name,
bus_name,
we_pin_name,
clk_pin_name,
include_memory_write,
addr_bus_name,
):
"""Writes the data bus"""

Expand All @@ -370,7 +377,7 @@ def write_data_bus(
out_fh.write(" bus_type : %s_DATA;\n" % name)
if include_memory_write:
out_fh.write(" memory_write() {\n")
out_fh.write(" address : addr_in;\n")
out_fh.write(f" address : {addr_bus_name};\n")
out_fh.write(f' clocked_on : "{clk_pin_name}";\n')
out_fh.write(" }\n")
out_fh.write(" direction : input;\n")
Expand Down Expand Up @@ -415,14 +422,13 @@ def write_rw_pin_set(self, out_fh, name, rw_port_group, is_ram):
"""Writes the rw port group to the output stream"""

clk_pin_name = rw_port_group.get_clock_name()
addr_bus_name = rw_port_group.get_address_bus_name()
if rw_port_group.get_write_enable_name():
self.write_pin(
out_fh, name, rw_port_group.get_write_enable_name(), clk_pin_name
)
if rw_port_group.get_address_bus_name():
self.write_address_bus(
out_fh, name, rw_port_group.get_address_bus_name(), clk_pin_name
)
if addr_bus_name:
self.write_address_bus(out_fh, name, addr_bus_name, clk_pin_name)
if (
rw_port_group.get_data_input_bus_name()
and rw_port_group.get_write_enable_name()
Expand All @@ -434,6 +440,7 @@ def write_rw_pin_set(self, out_fh, name, rw_port_group, is_ram):
rw_port_group.get_write_enable_name(),
clk_pin_name,
is_ram,
addr_bus_name,
)
if rw_port_group.get_data_output_bus_name():
self.write_output_bus(
Expand All @@ -442,9 +449,10 @@ def write_rw_pin_set(self, out_fh, name, rw_port_group, is_ram):
rw_port_group.get_data_output_bus_name(),
clk_pin_name,
is_ram,
addr_bus_name,
)
for related_pin in rw_port_group.get_related_pins():
self.write_pin(out_fh, name, related_pin, clk_pin_name)
for bus_name,bus_data in rw_port_group.get_related_busses().items():
for bus_name, bus_data in rw_port_group.get_related_busses().items():
self.write_generic_bus(out_fh, name, bus_name, clk_pin_name)
self.write_clk_pin(out_fh, clk_pin_name)
13 changes: 9 additions & 4 deletions utils/single_port_ram_liberty_exporter.py
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Original file line number Diff line number Diff line change
Expand Up @@ -20,24 +20,29 @@ def write_cell(self, out_fh):
timing_data = self._memory.get_timing_data()
rw_port_group = self._memory.get_rw_port_groups()[0]
clk_pin_name = rw_port_group.get_clock_name()
addr_bus_name = rw_port_group.get_address_bus_name()
self.write_memory_section(out_fh)
self.write_clk_pin(out_fh, clk_pin_name)
self.write_output_bus(
out_fh, name, rw_port_group.get_data_output_bus_name(), clk_pin_name, True
out_fh,
name,
rw_port_group.get_data_output_bus_name(),
clk_pin_name,
True,
addr_bus_name,
)
self.write_pin(
out_fh, name, rw_port_group.get_write_enable_name(), clk_pin_name
)
for pin in self._memory.get_misc_ports():
self.write_pin(out_fh, name, pin, clk_pin_name)
self.write_address_bus(
out_fh, name, rw_port_group.get_address_bus_name(), clk_pin_name
)
self.write_address_bus(out_fh, name, addr_bus_name, clk_pin_name)
self.write_data_bus(
out_fh,
name,
rw_port_group.get_data_input_bus_name(),
rw_port_group.get_write_enable_name(),
clk_pin_name,
True,
addr_bus_name,
)
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