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UPSTREAM-PEND: drivers: watchdog: MSPM0 WWDT native register access + interval-timer- #114858 - #74
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natto1784 merged 22 commits intoOct 9, 2026
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commit ef0d8a2 upstream. - Add the numaker_pfm_m487 board to watchdog timer tests. Signed-off-by: Scott Laboe <scottyl2.718@gmail.com>
commit 0ca5b7d upstream. Change test code to ease test configuration for a new platform. Instead of defining test configuration in main.c define Kconfigs. Kconfig value can be set much easier. Signed-off-by: Sebastian Głąb <sebastian.glab@nordicsemi.no>
commit 5ffab1a upstream. Add devicetree binding for the MSPM0 windowed watchdog (WWDT). Signed-off-by: Sanjay Vallimanalan <sanjay@linumiz.com> Signed-off-by: Jackson Farley <j-farley@ti.com>
commit 143953b upstream. TI MSPM0 has a WWDT module to initiate a reset when correct operation of the device has failed due to an unexpected software or system delay. Signed-off-by: Sanjay Vallimanalan <sanjay@linumiz.com> Signed-off-by: Jackson Farley <j-farley@ti.com>
commit 64260d4 upstream. Add devicetree nodes for the MSPM0 watchdog peripherals and set them disabled by default. Signed-off-by: Sanjay Vallimanalan <sanjay@linumiz.com> Signed-off-by: Jackson Farley <j-farley@ti.com>
commit a3c2a68 upstream. Add board-specific overlays to enable the MSPM0 WWDT in the Zephyr watchdog sample for lp_mspm0g3507 and lp_mspm0l2228 boards. Signed-off-by: Sanjay Vallimanalan <sanjay@linumiz.com> Signed-off-by: Jackson Farley <j-farley@ti.com>
…rupts PR: 114858 Add required clocks property referencing LFCLK clock controller. The driver reads the actual rate via clock_control_get_rate() instead of assuming 32768 Hz. Add optional interrupts property for the INTTIM interrupt line used in interval-timer mode (WDT_FLAG_RESET_NONE). Window-watchdog instances without an interrupt line omit this property. Also corrects the ti,watchdog-reset-action description which had the SYSRST and BOOTRST values reversed: 1 maps to WDT_FLAG_RESET_SOC (SYSRST) and 0 maps to WDT_FLAG_RESET_CPU_CORE (BOOTRST). Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
…nodes PR: 114858 Add clocks = <&ckm MSPM0_CLOCK_LFCLK> and interrupts = <0 0> to wdt0 in mspm0.dtsi (all devices) and wdt1 in mspm0g.dtsi (G-series only). WWDT0 and WWDT1 on MSPM0G share NVIC IRQ 0. Enabling both instances in interval-timer mode requires CONFIG_SHARED_INTERRUPTS; the driver enforces this with a BUILD_ASSERT. Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
…er ... PR: 114858 Replace all DL_WWDT_* HAL calls with direct register access using a native struct wwdt_mspm0_regs mapped over the peripheral base address. Includes BUILD_ASSERT offset checks for critical register positions. All functions use the two-step config/base extraction pattern: const struct wwdt_mspm0_config *config = dev->config; struct wwdt_mspm0_regs *base = config->base; init() issues a peripheral reset (GPRCM.RSTCTL) before enabling power (GPRCM.PWREN) to match the standard MSPM0 peripheral init sequence. The following gaps from the original HAL-based driver are preserved intentionally and addressed in follow-up patches: - calculate_timeout_periods() uses per_counts (2^n counter widths) but still assumes a fixed 32768 Hz LFCLK - setup() still honors WDT_OPT_PAUSE_IN_SLEEP unconditionally - install_timeout() uses a strict equality check against reset_action - feed() uses ARG_UNUSED(channel_id) — single-channel driver, no validation - disable() returns unconditional -EPERM with no state tracking Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
…tiv... PR: 114858 Three small, independent fixes found while translating the HAL-based driver to native register access: - calculate_timeout_periods(): the closed-window search loop used an explicit bound of 7 while window_sixteenths[] has 8 entries, so a window.min that only the last (87.5%) entry could satisfy silently fell through to that entry without validating the fit. Walk the full array and return -EINVAL when no available fraction enforces the requested window.min, instead of silently widening the window. - setup(): WDT_OPT_PAUSE_IN_SLEEP was silently accepted and mapped to the STISM bit, but hw_wwdt.h documents that STISM has no effect for the global Window Watchdog. Return -ENOTSUP instead. Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
…utex PR: 114858 Add timeout_valid and is_setup to wwdt_mspm0_data and a k_mutex to protect them, guarding all four API entry points against invalid or concurrent call sequences: - setup(): -EINVAL if install_timeout() was never called successfully, -EBUSY if already running - disable(): distinguishes -EFAULT (never started) from -EPERM (started, can't stop) instead of an unconditional -EPERM - install_timeout(): the already-running check now uses is_setup instead of polling WWDTSTAT; -ENOMEM if a timeout is already installed and disable() has not freed the single channel slot - feed(): -EINVAL if setup() was never called Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
…ste... PR: 114858 Read the LFCLK rate via clock_control_get_rate() instead of assuming a fixed 32768 Hz, and reject a rate of zero. Requires the ti,mspm0-watchdog clocks property added in an earlier patch of this series. The per_counts (2^n counter widths) format was already introduced in the native conversion patch; this patch replaces the hardcoded 32768 Hz assumption in all timeout computations with the actual rate returned by clock_control_get_rate(). Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
…ara... PR: 114858 One validation gap in the API contract: - install_timeout(): mask cfg->flags to WDT_FLAG_RESET_MASK before comparing against config->reset_action, and reject any reset-type bits above WDT_FLAG_RESET_SOC with -ENOTSUP instead of -EINVAL. The unmasked comparison rejected any caller that also set unrelated wdt_timeout_cfg flag bits alongside a valid reset action. Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
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October 8, 2026 11:00
…ack... PR: 114858 Add WDT_FLAG_RESET_NONE mode using the WWDT interval-timer hardware path (WWDTCTL0.MODE = MODE_INTERVAL). The counter fires INTTIM on each expiry and auto-reloads without reset, delivering a periodic callback. WWDT0 and WWDT1 share IRQ 0 on MSPM0G. The ISR checks RIS before acting so z_shared_isr dispatch is safe. Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
…nd ... PR: 114858 Replace eight raw-hex PER field constants with WWDT_CTL0_PER_MASK (GENMASK(6,4)) and FIELD_PREP(), eliminating the wwdt_period_lut struct in favour of a per_exp[] exponent array with BIT() inline. Name the hardcoded clock-divider bounds as WWDT_CTL0_CLKDIV_MASK and WWDT_MAX_CLKDIV. Mask CLKDIV on register writes for safety. Replace volatile bool is_setup with atomic_t for correct memory-barrier semantics on the ISR read path in feed() and wwdt_mspm0_isr(). Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
PR: 114858 Configure WWDT0 with LFCLK as clock source and the appropriate closed-window and period settings for the board. Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
PR: 114858 Add watchdog0 and watchdog1 aliases pointing to wdt0 and wdt1. The wdt nodes remain disabled by default following Zephyr convention; applications and tests enable them via board overlays. Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
PR: 114858 Add watchdog0 alias pointing to wdt0. The wdt0 node remains disabled by default following Zephyr convention; applications and tests enable it via board overlays. Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
…9/l... PR: 114858 Add board overlays enabling wdt0 for wdt_basic_api on LP_MSPM0G3507, LP_MSPM0G3519, and LP_MSPM0L2228. This test has no test functions and serves as a build-only smoke test to validate driver compilation. Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
…228... PR: 114858 Add board overlays enabling wdt0 for the watchdog sample on LP_MSPM0G3507, LP_MSPM0G3519, and LP_MSPM0L2228. Exclude ti_mspm0_watchdog from the pre-reset callback attempt (WDT_ALLOW_CALLBACK=0): MSPM0 WWDT window-watchdog violations route to the ESM safety block, not the NVIC, so a pre-reset callback is architecturally impossible and would always be rejected with -ENOTSUP. The sample uses WDT_FLAG_RESET_SOC without a callback, which is supported directly by the MSPM0 WWDT window-watchdog mode. Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
…228... PR: 114858 Add board overlays for LP_MSPM0G3507 and LP_MSPM0L2228 and add the boards to the tests.yaml platform_allow list. Add MSPM0 WWDT defaults to the test Kconfig so no board-level conf files are needed, matching how other vendors (Silabs, NuMaker) handle their hardware-specific test parameters: - TEST_WDT_FLAG_RESET_NONE_SUPPORTED=y: MSPM0 WWDT interval-timer mode implements WDT_FLAG_RESET_NONE (INTTIM interrupt, no reset) - TEST_WDT_WINDOW_MIN_SUPPORTED=y: WWDT hardware enforces the closed-window minimum feed time - TEST_WDT_WINDOW_MAX_ALLOWED=0x7D0000 (8192000 ms): WWDT maximum timeout at 32768 Hz LFCLK: 8 * 2^25 * 1000 / 32768 = 8192000 ms Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
…07/... PR: 114858 Add board overlays and tests.yaml platform_allow entries for LP_MSPM0G3507, LP_MSPM0G3519, and LP_MSPM0L2228. WDT_SETUP_FLAGS=2 (WDT_OPT_PAUSE_HALTED_BY_DBG) is set via extra_configs in tests.yaml; this is supported by the MSPM0 WWDT PDBGCTL register. No board-level conf is needed. Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
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Convert the MSPM0 Windowed Watchdog Timer driver from TI DriverLib HAL calls to native register access, add WDT_FLAG_RESET_NONE interval-timer callback support, and enable the driver on three MSPM0 LaunchPad boards.
PR: zephyrproject-rtos#114858
Cherrypicked linumiz HAL based merged PR: zephyrproject-rtos#95304
Hardware testing reports on downstream:
wdt_error_case
08-Oct-26_16-21-10_ML222228_ttyACM0.txt
08-Oct-26_16-20-39_MG353507_ttyACM2.txt
08-Oct-26_16-20-09_MG003519_ttyACM4.txt
wdt_basic_api
08-Oct-26_15-39-36_MG353507_ttyACM2.txt
08-Oct-26_15-40-38_ML222228_ttyACM0.txt
wdt_basic_reset_none
08-Oct-26_16-17-39_MG353507_ttyACM2.txt
08-Oct-26_16-18-20_MG003519_ttyACM4.txt
08-Oct-26_16-17-05_ML222228_ttyACM0.txt
sample watchdog
08-Oct-26_15-41-15_ML222228_ttyACM0.txt