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UPSTREAM-PEND: dts: ti: add pinctrl DTSIs for MSPM0GX51X and MSPM33C321A families- #116778 and enable pinctrl for MSPM33C321A- #119150 - #62
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commit 37114d6 upstream. Add gpioa/gpiob/gpioc and their pin-controller parent to mspm33c.dtsi. Addresses (0x400f0000/0x400f2000/0x400f4000), IRQs (6/7/8), and the pin-controller's combined address range are taken from the MSPM33C321A TRM memory map and NVIC interrupt vector tables GPIO0/1/2's DOUT/DOE/DIN/POLARITY/CPU_INT register layout is identical to MSPM0's GPIO_Regs (same GPIO IP block), so the existing "ti,mspm0-gpio" and "ti,mspm0-pinctrl" compatibles are reused as-is instead of introducing new bindings. Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
PR: 116778 Add pinctrl state nodes for the MSPM0GX51X device family. Pin node properties are derived from the device's IOMUX register definitions. Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
…c321a PR: 116778 Add pinctrl state nodes for MSPM33C321A. Pin node properties are derived from the device IOMUX register definitions. Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
PR: 116778 Switch the SoC include from the HAL path to the Zephyr-tree native path so that the pinctrl label defined in mspm0.dtsi is visible to boards including the new per-family pinctrl dtsi files. Update the pinctrl include to the correct mspm0gx51x family file. Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
PR: 116778 Include the device-specific pinctrl DTSI so peripheral drivers can reference pin configuration nodes via &pinctrl. Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
… pl... PR: 119150 The pinctrl node incorrectly used GPIOA base address (0x400f0000) instead of the IOMUX base address (0x400cc000), as defined by IOMUX_BASE in mspm33c321x.h. Reorganize GPIO nodes as peer nodes of pinctrl under soc, matching the MSPM0 structure. Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
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Add per-family pinctrl DTSIs for two TI MSP device families and update the corresponding LaunchPad board files.
Fix the MSPM33C321A pinctrl node and enable pinctrl on the LP_MSPM33C321A board.
The pinctrl node in mspm33c.dtsi incorrectly used the GPIOA base address (0x400f0000) instead of the IOMUX base address (0x400cc000) as defined by IOMUX_BASE.
GPIO nodes were also nested inside pinctrl instead of being peer nodes under soc.
Includes the per-board pinctrl DTSI on lp_mspm33c321a.