fp-cuda: device-resident F₂ row reduction (RREF) on Hopper#274

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JoeyBF:claude/blas3-row-reduction-lgjz3y

Commits on Jul 17, 2026

fp-cuda: wgmma.b1 F2 GEMM kernel — host-arranged A/B operands

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fp-cuda: K-pipeline — TMA loads, double-buffering, warpgroup specialization

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Phase 3: 128B-swizzle operands + pipelined wgmmas

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Phase 4: widen to m64n256k256 (largest binary MMA shape)

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Phase 5: per-warpgroup register reallocation (setmaxnreg)

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Phase 6: deepen K-pipeline to STAGES=3

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Phase 7: write the output tile via TMA bulk store (S2G)

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Migrate host layer from cuda-core to cudarc (stable Rust)

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Phase 8: persistent kernel + grouped tile rasterization

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Phase 9: thread-block clusters + TMA multicast of B

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Phase 10: register-block the output tile to cut operand-refill bandwidth

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Phase 11: overlap the output-tile TMA store with the next tile's compute

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Phase 12: hoist wgmma.fence out of the consumer K-loop

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fp-cuda: occupancy-aware persistent launch; document 2-CTA/SM dead end

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fp-cuda: wire into fp behind a `gpu` feature; CI builds without nvcc

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Commits on Jul 18, 2026