[AMD] dsv4-fp4-mi355x-sglang: switch fixed-seq-len search space to TP4

[seungrokj]

Summary

• Switch dsv4-fp4-mi355x-sglang fixed-seq-len search space from TP8 to TP4 for both isl=1024 and isl=8192 scenarios
• Expand isl=8192 coverage: add TP4 dp-attn sweep (conc 32–2048) alongside TP4 TP-only sweep (conc 1–32)
• Update perf-changelog.yaml with change description

Test plan

• Verify dsv4-fp4-mi355x-sglang fixed-seq-len CI jobs launch with TP4 configs
• Confirm isl=8192 dp-attn and TP-only rows both appear in sweep results

🤖 Generated with Claude Code

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Note

Low Risk
YAML-only benchmark sweep tuning; no application or serving code paths change.

Overview
Updates dsv4-fp4-mi355x-sglang fixed-seq-len benchmark sweeps on MI355X: the former TP8, dp-attn off latency rows (conc 1–32) are replaced with TP4 coverage—dp-attn on (conc 16–128) and dp-attn off (conc 1–32)—for both isl=1024 and isl=8192. The existing TP8 + dp-attn high-concurrency rows (conc 64–2048) are unchanged.

Documents the change in perf-changelog.yaml for config key dsv4-fp4-mi355x-sglang.

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[github-actions]

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[functionstackx]

@seungrokj can u try looking into sgl mtp too? would switching it help? +viz @1am9trash

[cursor]

Cursor Bugbot has reviewed your changes and found 1 potential issue.

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[github-actions]

see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=27528680882
see unofficial run visualizer at https://inferencex.semianalysis.com/evaluation?unofficialRun=27528680882

[github-actions]

see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=27528759942
see unofficial run visualizer at https://inferencex.semianalysis.com/evaluation?unofficialRun=27528759942

[github-actions]

see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=27528759942
see unofficial run visualizer at https://inferencex.semianalysis.com/evaluation?unofficialRun=27528759942

[seungrokj]

@functionstackx @cquil11 can you plz approve this ?