[None][feat] Kimi K3: unlock the CUTEDSL MoE backend for NVFP4 SiTU - #19003
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Included review availability: Your plan provides up to 12 included reviews per hour; 10 remain after this review. WalkthroughKimi K3 NVFP4 now supports SiTU through CuteDSL, preserves explicit backend failures, adds resolver and kernel tests, and exposes backend selection in Python and Slurm launchers. ChangesKimi K3 SiTU backend support
Priority: ➖ Normal Estimated code review effort: 4 (Complex) | ~45 minutes Change: Feature Sequence Diagram(s)sequenceDiagram
participant KimiK3Launcher
participant LLM
participant BackendResolver
participant CuteDslFusedMoE
participant SiTUKernel
KimiK3Launcher->>LLM: pass MoeConfig backend override
LLM->>BackendResolver: resolve explicit MoE backend
BackendResolver->>CuteDslFusedMoE: validate NVFP4 SiTU eligibility
CuteDslFusedMoE->>SiTUKernel: pass SiTU beta parameters
SiTUKernel->>LLM: return fused MoE output
Merge Risk: 🔵 Low · up to Sequential SiTU beta configurations still lack verified regression coverage for kernel-cache separation. This is a bounded test-confidence risk that should be tracked before merge. 🚥 Pre-merge checks | ✅ 5✅ Passed checks (5 passed)
✨ Finishing Touches🧪 Generate unit tests (beta)
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In `@examples/kimi_k3/quick_start_kimi_k3.sbatch`:
- Line 43: Update the usage() function to include the accepted --moe-backend
option as [--moe-backend BACKEND], leaving the existing argument parsing
unchanged.
In `@tensorrt_llm/_torch/custom_ops/cute_dsl_custom_ops.py`:
- Line 92: Update _canonicalize_situ_beta to return None only when situ_beta
equals the SITU_BETA_DISABLED sentinel, preserving explicit values such as 0.0
and -2.0. Add coverage for ActivationType.Swiglu confirming those values are
rejected by validation.
In
`@tensorrt_llm/_torch/cute_dsl_kernels/blackwell/blockscaled_contiguous_gather_grouped_gemm_act_fusion.py`:
- Around line 436-440: Update the SiTU beta validation in the constructor around
the existing situ_beta and situ_linear_beta check to reject any non-finite value
as well as zero or negative values, while preserving the current ValueError
behavior and message context. Add regression coverage in the Kimi SiTU MoE tests
for NaN, positive infinity, zero, and negative beta inputs.
In `@tensorrt_llm/_torch/models/modeling_kimi_linear.py`:
- Line 1141: Add a regression test in the Kimi K3 MoE runtime tests covering
explicit CUTEDSL selection when CUTEDSL is ineligible but CUTLASS is eligible.
Assert that KimiK3MoERuntime raises and includes the backend rejection trail,
rather than falling back to CUTLASS; keep existing allow-list and
configuration-preservation tests unchanged.
In `@tests/unittest/_torch/moe/test_kimi_k3_situ_moe.py`:
- Around line 1043-1044: Update the CUTEDSL test skip condition around
IS_CUTLASS_DSL_AVAILABLE to also require an SM100 or SM103 GPU, using the
existing device capability detection symbols in the test; skip before backend
resolution for all other architectures while preserving the current CuTe DSL
wheel check.
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We rarely use the CUTLASS backend for kimi k3, so could we keep this test focused on CUTEDSL and remove the CUTLASS case to avoid spending CI resources on it? thanks
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In `@tensorrt_llm/_torch/custom_ops/cute_dsl_custom_ops.py`:
- Around line 3460-3461: Add regression coverage in the SiTU MoE execution test
using the same CUTEDSL shape and tactic with two distinct beta pairs. Verify
each output against its corresponding SiTU reference and assert the outputs
differ, exercising beta-specific kernel-cache identity and preventing reuse
across soft-cap values.
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Docstring coverage over the diff was 72%, under the 80% gate. Seven functions were missing one; each now says the thing a reader could not recover from the signature. The two that carry real information: unique_id() lists trace-time constants, which is why the activation soft-caps belong in it -- they are folded into the compiled kernel as const_expr, so two runners differing in a beta are different kernels and must not share a tuning result. Omitting them would silently serve one layer's kernel to a layer with different soft-caps. _skip_if_backend_unavailable() probes at call time rather than through pytest.mark.skipif, because the marker is evaluated during collection and importing cute_dsl_utils that early puts the CuTe DSL wheel's package directory on sys.path for every other test file in the session. No behaviour change. Signed-off-by: Xin Guan <294044352+xguannv@users.noreply.github.com>
Five review findings, all verified against the code first. _canonicalize_situ_beta mapped the whole `<= 0` range to None, not just the sentinel. On a SwiGLU layer that turned situ_beta=0.0 into "no soft-caps supplied" and accepted it, when the kernel's own check would have refused the combination. Only SITU_BETA_DISABLED disables now; everything else is forwarded so the kernel sees it. The kernel's `situ_beta <= 0` test let NaN and positive infinity through -- every comparison against NaN is false, and an infinity is positive. The epilogue folds 2/beta and 2*beta at trace time, so either one is compiled in and returns quietly wrong activations rather than failing. Replaced with `0 < beta < inf`. Note this file's `math` is the MLIR dialect, not Python's, so isfinite() is not available here. Three new tests: the sentinel is the only disabling value; the kernel refuses NaN, infinity, zero and negative betas; and an ineligible explicit CUTEDSL request raises rather than degrading to CUTLASS, with the allow_degradation=True case as the control so the assertion cannot pass because substitution stopped working altogether. _skip_if_backend_unavailable() checked only for the CuTe DSL wheel, but nvfp4_moe_supported admits every SM >= 100 and only the Blackwell act-fusion kernel carries the SiTU epilogue, so on other architectures the CUTEDSL case failed in resolution instead of skipping. Also the launcher's usage() text, which omitted --moe-backend while the parser accepted it -- and printed that incomplete text on the error path -- and the kernel class docstring, which still said SwiGLU or Relu2 only. Signed-off-by: Xin Guan <294044352+xguannv@users.noreply.github.com>
Four findings from review, all verified against the code first. The op schema does take Optional[float]. My earlier commit message claimed it cannot, and that claim was the whole reason SITU_BETA_DISABLED existed; trtllm::kda_mtp_decode in this repo has carried `scale: Optional[float] = None` all along. The sentinel, its canonicalization helper and the test that covered the helper are gone -- None now means "not a SiTU layer" the way it does everywhere else. test_nvfp4_kernel_actually_applies_situ compared against SwigluBias, `gate*sigmoid(gate*alpha)*(up+beta)`. No epilogue on this path computes that. What a CuteDSL layer computes when it does not run SiTU is `up * silu(gate)`, so a genuine SwiGLU fallback landed far from both references and still satisfied `situ_cos > swiglu_cos` -- the test could not fail the way it claimed to. The control is now the realistic wrong answer. The absolute bounds the review also asked for are deliberately not in this commit: cosine is scale-invariant, so the assertion that catches a mis-scaled SiTU has to be on rel_l2, and its threshold should come from the measured spread rather than a guess. Both scores are printed; the bounds land once there is a number to set them from. test_kimi_k3_allow_list_matches_what_the_backends_declare said "exactly" and tested inclusion, walking a dict of backends written out by hand -- a second copy of the capability set, which is the defect this module exists to catch. Both sides are derived now, from BACKEND_FAMILY and from asking the allow-list, and compared as sets so an offered-but-incapable backend fails too. `any` rather than `all` over a family because resolution walks members in IMPL_PRIORITY order: CUTEDSL qualifies through CuteDslFusedMoE while CuteDslB12xFusedMoE does not declare SiTu. None of the five tests this PR adds were in any CI list, including test_nvfp4_kernel_actually_applies_situ[CUTEDSL] -- the one the PR is for. All are listed in l0_b300.yml now. The [CUTLASS] arm is replaced rather than joined, per review: K3 rarely runs CUTLASS, and the parametrization keeps the case for local use. Signed-off-by: Xin Guan <294044352+xguannv@users.noreply.github.com>
…budget
Review asked for two things: compare against plain SwiGLU, and assert an
error bound, because the cosine ordering alone accepts both plain-SwiGLU
output and incorrectly scaled SiTU. The first landed earlier; this is the
second, and getting there needed two corrections first.
input_scale is 1.0. All 247296 *.input_scale entries in nvidia/Kimi-K3-NVFP4,
across 92 shards, are exactly 1.0, so that is what inference runs. This test
derived amax/(448*6) instead, a value no checkpoint produces, and on that
path the kernel lands 36% short of the reference -- norms 263.02 against
412.49 -- which is the open activation-scale issue that
test_nvfp4_experts_match_situ_reference already carries as a strict xfail.
At input_scale=1.0 the norms agree to 1.004. So the test was running off the
inference path and on top of an unrelated defect, and the cosine assertion
could not see the 36% at all, cosine being scale-invariant. That is the
reviewed failure mode, live in the suite rather than hypothetical.
Both references now read the weights back out of the checkpoint tensors via
e2m1_and_ufp8sf_scale_to_float_v2, as tests/unittest/_torch/thop/serial/
test_moe.py does, so weight quantization cancels instead of landing on one
side only.
The bound is derived rather than fitted. One NVFP4 round trip of Gaussian
data -- the e2m1 grid under a per-16 e4m3 block scale -- costs eps = 0.0950
relative L2, which the checkpoint weights confirm at 0.09515/0.09510/0.09512.
Quantization error does not amplify through a dot product of random data, so
N independent stages compose as sqrt(N)*eps; with the weight stages cancelled
three remain -- the activation reaching the gate, the activation reaching the
up projection, independent because they cross different weight matrices and
SiTU multiplies them, and the FC1->FC2 intermediate -- giving a floor of
sqrt(3)*0.0950 = 0.1645. Measured across 6 seeds x {CUTLASS, TRTLLM, CUTEDSL}:
0.1613 to 0.1656, i.e. 0.980 to 1.006 of prediction, norm ratio in
0.9992..1.0035. The budget is confirmed, not calibrated.
0.20 is that floor plus ~21% headroom against a +-2% spread, and catches a
SiTU mis-scaled by >=11.4% since a scale error s appears as
sqrt(s**2 + 0.1645**2). Fitting the bound to measurements instead would have
frozen whatever the implementation does today into the baseline; anchored on
the budget, an extra quantization stage reports as a failure rather than as a
number to loosen.
The ordering assertion stays as the diagnosis. The norm ratio is printed next
to cosine because rel_l2**2 = r**2 - 2*r*cos + 1, so the two split the
asserted number into a magnitude half and a direction half.
Signed-off-by: Xin Guan <294044352+xguannv@users.noreply.github.com>
Measured from nvidia/Kimi-K3-NVFP4: with the post_attention_layernorm weight giving the MoE input its per-channel magnitude, real g and u have sigma 0.095..0.234 across layers 3/10/30/55, against beta=4 and linear_beta=25. At that scale SiTU and plain SwiGLU differ by 0.08%..0.4%, well under the sqrt(3)*eps = 0.1645 quantization floor, so no assertion could separate them. The test's randn*0.05 puts sigma at 1.497, 6-15x production, where they differ by 14%. That is the reason the discriminator works, so it belongs in the docstring rather than being left to look like an arbitrary constant. Keeping the scale, not changing it: an earlier plan to raise it further was based on assuming production activations were larger, which the measurement reversed. Also drops two claims that the previous commit made stale by adding a bound: the comparison is no longer tolerance-free. Signed-off-by: Xin Guan <294044352+xguannv@users.noreply.github.com>
Review asked for regression coverage on beta-specific cache identity. The betas are trace-time const_expr folded into the compiled epilogue, so unique_id() lists them; if they ever drop out, the autotuner returns the kernel built for the previous betas and nothing raises -- the second layer just silently applies the first layer's soft-caps. Two layers run in one process, in cache order, and each output is checked against the reference built for ITS OWN betas. Asserting only that the two differ would pass if the second were wrong some other way. What varies is the betas, not the input distribution. Measured from the checkpoint, production g and u sit at sigma 0.10..0.23, so inflating the activation to make the caps bite would push the test further from inference, not closer. The second pair is (2.0, 10.0) because the residual grows as the caps tighten and that is the last pair the sqrt(3)*eps budget still covers -- 0.1644, 0.1674, 0.1869, 0.2185 for (4.0,25.0), (2.0,10.0), (0.5,2.0), (0.25,1.0). The growth is not explained: sharper clipping does make the FC1->FC2 intermediate quantize slightly worse, but that is ~3% of it, not 33%. Picking a pair the budget covers keeps one bound over both arms instead of granting an unexplained exception, and (2.0, 10.0) still lands 27% from the production output, far outside allclose, which is all the cache question needs. _make_routed_moe and _make_nvfp4_moe take the soft-caps as parameters now, defaulting to the production 4.0 / 25.0, so two layers can differ in nothing else. Listed in l0_b300.yml. Signed-off-by: Xin Guan <294044352+xguannv@users.noreply.github.com>
Signed-off-by: Xin Guan <294044352+xguannv@users.noreply.github.com>
Signed-off-by: Xin Guan <294044352+xguannv@users.noreply.github.com>
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Port the MoE feature family from the Rubin development branch that main does not already carry: * PDL launch support in the SiTU Triton kernel (`_torch/modules/situ.py`), gated on `get_env_enable_pdl()` and SM >= 90. * `_Pointer.__add__` in `_torch/cute_dsl_kernels/rubin/moe/utils.py`, so a Rubin device pointer can be offset by an element count with the alignment narrowed to the real `gcd`. * A `moe_a2a_cft_release` hook on the NVLink one-sided teardown path: the C++ CFT logical endpoint is destroyed before the last Python reference to its MNNVL backing memory is dropped. * MegaMoE DeepGEMM rendezvous: trust `MASTER_ADDR`/`MASTER_PORT`/`RANK`/ `WORLD_SIZE` only when they actually describe this MPI world, so a disaggregated launcher's outer world cannot be adopted by an inner one. * Duplicate routing-input warnings demoted to debug across the TRTLLM-Gen MoE ops, except `fp4BlockScaleMoe.cpp` -- see below. * Drop the unused `<ATen/native/cuda/Resize.h>` includes from `moeOp.cpp` and `moeUtilOp.cpp`. * An NVFP4 SiTU MoE unit test, on the B200 L0 list. `cpp/tensorrt_llm/thop/moe/fp4BlockScaleMoe.cpp` is deliberately left byte-identical to main. The EP-aware padded-token sizing this series carried for it (`num_experts` -> `local_num_experts` for `getMaxPermutedPaddedCount` and `getMaxNumCtasInBatchDim`) is under separate review in NVIDIA#19251: `routingIndicesWarpKernel` in `RoutingLlama4.cu` counts tokens ungated by `isLocalExpert` and writes a global expert id as the CTA batch index, so the smaller allocation can be written out of bounds on the Llama4 routing path. That change and the one-line log-level demote for the same file travel with NVIDIA#19251 rather than with SM107 enablement. Two things this series used to carry are now main's and are not restated here. `CuteDslFusedMoE.run_moe_nvfp4` already admits `ActivationType.SiTu` after NVIDIA#19003, so `fused_moe_cute_dsl.py` is left byte-identical to main. And the MegaMoE NVFP4 CuteDSL kernel tree that lived in `_torch/cute_dsl_kernels/mega_moe_nvfp4/` was deleted by PR NVIDIA#17956 and replaced with `_torch/cute_dsl_kernels/cutedsl_megamoe/`, which already carries the same SM107 work (renamed: `build_sm107_static_idesc_base` -> `build_static_idesc_base`, `Sm107MegaMoEKernel` -> `rubin/inference/mega/BlockScaledSwapAbMegaMoeKernel`, and so on). The `CuteDslFc12FusedMoE` backend and the Rubin fused-FC12 GEMM landed upstream too.
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Port the MoE feature family from the Rubin development branch that main does not already carry: * PDL launch support in the SiTU Triton kernel (`_torch/modules/situ.py`), gated on `get_env_enable_pdl()` and SM >= 90. * `_Pointer.__add__` in `_torch/cute_dsl_kernels/rubin/moe/utils.py`, so a Rubin device pointer can be offset by an element count with the alignment narrowed to the real `gcd`. * A `moe_a2a_cft_release` hook on the NVLink one-sided teardown path: the C++ CFT logical endpoint is destroyed before the last Python reference to its MNNVL backing memory is dropped. * MegaMoE DeepGEMM rendezvous: trust `MASTER_ADDR`/`MASTER_PORT`/`RANK`/ `WORLD_SIZE` only when they actually describe this MPI world, so a disaggregated launcher's outer world cannot be adopted by an inner one. * Duplicate routing-input warnings demoted to debug across the TRTLLM-Gen MoE ops, except `fp4BlockScaleMoe.cpp` -- see below. * Drop the unused `<ATen/native/cuda/Resize.h>` includes from `moeOp.cpp` and `moeUtilOp.cpp`. * An NVFP4 SiTU MoE unit test, on the B200 L0 list. `cpp/tensorrt_llm/thop/moe/fp4BlockScaleMoe.cpp` is deliberately left byte-identical to main. The EP-aware padded-token sizing this series carried for it (`num_experts` -> `local_num_experts` for `getMaxPermutedPaddedCount` and `getMaxNumCtasInBatchDim`) is under separate review in NVIDIA#19251: `routingIndicesWarpKernel` in `RoutingLlama4.cu` counts tokens ungated by `isLocalExpert` and writes a global expert id as the CTA batch index, so the smaller allocation can be written out of bounds on the Llama4 routing path. That change and the one-line log-level demote for the same file travel with NVIDIA#19251 rather than with SM107 enablement. Two things this series used to carry are now main's and are not restated here. `CuteDslFusedMoE.run_moe_nvfp4` already admits `ActivationType.SiTu` after NVIDIA#19003, so `fused_moe_cute_dsl.py` is left byte-identical to main. And the MegaMoE NVFP4 CuteDSL kernel tree that lived in `_torch/cute_dsl_kernels/mega_moe_nvfp4/` was deleted by PR NVIDIA#17956 and replaced with `_torch/cute_dsl_kernels/cutedsl_megamoe/`, which already carries the same SM107 work (renamed: `build_sm107_static_idesc_base` -> `build_static_idesc_base`, `Sm107MegaMoEKernel` -> `rubin/inference/mega/BlockScaledSwapAbMegaMoeKernel`, and so on). The `CuteDslFc12FusedMoE` backend and the Rubin fused-FC12 GEMM landed upstream too. Signed-off-by: Lizhi Zhou <1432185+reasonsolo@users.noreply.github.com>
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Port the MoE feature family from the Rubin development branch that main does not already carry: * PDL launch support in the SiTU Triton kernel (`_torch/modules/situ.py`), gated on `get_env_enable_pdl()` and SM >= 90. * `_Pointer.__add__` in `_torch/cute_dsl_kernels/rubin/moe/utils.py`, so a Rubin device pointer can be offset by an element count with the alignment narrowed to the real `gcd`. * A `moe_a2a_cft_release` hook on the NVLink one-sided teardown path: the C++ CFT logical endpoint is destroyed before the last Python reference to its MNNVL backing memory is dropped. * MegaMoE DeepGEMM rendezvous: trust `MASTER_ADDR`/`MASTER_PORT`/`RANK`/ `WORLD_SIZE` only when they actually describe this MPI world, so a disaggregated launcher's outer world cannot be adopted by an inner one. * An NVFP4 SiTU MoE unit test, on the B200 L0 list. Every `cpp/tensorrt_llm/thop/` translation unit this series used to touch is now left byte-identical to main. The EP-aware padded-token sizing carried for `fp4BlockScaleMoe.cpp` (`num_experts` -> `local_num_experts` for `getMaxPermutedPaddedCount` and `getMaxNumCtasInBatchDim`) is under separate review in NVIDIA#19251: `routingIndicesWarpKernel` in `RoutingLlama4.cu` counts tokens ungated by `isLocalExpert` and writes a global expert id as the CTA batch index, so the smaller allocation can be written out of bounds on the Llama4 routing path. The duplicate-routing-input log-level demote and the unused `<ATen/native/cuda/Resize.h>` include removals are unrelated to SM107 enablement and are dropped from this series; `th_common` is already built as C++20 on main, so those includes cost nothing but a line. Two things this series used to carry are now main's and are not restated here. `CuteDslFusedMoE.run_moe_nvfp4` already admits `ActivationType.SiTu` after NVIDIA#19003, so `fused_moe_cute_dsl.py` is left byte-identical to main. And the MegaMoE NVFP4 CuteDSL kernel tree that lived in `_torch/cute_dsl_kernels/mega_moe_nvfp4/` was deleted by PR NVIDIA#17956 and replaced with `_torch/cute_dsl_kernels/cutedsl_megamoe/`, which already carries the same SM107 work (renamed: `build_sm107_static_idesc_base` -> `build_static_idesc_base`, `Sm107MegaMoEKernel` -> `rubin/inference/mega/BlockScaledSwapAbMegaMoeKernel`, and so on). The `CuteDslFc12FusedMoE` backend and the Rubin fused-FC12 GEMM landed upstream too. Signed-off-by: Lizhi Zhou <1432185+reasonsolo@users.noreply.github.com>
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Sep 22, 2026
Port the MoE feature family from the Rubin development branch that main does not already carry: * PDL launch support in the SiTU Triton kernel (`_torch/modules/situ.py`), gated on `get_env_enable_pdl()` and SM >= 90. * `_Pointer.__add__` in `_torch/cute_dsl_kernels/rubin/moe/utils.py`, so a Rubin device pointer can be offset by an element count with the alignment narrowed to the real `gcd`. * A `moe_a2a_cft_release` hook on the NVLink one-sided teardown path: the C++ CFT logical endpoint is destroyed before the last Python reference to its MNNVL backing memory is dropped. * MegaMoE DeepGEMM rendezvous: trust `MASTER_ADDR`/`MASTER_PORT`/`RANK`/ `WORLD_SIZE` only when they actually describe this MPI world, so a disaggregated launcher's outer world cannot be adopted by an inner one. The NVFP4 SiTU MoE unit test that accompanied this work, its `l0_b200` entry and the de-duplication of the overlapping tactic-reachability case in `tests/unittest/_torch/thop/serial/test_moe.py` are not part of this series; this PR carries the production change only. Every `cpp/tensorrt_llm/thop/` translation unit this series used to touch is now left byte-identical to main. The EP-aware padded-token sizing carried for `fp4BlockScaleMoe.cpp` (`num_experts` -> `local_num_experts` for `getMaxPermutedPaddedCount` and `getMaxNumCtasInBatchDim`) is under separate review in NVIDIA#19251: `routingIndicesWarpKernel` in `RoutingLlama4.cu` counts tokens ungated by `isLocalExpert` and writes a global expert id as the CTA batch index, so the smaller allocation can be written out of bounds on the Llama4 routing path. The duplicate-routing-input log-level demote and the unused `<ATen/native/cuda/Resize.h>` include removals are unrelated to SM107 enablement and are dropped from this series; `th_common` is already built as C++20 on main, so those includes cost nothing but a line. Two things this series used to carry are now main's and are not restated here. `CuteDslFusedMoE.run_moe_nvfp4` already admits `ActivationType.SiTu` after NVIDIA#19003, so `fused_moe_cute_dsl.py` is left byte-identical to main. And the MegaMoE NVFP4 CuteDSL kernel tree that lived in `_torch/cute_dsl_kernels/mega_moe_nvfp4/` was deleted by PR NVIDIA#17956 and replaced with `_torch/cute_dsl_kernels/cutedsl_megamoe/`, which already carries the same SM107 work (renamed: `build_sm107_static_idesc_base` -> `build_static_idesc_base`, `Sm107MegaMoEKernel` -> `rubin/inference/mega/BlockScaledSwapAbMegaMoeKernel`, and so on). The `CuteDslFc12FusedMoE` backend and the Rubin fused-FC12 GEMM landed upstream too. Signed-off-by: Lizhi Zhou <1432185+reasonsolo@users.noreply.github.com>
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Description
Enable explicitly selected CUTEDSL routed experts for Kimi K3 NVFP4 on SM100/SM103. The Blackwell kernel already implements SiTU in the rebased main; this change enables it through the MoE capability declaration and K3 backend selection, forwards both soft-caps, and rejects an explicit CUTEDSL request that cannot be served instead of silently selecting CUTLASS.
The Blackwell custom op and fake schema use
Optional[float] = Nonedirectly. SiTU constants must be finite and positive. SM107 end-to-end SiTU integration remains gated; existing Rubin ops retain their separate legacy sentinel API.Review coverage
BACKEND_FAMILYand check exact agreement with the K3 allow-list.KimiK3MoERuntime/ resolver call chain with CUTEDSL ineligible and CUTLASS eligible; require an explicit rejection, with an allowed-degradation positive control.(4,25),(2,25),(4,10),(2,10)and verify distinct runner identities and numerical outputs.l0_b300.yml. Keep the numerical discriminator's CI selection focused on CUTEDSL as requested; retain the existing TRTLLM selector. Update the upstream Blackwell direct-op test to useNonefor absent SiTU parameters.Validation
Current PR head:
e04607744e7571a9817ce4bc0add0434591366f5. GPU validation ran at74a480e98701ba8423151f68503edd5e6db31e7b; the only subsequent change restores three example files to the base version. Implementation, unit tests, and CI selectors are unchanged. The DEP16 quickstart result below used the earlier example launcher with explicit backend selection. The branch was rebased onto63e64e5bdb447af0eb12b5b6ca6a185483131783.OCIAGA GB300/SM103, image
trtllm-ociaga-gb300-k3-base-nsys2025.5-20260916.sqsh;libtensorrt_llm.soSHA2563eac19a923ae4df65df65bd63d03a64d5716f5ce298424433738eeabc78b5eeb. Build job 802376 usedad95dd32a303; the GPU-validated candidate differs only in the CI selector YAML.GSM8K used
nvidia_kimi-k3-nvfp4/hf/hf-f8c5234_orig, 4 nodes × 4 GPUs in one NVLink segment, DEP16, batch size 8, KV fraction 0.35, 5-shot, all 1319/1319 questions, and a 256-token output limit. Nodes:nvl72d136-T[02,07-09].The same GSM8K run recorded both
CuteDslFusedMoE::run_moe_nvfp4andtrtllm::cute_dsl_nvfp4_gather_grouped_gemm_act_fusion_blackwellon every rank 0–15. These are runtime call-path records, emitted once per rank during warmup, rather than per-question kernel counts. There were notrtllm::fused_moe::gemm1records or resolver declines. The four soft-cap unit cases had relative L2 errors 0.164376 / 0.167295 / 0.165008 / 0.167400.These are local cluster validation results, not a claim that official PR GPU CI has passed. No performance improvement or backend ranking is claimed.
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