[None][feat] add VisualGen VSA and SOL sparse attention on PrimTS block-sparse FMHA by heyuhhh · Pull Request #18079 · NVIDIA/TensorRT-LLM

heyuhhh · 2026-08-21T16:16:30Z

Description

VisualGen sparse attention on the PrimTS block-sparse FMHA merged in #18815. VisualGen ships two block-sparse algorithms for DiT video models; this PR gives both a TRTLLM backend (Triton predictor + generic block-sparse FMHA) next to the existing CuTeDSL kernels, selected by AttentionConfig.backend under one configuration per algorithm:

VSA (VideoSparseAttentionConfig): coarse/fine Video Sparse Attention for the FastVideo VSA checkpoints. Metadata, route prediction and post-processing are shared by the TRTLLM and CuTeDSL backends (attention_backend/sparse/vsa); the TRTLLM backend runs the top-k prediction as Triton kernels and the fine stage through the block-sparse FMHA, with dense fallback, packed or separate QKV, TP, Ulysses and CUDA Graph support.
SOL (SolAttentionConfig: tau, thresh_type, disabled_until_timestep, dense_layers): the TRTLLM backend runs the SOL predictor as a functional Triton operator (block pooling, key statistics, diag/exact thresholds, exact-block selection) and executes the exact blocks plus proxy K/V summaries through the block-sparse FMHA (proxy-compensated attention from feat(prims-ts): support proxy-compensated block-sparse attention flashinfer-ai/flashinfer#4872). The fused CuTeDSL Sol-Attn kernel of [TRTLLM-15917][feat] Integrate Sol-Attn sparse attention into VisualGen #18329 stays as the CUTEDSL backend of the same config.
Shared pieces: one timestep-to-phase reduction (attention/backends/sparse/timestep_phase.py) used by SkipSoftmax, both SOL backends and a single sparse_attn_phase CUDA Graph key; the VisualGen TRTLLM wrapper passes separate Q/K/V and block-sparse routes into the core for sparse calls, fuses QKV for the dense-layer and dense-phase calls of a route-predicting backend (the TRTLLM kernel serves dense self-attention from fused QKV only), and shares one FMHA plan cache per model component through the new optional fmha_state constructor argument of TrtllmAttention. These two are the only core attention changes.
The sparse TRTLLM backends reject cross-attention, context parallelism and attention quantization; dense layers and dense timestep phases return no routes and run the dense kernel.

Behavior notes: per-token timesteps reduce to their largest live value, so a Wan 2.2 5B I2V conditioning frame at timestep zero no longer disables a configured dense prefix; SkipSoftmax dense and sparse CUDA graphs are keyed per phase on every model with a cutoff, including LTX-2. Docs: docs/source/features/visualgen-sparse-attention.md (per-algorithm guide) and the SOL-Attn column in docs/source/models/visual-generation.md.

Performance and accuracy of the TRTLLM backends

One B200, Wan2.1-VSA-T2V-14B-720P, 720x1280, seed 42, guidance 5.0, prompt "A cat sitting on a sunny windowsill watching birds outside.", CUDA Graph on, torch.compile off. Long = 81 frames (75,600 tokens per stream), Short = 9 frames (10,800 tokens). Deployment settings follow the documentation: SOL tau=1.0, diag, disabled_until_timestep=0.6, dense_layers=[0, 2, 3, 4], which on this checkpoint's UniPC schedule (flow shift 3.0) runs 34 of 50 steps dense and 16 sparse; VSA has no dense prefix or dense-layer option and follows the checkpoint recipe, sparsity 0.9 at 81 frames and 0.875 at 9 frames. LPIPS is AlexNet on the raw frames, scaled to [-1, 1], mean over frames (the normalization of scripts/visualgen_eval/visual_gen_lpips_score_eval.py); scoring the same clips as H.264 MP4 agrees within 0.005 except on near-identical pairs, where the codec adds 0.01 to 0.015.

End to end, 50 denoising steps (the timed request after warmup and one settle request):

Workload	Algorithm	Backend	50-step denoise s	Speedup vs dense	Speedup vs CuTeDSL
Long	dense	TRTLLM	584.4	1.00x	–
Long	dense	CuTeDSL	599.7	0.97x	–
Long	SOL	CuTeDSL	560.2	1.04x	–
Long	SOL	TRTLLM	518.6	1.13x	1.08x
Long	VSA	CuTeDSL	371.0	1.58x	–
Long	VSA	TRTLLM	325.6	1.79x	1.14x
Short	dense	TRTLLM	40.0	1.00x	–
Short	SOL	CuTeDSL	39.8	1.00x	–
Short	SOL	TRTLLM	38.6	1.04x	1.03x
Short	VSA	CuTeDSL	41.1	0.97x	–
Short	VSA	TRTLLM	38.7	1.03x	1.06x

Sparse phase alone (the dense prefix disabled so every timed step is sparse; ms per self-attention call, mean over 40 layers and 24 Long / 48 Short timed steps, CUDA events inside the captured graph). This is the kernel-level comparison the end-to-end numbers are built from:

Workload	Algorithm	Backend	Attention ms/call	Speedup vs dense	Speedup vs CuTeDSL	Transformer step ms	Step speedup vs dense	Step speedup vs CuTeDSL
Long	dense	TRTLLM	183.71	1.00x	–	11,709	1.00x	–
Long	SOL	CuTeDSL	127.70	1.44x	–	9,218	1.27x	–
Long	SOL	TRTLLM	60.27	3.05x	2.12x	6,937	1.69x	1.33x
Long	VSA	CuTeDSL	68.76	2.67x	–	7,451	1.57x	–
Long	VSA	TRTLLM	42.82	4.29x	1.61x	6,474	1.81x	1.15x
Short	dense	TRTLLM	4.31	1.00x	–	797.0	1.00x	–
Short	SOL	CuTeDSL	4.04	1.07x	–	763.8	1.04x	–
Short	SOL	TRTLLM	1.90	2.27x	2.12x	693.7	1.15x	1.10x
Short	VSA	CuTeDSL	3.92	1.10x	–	815.0	0.98x	–
Short	VSA	TRTLLM	2.27	1.90x	1.72x	760.4	1.05x	1.07x

On Long the TRTLLM backends spend 2.7 ms (SOL) and 5.8 ms (VSA) per call in the Triton predictors, against 7.2 ms of in-kernel preprocessing for SOL CuTeDSL and 15.8 ms for the VSA CuTeDSL predictor; the rest of the gap is the block-sparse FMHA itself (57.6 vs 120.5 ms for SOL, 36.0 vs 52.0 ms for VSA). The end-to-end SOL speedup is smaller than the per-call one because the documented example runs 34 of 50 steps and 4 of 40 layers dense.

LPIPS under the deployment settings (mean over frames; lower is closer). The dense TRTLLM pipeline is bit-exact run to run and between eager and CUDA Graph, so every non-zero value is kernel numerics amplified by the sampler; two exact dense kernels (TRTLLM vs CuTeDSL) already differ by 0.30 after 50 steps, which is the floor for any cross-kernel pair:

Pair	Long	Short
dense TRTLLM vs dense CuTeDSL (exact-kernel floor)	0.303	0.152
SOL TRTLLM vs dense TRTLLM (its own dense kernel)	0.010	0.030
SOL CuTeDSL vs dense CuTeDSL (its own dense kernel)	0.008	0.026
SOL TRTLLM vs SOL CuTeDSL (prefixes run different dense kernels)	0.304	0.153
VSA TRTLLM vs VSA CuTeDSL	0.154	0.419
VSA TRTLLM vs dense TRTLLM / VSA CuTeDSL vs dense TRTLLM	0.836 / 0.844	0.522 / 0.473

With the dense prefix, each SOL backend reproduces the sample of its own dense kernel (PSNR 38 dB on Long), and the two SOL backends differ from each other by exactly the dense-kernel floor. VSA converges to a different, clean sample than dense at 0.9 sparsity; both VSA backends agree on that sample within the floor on Long, and the Short VSA pair (0.42) is the most sensitive case (same scene, different framing, at a 9-frame workload the VSA checkpoint was not trained for). With the SOL prefix disabled entirely, SOL likewise converges to its own sample (LPIPS 0.79 vs dense for both backends, 0.10 between them). Kernel-level closeness is asserted by the parity tests in sparse_attention/{sol,vsa}/test_*_parity.py.

Test Coverage

Unit tests live in tests/unittest/_torch/visual_gen/sparse_attention/{skip_softmax,sol,vsa}/, mirroring tests/unittest/_torch/attention/sparse: per algorithm the backend behavior tests, the kernel tests and a parity module that runs the TRTLLM and CuTeDSL backends on the same inputs and compares them with dense attention and with each other (the SOL parity sweeps tau 2 / 1 / 0 against the exact-block/proxy-summary contract of the predicted routes, and runs a dense layer and a dense-phase step of the TRTLLM backend through the real kernel against dense attention). l0_b200.yml registers the VSA and SOL modules and test_trtllm_attention_metadata.py (TRTLLM skip-softmax CUDA Graph capture under an SM100 gate); l0_b300.yml registers the SOL module for the sm103 stage in place of the merged CuTeDSL file; l0_cpu.yml registers the skip-softmax module and the CPU-only parts of the SOL modules.

Run on B200 with an SM100 build (CUTLASS DSL 4.8.0.dev0; the changes are Python-only):

sparse_attention/sol/ after the dense-call fix: GPU stage (-m "not cpu_only") 61 passed, CPU stage (-m cpu_only, CUDA hidden) 73 passed; the whole sparse_attention/ CPU stage 185 passed. The deployment-setting measurements above were taken with that fix.
Before that fix, on main a1c6c2b: sparse_attention/ GPU stage 142 passed plus the 14 SOL parity cases; CPU stage 113 passed.
test_attention_integration.py, test_fa4_cutlass_compatibility.py and the VSA kernel tests: 129 passed.
Core test_attention_mla.py, test_fmha_manager.py, test_fmha_registry.py, sparse/test_flashinfer_utils.py: 205 passed, 1 skipped.
test_ltx2_pipeline.py and test_ltx2_transformer.py: 67 passed. HunyuanVideo 1.5 and GLM-Image test_fp8_trtllm_attention: 2 passed. test_wan_vsa_pipeline.py::TestWanVsa14B_PipelineCorrectness::test_cosine_similarity: 1 passed.
CUDA hidden (the CPU stages): sparse_attention/, test_visual_gen_args.py, test_trtllm_attention_metadata.py, test_timestep_phase.py: 188 passed, 29 skipped.
Multi-GPU Wan VSA TP/Ulysses parity was verified on the previous stack; the 8-GPU Wan VSA parity case has a pre-existing numerical tolerance gap that reproduces on the original VSA source commit.
End-to-end Wan 2.1 14B generations at 720x1280 with 9 and 81 frames ran for all five implementations under CUDA Graph with the deployment settings above (the tables in the previous section).

PR Checklist

PR title follows the template
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Dev Engineer Review

Adds VSA and SOL support through generic PrimTS block-sparse FMHA.
Adds TRT-LLM and CuTeDSL VSA backends, dense fallback, packed/separate QKV, TP, Ulysses, and CUDA Graph support.
Adds SOL configuration, routing, Triton kernels, and shape-specialized predictor plans.
Centralizes timestep reduction and sparse graph-phase handling.
Removes the legacy CuTeDSL VSA implementation and exports. Verify downstream imports.
VSA rejects quantized attention. VSA and SOL reject context parallelism. SOL rejects Torch fullgraph compilation.
LTX-2 now passes raw denoising timesteps to attention.
Verify fallback paths, custom operators, plan preparation, graph capture, tensor validation, and multi-GPU execution.
CI follow-up is required because reported merge pipelines include failures and an unstable result.

QA Engineer Review

Adds VSA, SOL, multi-GPU, LTX-2, TRT-LLM metadata, SkipSoftmax, and configuration tests.
Covers dispatch, validation, fallback, metadata, routing, kernels, numerical parity, compilation, custom operators, CUDA Graph replay, TP, and Ulysses behavior.
Removes the legacy CuTeDSL VSA test module.
Updates l0_b200.yml and l0_cpu.yml with VSA, SOL, CUDA Graph, metadata, backend, and predictor entries.
No manual-QA list changes are provided.
Coverage verdict: needs follow-up because CI reported failures and multi-GPU execution requires approval.

Per-File QA Perspective

VSA and SOL source files: Verify backend dispatch, validation, dense fallback, metadata caching, route prediction, post-processing, Triton/PyTorch parity, and CUDA Graph behavior.
TRT-LLM and attention files: Verify timestep scheduling, sparse phase selection, QKV routing, cache reuse, and sparse argument forwarding.
VisualGen configuration files: Verify SOL fields, dense-layer parsing, compatibility rules, quantization restrictions, and fullgraph validation.
Model and pipeline files: Verify raw timestep propagation, graph keys, VSA builder lifecycle, TP sharding, and async Ulysses forwarding.
Removed CuTeDSL VSA files and exports: Verify no stale imports remain.
Documentation files: Verify documented backend support, fallback behavior, validation rules, and CUDA Graph behavior.
l0_b200.yml: Adds B200 VSA, SOL, CUDA Graph, and metadata coverage.
l0_cpu.yml: Adds CPU SOL backend and predictor coverage.
VSA tests: Cover backend contracts, metadata, fallback, routing, kernels, parity, packed QKV, and graph replay. Full CI mapping is not established.
SOL tests: Cover backend behavior, predictor plans, kernels, validation, compilation, custom operators, and graph replay. CPU and B200 entries are listed.
Multi-GPU tests: Cover async gate redistribution and TP-local dimensions. CI execution requires the reported approval label.
LTX-2, TRT-LLM metadata, SkipSoftmax, argument, and WAN tests: Cover sparse phase keys, raw timesteps, metadata lifecycle, dispatch, configuration validation, TP-aligned gates, and Ulysses forwarding.

tensorrt-cicd · 2026-09-21T18:22:02Z

PR_Github #74760 [ run ] completed with state SUCCESS. Commit: 0f0ac14
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chang-l · 2026-09-21T18:05:59Z

+import torch
+
+
+def timestep_to_float(timestep: object) -> Optional[float]:


@bobboli can you please help review the ss-related changes?

Mirror tests/unittest/_torch/attention/sparse: each algorithm owns a folder under visual_gen/sparse_attention with its backend behavior tests, its kernel tests and a parity module that runs the TRTLLM and CuTeDSL backends on the same inputs and compares them with dense attention and with each other. The CuTeDSL SOL tests merge into the SOL behavior module, the VSA module tests leave the attention integration module, and the CPU and B200 test lists follow the new paths. The SOL parity module sweeps the routing threshold from a value few blocks reach to one most blocks clear and checks both backends against the exact-token/proxy-summary contract of the routes the predictor emits, so a backend that routes a borderline block differently fails locally instead of hiding behind a global similarity to dense attention. Signed-off-by: yuhangh <58161490+heyuhhh@users.noreply.github.com>

…n the model matrix Replace the VSA section of the model guide with a short overview of the three sparse attention algorithms that points to the feature guide, and move the VSA requirements, configuration and examples into the feature guide next to the SOL section. The feature matrix now carries a SOL-Attn column: SOL is a runtime feature of the TRTLLM and CuTeDSL backends, while VSA needs a fine-tuned checkpoint and stays a model row. Signed-off-by: yuhangh <58161490+heyuhhh@users.noreply.github.com>

heyuhhh · 2026-09-22T05:39:40Z

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heyuhhh · 2026-09-22T06:08:31Z

Thanks for the clarifications; my two comments are resolved (one withdrawn, one a pre-existing gap for a follow-up). LGTM. It would be good to add LPIPS and speedup numbers for the new TRTLLM SOL/VSA backends to the description.

Hi @karljang , I have updated the description and added the LPIPS and Speedups with the PrimsTS kernels. Could you help check the results of LPIPS? Because i found that the case of dense TRTLLM v.s. dense CuteDSL has a LPIPS value of 0.303, it's a little strange for me. The others looks make sense and consistent for me.

tensorrt-cicd · 2026-09-22T09:41:39Z

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SOLTrtllmAttention reports support_fused_qkv() == False because its in-core route prediction needs separate Q, K and V, and the VisualGen TRTLLM wrapper turned that into "always pass separate tensors". A dense layer or a dense-phase step returns no routes, so the core fell back to the standard TRTLLM attention op, which serves dense self-attention from fused QKV only and failed with "only fused QKV is supported now". The documented SOL configuration (disabled_until_timestep with dense_layers) therefore could not run on the TRTLLM backend, in eager mode or under CUDA Graph capture. The wrapper now requests separate Q, K and V from such a backend only for calls that run its sparse path; dense-layer and dense-phase calls take the existing fused path. The decision uses the host timestep the metadata adapter prepares, and the sparse phase is already part of the CUDA Graph key, so both phases capture. SkipSoftmax and VSA report fused support and are unchanged. Tests: the SOL behavior module checks that dense-layer and dense-phase calls reach the stubbed core as fused QKV without prediction; the SOL parity module runs the real op for a dense layer and a dense-phase step against dense attention with no block-sparse launch, then a sparse step of the same backend through the block-sparse FMHA. Signed-off-by: yuhangh <58161490+heyuhhh@users.noreply.github.com>

The per-algorithm test reorganization merged tests/unittest/_torch/visual_gen/test_attention_cute_dsl_sol_attn.py into sparse_attention/sol/test_sol_attention.py and removed the old file, but l0_b300.yml still listed the old path, so the B300 unit-test stage failed to collect it. The list validator only checks entries with node ids, which is why the stale file entry passed pre-commit. The replacement module carries the same CuTeDSL SOL tests under the same CUDA gate. Signed-off-by: yuhangh <58161490+heyuhhh@users.noreply.github.com>

heyuhhh · 2026-09-22T13:19:57Z

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github-actions Bot assigned heyuhhh Aug 21, 2026

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This was referenced Aug 25, 2026

[None][feat] add generic PrimTS block-sparse FMHA yuxianq/TensorRT-LLM#2

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[None][feat] align VisualGen VSA with block-sparse FMHA heyuhhh/TensorRT-LLM#7

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heyuhhh force-pushed the user/yuhangh/update_vsa branch from 10fbec9 to 7446583 Compare August 25, 2026 14:26

heyuhhh changed the title ~~[None][feat] enable PrimTS block-sparse attention for VisualGen VSA~~ [None][feat] integrate VisualGen VSA with block-sparse FMHA Aug 25, 2026

heyuhhh force-pushed the user/yuhangh/update_vsa branch 11 times, most recently from ad0165b to 6e34838 Compare September 4, 2026 14:55

heyuhhh mentioned this pull request Sep 7, 2026

[None][feat] add generic PrimTS block-sparse FMHA and unify sparse attention runtime inputs #18815

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heyuhhh force-pushed the user/yuhangh/update_vsa branch from 6e34838 to 39c3ebb Compare September 7, 2026 09:18

heyuhhh changed the title ~~[None][feat] integrate VisualGen VSA with block-sparse FMHA~~ [None][feat] VisualGen VSA and SOL sparse attention on PrimTS block-sparse FMHA (overview) Sep 7, 2026

heyuhhh mentioned this pull request Sep 7, 2026

[None][feat] add VisualGen SOL sparse attention heyuhhh/TensorRT-LLM#9

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heyuhhh force-pushed the user/yuhangh/update_vsa branch 9 times, most recently from a912915 to e4d992d Compare September 8, 2026 03:32

chang-l reviewed Sep 21, 2026

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heyuhhh force-pushed the user/yuhangh/update_vsa branch from 75fca39 to f5046d3 Compare September 22, 2026 03:15

Merge branch 'main' into user/yuhangh/update_vsa

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heyuhhh requested a review from weiminwang-nv September 22, 2026 03:25

chang-l requested a review from bobboli September 22, 2026 05:35

heyuhhh added 3 commits September 22, 2026 12:31

Merge branch 'main' into user/yuhangh/update_vsa

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Merge branch 'main' into user/yuhangh/update_vsa

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		import torch


		def timestep_to_float(timestep: object) -> Optional[float]:

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Performance and accuracy of the TRTLLM backends

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