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core_complex: fix uint64_t overflow issue #49

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Merged
eyck merged 2 commits into from
Apr 21, 2026
+11 −7
Merged

core_complex: fix uint64_t overflow issue #49

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fc4fca5
core_complex: fix uint64_t overflow issue
sanpar-qcom Apr 14, 2026
9a28fe8
core_complex: simplify end range check logics/functions
sanpar-qcom Apr 21, 2026
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18 changes: 11 additions & 7 deletions src/sysc/core_complex.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -88,6 +88,10 @@ using namespace sc_core;
namespace {
iss::debugger::encoder_decoder encdec;
std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};

inline bool is_in_end_range(uint64_t end, uint64_t inclusive_range_end) {
return (end <= inclusive_range_end) || ((end >= 0) && ((end - 1) <= inclusive_range_end));
}
} // namespace

template <unsigned int BUSWIDTH, typename QK>
Expand Down Expand Up @@ -191,20 +195,20 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::i
core_complex_if::exec_on_sysc = util::delegate<void(std::function<void(void)>&)>::from<this_class, &this_class::exec_on_sysc<QK>>(this);
ibus.register_invalidate_direct_mem_ptr([this](uint64_t start, uint64_t end) -> void {
auto lut_entry = fetch_lut.getEntry(start);
if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && is_in_end_range(end, lut_entry.get_end_address())) {
fetch_lut.removeEntry(lut_entry);
}
});
dbus.register_invalidate_direct_mem_ptr([this](uint64_t start, uint64_t end) -> void {
for(auto& read_lut : dmi_read_luts) {
auto lut_entry = read_lut.getEntry(start);
if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && is_in_end_range(end, lut_entry.get_end_address())) {
read_lut.removeEntry(lut_entry);
}
}
for(auto& write_lut : dmi_write_luts) {
auto lut_entry = write_lut.getEntry(start);
if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && is_in_end_range(end, lut_entry.get_end_address())) {
write_lut.removeEntry(lut_entry);
}
}
Expand Down Expand Up @@ -396,7 +400,7 @@ bool core_complex<BUSWIDTH, QK>::read_mem(const addr_t& addr, unsigned length, u
bool is_fetch = addr.space == std::numeric_limits<decltype(addr.space)>::max() ? true : false;
auto& dmi_lut = is_fetch ? fetch_lut : get_read_lut(addr.space);
auto lut_entry = dmi_lut.getEntry(addr.val);
if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && (addr.val + length) <= (lut_entry.get_end_address() + 1)) {
if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && is_in_end_range(addr.val + length, lut_entry.get_end_address())) {
auto offset = addr.val - lut_entry.get_start_address();
std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
if(is_fetch)
Expand Down Expand Up @@ -450,7 +454,7 @@ bool core_complex<BUSWIDTH, QK>::read_mem(const addr_t& addr, unsigned length, u
gp.set_address(addr.val);
tlm_dmi_ext dmi_data;
if(exec_get_direct_mem_ptr(gp, dmi_data)) {
if(dmi_data.is_read_allowed() && (addr.val + length - 1) <= dmi_data.get_end_address())
if(dmi_data.is_read_allowed() && is_in_end_range(addr.val + length, dmi_data.get_end_address()))
dmi_lut.addEntry(dmi_data, dmi_data.get_start_address(), dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
}
}
Expand All @@ -461,7 +465,7 @@ bool core_complex<BUSWIDTH, QK>::read_mem(const addr_t& addr, unsigned length, u
template <unsigned int BUSWIDTH, typename QK>
bool core_complex<BUSWIDTH, QK>::write_mem(const addr_t& addr, unsigned length, const uint8_t* const data) {
auto lut_entry = get_write_lut(addr.space).getEntry(addr.val);
if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && (addr.val + length) <= (lut_entry.get_end_address() + 1)) {
if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && is_in_end_range(addr.val + length, lut_entry.get_end_address())) {
auto offset = addr.val - lut_entry.get_start_address();
std::copy(data, data + length, lut_entry.get_dmi_ptr() + offset);
dbus_inc += lut_entry.get_write_latency() / curr_clk;
Expand Down Expand Up @@ -508,7 +512,7 @@ bool core_complex<BUSWIDTH, QK>::write_mem(const addr_t& addr, unsigned length,
gp.set_address(addr.val);
tlm_dmi_ext dmi_data;
if(exec_get_direct_mem_ptr(gp, dmi_data)) {
if(dmi_data.is_write_allowed() && (addr.val + length - 1) <= dmi_data.get_end_address())
if(dmi_data.is_write_allowed() && is_in_end_range(addr.val + length, dmi_data.get_end_address()))
get_write_lut(addr.space)
.addEntry(dmi_data, dmi_data.get_start_address(), dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
}
Expand Down
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