VGA working: connect vdma to MIG and vga_out#12
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…rmed - Fix MIG AXI slave perpetual reset: add NOT gate on ui_clk_sync_rst to produce active-low aresetn for SmartConnect, MIG AXI slave, and VDMA - Fix vga_out stuck in reset: was driven by peripheral_reset (always HIGH); now tied to constant-0 via xlconstant_0 - Fix VDMA stream width: set c_m_axis_mm2s_tdata_width=16 to match 16-bit framebuffer pixel format - Fix VDMA register offsets in assemble.py (all were wrong); fix fill loop branch target; write VSIZE last to trigger DMA - Add tools/probe.py: periodic UART monitor (HALT→READ_PC→DUMP_STATE→UNHALT) - Add MEMORY_ERROR state to memory AXI state machine - Cleanup: remove fill_screen.s, ROM_PROGRAMS.md, mig_a.prj, bdelay tests, unused AXI_RESP_* constants; strip hardcoded paths from build.tcl; update docs and README to reflect working state Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
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