GitHub - DavySc/systemverilog-practice · GitHub

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systemverilog-practice

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Name		Name	Last commit message	Last commit date
.gitignore		.gitignore
README.md		README.md
always_fulladder.sv		always_fulladder.sv
d_latch.sv		d_latch.sv
flop.sv		flop.sv
flopr.sv		flopr.sv
fsm.sv		fsm.sv
fulladder.sv		fulladder.sv
gates.sv		gates.sv
inv.sv		inv.sv
mux2.sv		mux2.sv
mux4.sv		mux4.sv
sillyfunction.sv		sillyfunction.sv
synchronizer.sv		synchronizer.sv
tristate.sv		tristate.sv

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An assortment of components written following along to Digital Desing and Computer Architecture by Harris and Harris and other cool sources

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