diff --git a/HANDOVER.md b/HANDOVER.md index 98d3887..e72bd4a 100644 --- a/HANDOVER.md +++ b/HANDOVER.md @@ -42,7 +42,7 @@ manager, CAN 2.0B @500k. Docs 01–07 are the spec; read 05 (build plan) first | Design docs 01–07 | complete (07 = module firmware, new) | | Phase-1 schematic | **complete, v1**: 7 generated sheets, 137 components, ~90 nets machine-verified; audited (kicad-happy + ngspice 38/40 pass) | | Footprints | all vetted; custom lib `labbench.pretty` (LM5145 RGY, LMR36015 RNX, DAC80502 no-EP WSON, PowerFET_SON5x6_GDS) | -| PCB — Phase 1 | **Routed, 0 unconnected, 0 DRC errors** (PR #3, 2026-09-27; review fixes in a follow-up PR from `claude/project-thread-nojoms`): pass-1 + `fanout.py` + Freerouting 1.9 + `finish_routes.py`, then `eco_move.py` for the review moves; 1166 tracks / 357 vias. DRC = 9 silk *warnings* (6 are J1/J4 terminal-block silk over the edge, by design). Fab zip generated. `gen_board.py` PLACEMENT matches the board again (every footprint checked) | +| PCB — Phase 1 | **100 × 80 mm, routed, 0 unconnected, 0 DRC errors** (2026-09-27, draft PR from `claude/phase1-100x80`; the 120 × 80 layout it replaces is kept on branch `phase1-120x80`). Re-placed from the netlist, so L1 now has the 17 mm MWSA1707S/XAL1510 superset land and U7 the SC-70-5 land the BOM orders (the 120 × 80 board still carried XAL1350 and SOT-23-5 lands: do not order it). Output bank tightened round the bigger L1; R30 Kelvin shunt, U4/U5 and their sense traces moved as one block with the same geometry; Q3/Q4, J4 and the LTC7004 stack down the right edge. Pipeline: pass-1 + `fanout.py` + Freerouting 1.9 + `finish_routes.py`; 1303 tracks / 353 vias. DRC = 11 silk *warnings*. Fab zip + CPL regenerated | | PCB — Phase 3 backplane | **FAB-READY (2026-07-26, d9e1a7b)**: 0 DRC, 0 unconnected, silk 39/39 clean, no plane islands. Gerbers+drills in `fab/` (gitignored) via `python3 ../common/finish_board.py phase3-backplane.kicad_pcb`. Cross-checked: Edge_Cuts exactly 330.00×100.00 mm; drills 2×6.4 (M6 lugs), 16×2.8 (8 slots × 2 XT60 pins), 6×3.2 (M3), 86×1.0, 61×0.4. **Still gated on the XT60 polarity buzz-out before ordering** | | PCB — Phase 2 | **83 unconnected, 0 copper DRC, silk clean (2026-07-26, c1a86eb)** — see the resume section; finish by hand in KiCad. Older detail below: | | PCB — Phase 2 (history) | **(2026-07-25, 27fb2d1).** `gen_board.py` placement green (173 comps, all pour/courtyard/edge assertions pass, 130×90 4-layer); `route_board.py` pass-1 done (power pours, In2 heat patches, both phases' gate fan-outs, Kelvin pairs, disconnect trunk). DRC: **copper down to ~19 clearance + ~11 dangling/mask/hole in 3 known clusters** (see resume section); 243 unconnected = signal nets, autoroute not yet run. Found & fixed a real LM5143 land-pattern bug in the process (see load-bearing decisions) | @@ -209,12 +209,14 @@ Notable route_board facts a future session needs: is `common/lcsc_parts.py`; `--check` fails if anything is stale. Still open: generic R/C/jellybean/header numbers, and the `CHECK:` rows in the BOMs (footprint/variant mismatches vs SOURCING.md). -4. **Phase-1 board** — routed (0 unconnected, 0 DRC errors) and its - review items fixed (2026-09-27): C28 sits on U3.20, the VBUS divider +4. **Phase-1 board** — shrunk to 100 × 80 mm and re-routed (0 + unconnected, 0 DRC errors, 2026-09-27) with the BOM's L1 and U7 lands; + the 120 × 80 version (wrong L1/U7 lands) is on branch `phase1-120x80`. + Earlier review items still hold: C28 sits on U3.20, the VBUS divider (R60/R61/C62) sits by U10.14, and every part offset is in `gen_board.py` - PLACEMENT. VOUT_INT's 39.5 mm FB sense run was left as routed: it keeps - 5.5 mm or more from SW copper on every layer and its long end is the - low-impedance output side. Next: owner picks the BOM `CHECK:` parts, + PLACEMENT. The VOUT_INT FB sense run (52 mm, tapped at L1.2) keeps + 5.5 mm or more from SW copper on every layer, enforced by + `tools/fb_reroute.py` after routing. Next: owner picks the BOM `CHECK:` parts, then order. **Gates before ordering ANY board — including the fab-ready backplane:** @@ -316,9 +318,9 @@ by hand. If a DRC report ever shows this class again, suspect the env. - **INA228 ALERT has no external pull-up** in schematic v1 — firmware enables PB7's internal one; add a discrete pull-up in the next schematic rev. - **Grounding**: PGND/AGND split planes joined ONLY at NT1 (net-tie beside the - sense amps); In1 has an AGND pocket under the LTC7004 cluster. Never add a - via that shorts the domains — the seam geometry lives in gen_board.py - (`SEAM`, `AUXW`, `POCKET`). + sense amps). Phase-1 (100 × 80) has no AGND pocket: the LTC7004 cluster + sits below the seam. Never add a via that shorts the domains — the seam + geometry lives in gen_board.py (`SEAM`, `AUXW`). - **Kelvin shunt**: pours grab only the outer halves of R30's pads; sense traces leave the inner edges. Preserve this in any re-layout. - Package truths (all datasheet-verified): LM5145 pin 15 = isolated "EP" diff --git a/hardware/MECHANICAL.md b/hardware/MECHANICAL.md index cc2f8ad..19229f1 100644 --- a/hardware/MECHANICAL.md +++ b/hardware/MECHANICAL.md @@ -25,7 +25,7 @@ component + airflow: | Board | Size | Layers/copper | Notes | |---|---|---|---| | phase2-module | **130 × 90 mm** | 4-layer (stackup below) | grows from P1's 120×80 for hot-swap + 4 FETs; XT60PW-M + signal row on the bottom edge (power connector proud by ~2 mm for power-first mating) | -| phase1-module | 120 × 80 mm | 4-layer | unchanged; gets the same bottom-edge connector pair so it can plug the backplane too | +| phase1-module | **100 × 80 mm** (was 120 × 80; that layout is kept on branch `phase1-120x80`) | 4-layer | shrunk to fit JLCPCB's ≤100 × 100 mm tier; gets the same bottom-edge connector pair so it can plug the backplane too | | phase3-backplane | **~330 × 100 mm** | 2-layer 2 oz | 8 × 30 mm slots + end margins + manager header zone; M6 lug bolts at entry; bus rails solder-reinforced | | phase3-manager | **100 × 80 mm** | 2-layer 1 oz | display module on standoffs above (or panel-mounted via ribbon); encoder/keys wired to panel | diff --git a/hardware/common/lcsc_parts.py b/hardware/common/lcsc_parts.py index c373710..7df8b0a 100644 --- a/hardware/common/lcsc_parts.py +++ b/hardware/common/lcsc_parts.py @@ -221,8 +221,9 @@ "through-hole, hand-solder; SOURCING lists 2EDG 5.08 plugs C3697 for " "P1 bench IO, but this footprint is a 5.0 mm Phoenix PT - pick the " "matching header"), - ({P1: ["F1"]}, "through-hole, hand-solder; mini blade holder, likely " - "C3207114 as on the manager, not confirmed for 10 A"), + ({P1: ["F1"]}, "through-hole, hand-solder; the land is KiCad's " + "direct-solder mini blade pattern, so a 10 A mini blade (ATM) fuse " + "solders straight in with no holder (C3207114 does not fit it)"), ({BP: ["C2"]}, "SOURCING's 470 uF part C106666 is THT D10; this board " "uses a 16x17.5 SMD footprint - choose an SMD part"), ({P1: ["J2", "J3", "J5", "J6"]}, "through-hole pin header: hand-solder " diff --git a/hardware/phase1-module/bom/phase1-module-bom.csv b/hardware/phase1-module/bom/phase1-module-bom.csv index ee82419..c593d63 100644 --- a/hardware/phase1-module/bom/phase1-module-bom.csv +++ b/hardware/phase1-module/bom/phase1-module-bom.csv @@ -27,7 +27,7 @@ Item,Qty,References,Value,Footprint,LCSC,MPN,Manufacturer,Unit USD,Ext USD,Note 26,1,D5,SMBJ33A,Diode_SMD:D_SMB,C224019,SMBJ33A,Littelfuse,0.122,0.122, 27,1,D6,1N4148W,Diode_SMD:D_SOD-323,C2128,1N4148WS,"Jiangsu Changjing Electronics Technology Co., Ltd.",0.0158,0.016,1N4148WS is the SOD-323 version (1N4148W is SOD-123) 28,1,D7,STATUS,LED_SMD:LED_0603_1608Metric,C2286,KT-0603R,Hubei KENTO Elec,0.0075,0.007,red 0603 LED (Basic) -29,1,F1,10A blade,Fuse:Fuse_Blade_Mini_directSolder,,,,,,"through-hole, hand-solder; mini blade holder, likely C3207114 as on the manager, not confirmed for 10 A" +29,1,F1,10A blade,Fuse:Fuse_Blade_Mini_directSolder,,,,,,"through-hole, hand-solder; the land is KiCad's direct-solder mini blade pattern, so a 10 A mini blade (ATM) fuse solders straight in with no holder (C3207114 does not fit it)" 30,1,J1,VBUS IN,"TerminalBlock_Phoenix:TerminalBlock_Phoenix_PT-1,5-2-5.0-H_1x02_P5.00mm_Horizontal",,,,,,"through-hole, hand-solder; SOURCING lists 2EDG 5.08 plugs C3697 for P1 bench IO, but this footprint is a 5.0 mm Phoenix PT - pick the matching header" 31,1,J2,SWD,Connector_PinHeader_2.54mm:PinHeader_1x05_P2.54mm_Vertical,,,,,,through-hole pin header: hand-solder (or pay for JLCPCB THT assembly) 32,1,J3,UART,Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical,,,,,,through-hole pin header: hand-solder (or pay for JLCPCB THT assembly) diff --git a/hardware/phase1-module/bom/phase1-module-cpl.csv b/hardware/phase1-module/bom/phase1-module-cpl.csv index 7e87642..47343d4 100644 --- a/hardware/phase1-module/bom/phase1-module-cpl.csv +++ b/hardware/phase1-module/bom/phase1-module-cpl.csv @@ -8,22 +8,22 @@ C18,63.4000mm,-62.0000mm,Top,0 C19,68.2000mm,-61.0000mm,Top,0 C20,50.0000mm,-36.9000mm,Top,270 C21,42.3000mm,-36.9000mm,Top,270 -C22,106.2000mm,-26.9000mm,Top,90 -C23,89.6000mm,-36.9000mm,Top,270 +C22,103.1600mm,-26.9000mm,Top,90 +C23,91.5600mm,-36.9000mm,Top,270 C24,60.2000mm,-64.0000mm,Top,0 C25,63.2000mm,-56.0000mm,Top,0 C26,63.4000mm,-58.5000mm,Top,0 C27,75.3000mm,-47.2000mm,Top,90 C28,67.7500mm,-52.2000mm,Top,90 C29,72.0000mm,-61.5000mm,Top,0 -C31,122.2000mm,-49.0000mm,Top,0 -C32,127.5000mm,-60.0000mm,Top,270 -C33,119.6000mm,-39.5000mm,Top,0 -C34,110.5000mm,-56.0000mm,Top,270 -C41,127.7000mm,-36.6000mm,Top,90 -C42,122.0000mm,-45.5000mm,Top,270 -C43,112.8000mm,-65.5000mm,Top,270 -C44,107.0000mm,-58.0000mm,Top,270 +C31,99.6000mm,-56.7000mm,Top,270 +C32,107.8000mm,-69.2000mm,Top,270 +C33,106.8000mm,-41.0000mm,Top,90 +C34,103.6000mm,-60.0000mm,Top,270 +C41,111.5000mm,-60.1000mm,Top,90 +C42,117.6000mm,-62.6000mm,Top,0 +C43,97.0000mm,-64.0000mm,Top,270 +C44,101.6000mm,-59.9000mm,Top,270 C50,28.2000mm,-52.2000mm,Top,0 C51,28.2000mm,-55.6000mm,Top,0 C52,37.0000mm,-52.5000mm,Top,270 @@ -38,8 +38,8 @@ C65,93.0000mm,-74.0000mm,Top,0 C66,76.8000mm,-79.0000mm,Top,0 C67,76.8000mm,-82.0000mm,Top,0 C68,83.0000mm,-90.5000mm,Top,0 -C69,113.0000mm,-76.5000mm,Top,0 -C70,113.0000mm,-83.5000mm,Top,0 +C69,109.0000mm,-76.3000mm,Top,0 +C70,109.0000mm,-83.7000mm,Top,0 C71,83.3000mm,-75.8000mm,Top,0 C72,96.7000mm,-75.8000mm,Top,0 C73,83.3000mm,-88.2000mm,Top,0 @@ -47,10 +47,10 @@ C74,96.7000mm,-88.2000mm,Top,0 C75,54.0000mm,-36.9000mm,Top,270 C76,58.0000mm,-36.9000mm,Top,270 C77,62.0000mm,-36.9000mm,Top,270 -C78,95.5000mm,-26.9000mm,Top,90 -C79,93.3000mm,-36.9000mm,Top,270 -C80,97.0000mm,-36.9000mm,Top,270 -C81,100.7000mm,-36.9000mm,Top,270 +C78,94.3400mm,-26.9000mm,Top,90 +C79,94.7800mm,-36.9000mm,Top,270 +C80,98.0000mm,-36.9000mm,Top,270 +C81,101.2200mm,-36.9000mm,Top,270 D1,68.0000mm,-78.5000mm,Top,0 D2,75.5000mm,-85.5000mm,Top,0 D3,54.4000mm,-66.2000mm,Top,0 @@ -62,20 +62,20 @@ F1,34.7500mm,-26.5000mm,Top,0 J1,25.0000mm,-35.5000mm,Top,270 J2,65.0800mm,-96.8000mm,Top,90 J3,48.5400mm,-96.8000mm,Top,90 -J4,136.5000mm,-44.5000mm,Top,90 -J5,136.5000mm,-78.8900mm,Top,0 +J4,116.6500mm,-51.8000mm,Top,90 +J5,116.5000mm,-81.5900mm,Top,0 J6,30.8700mm,-94.0000mm,Top,90 -L1,81.0000mm,-35.0000mm,Top,0 +L1,80.5700mm,-35.0000mm,Top,0 L2,33.0000mm,-61.0000mm,Top,0 Q1,67.5000mm,-30.0000mm,Top,0 Q2,67.5000mm,-43.0000mm,Top,180 -Q3,122.9000mm,-30.0000mm,Top,0 -Q4,131.7000mm,-30.0000mm,Top,180 +Q3,115.5000mm,-34.0000mm,Top,270 +Q4,115.5000mm,-42.5000mm,Top,90 Q5,51.5000mm,-58.0000mm,Top,0 Q6,55.5000mm,-58.0000mm,Top,0 -Q7,128.0000mm,-65.5000mm,Top,0 +Q7,95.5000mm,-68.0000mm,Top,0 Q8,34.0000mm,-90.2000mm,Top,0 -Q9,109.0000mm,-67.0000mm,Top,0 +Q9,99.5000mm,-68.0000mm,Top,0 R1,60.2000mm,-54.0000mm,Top,0 R2,60.2000mm,-60.0000mm,Top,0 R3,58.5000mm,-81.5000mm,Top,0 @@ -94,19 +94,19 @@ R23,51.0000mm,-65.0000mm,Top,0 R24,60.2000mm,-62.0000mm,Top,0 R25,63.4000mm,-60.0000mm,Top,0 R26,63.4000mm,-64.0000mm,Top,0 -R27,104.7000mm,-37.2000mm,Top,270 +R27,109.5200mm,-24.4000mm,Top,90 R28,77.6000mm,-47.2000mm,Top,90 R29,66.2000mm,-36.6000mm,Top,270 -R30,114.5000mm,-30.0000mm,Top,0 -R31,118.5000mm,-49.0000mm,Top,0 -R32,130.5000mm,-54.0000mm,Top,270 -R33,130.5000mm,-60.0000mm,Top,270 -R43,122.0000mm,-66.0000mm,Top,270 -R44,131.5000mm,-65.5000mm,Top,270 -R45,104.0000mm,-53.0000mm,Top,270 -R46,104.0000mm,-58.0000mm,Top,270 -R47,124.5000mm,-62.5000mm,Top,270 -R48,124.5000mm,-68.5000mm,Top,270 +R30,106.7000mm,-34.8000mm,Top,0 +R31,99.6000mm,-53.5000mm,Top,270 +R32,106.0000mm,-66.0000mm,Top,270 +R33,106.0000mm,-69.2000mm,Top,270 +R43,92.0000mm,-68.0000mm,Top,270 +R44,114.5000mm,-62.6000mm,Top,0 +R45,101.6000mm,-53.5000mm,Top,270 +R46,101.6000mm,-56.7000mm,Top,270 +R47,102.8000mm,-64.5000mm,Top,270 +R48,102.8000mm,-67.7000mm,Top,270 R50,34.0000mm,-65.5000mm,Top,0 R51,34.0000mm,-68.0000mm,Top,0 R52,103.5000mm,-81.5000mm,Top,0 @@ -124,12 +124,12 @@ RT2,81.0000mm,-48.7000mm,Top,0 U1,54.0000mm,-82.0000mm,Top,0 U2,64.0000mm,-82.0000mm,Top,0 U3,67.0000mm,-56.0000mm,Top,0 -U4,114.5000mm,-44.0000mm,Top,90 -U5,114.5000mm,-56.0000mm,Top,90 -U6,127.0000mm,-42.0000mm,Top,0 -U7,114.0000mm,-62.0000mm,Top,0 +U4,106.7000mm,-48.8000mm,Top,90 +U5,106.7000mm,-60.8000mm,Top,90 +U6,115.8000mm,-59.6000mm,Top,180 +U7,99.5000mm,-64.0000mm,Top,0 U8,33.0000mm,-54.9997mm,Top,0 U9,31.5000mm,-73.0000mm,Top,0 U10,90.0000mm,-82.0000mm,Top,0 -U11,118.0000mm,-80.0000mm,Top,0 +U11,109.0000mm,-80.0000mm,Top,0 Y1,81.5000mm,-80.5000mm,Top,0 diff --git a/hardware/phase1-module/phase1-module-fab.zip b/hardware/phase1-module/phase1-module-fab.zip index 3b5f1f6..f3fd49f 100644 Binary files a/hardware/phase1-module/phase1-module-fab.zip and b/hardware/phase1-module/phase1-module-fab.zip differ diff --git a/hardware/phase1-module/phase1-module.kicad_pcb b/hardware/phase1-module/phase1-module.kicad_pcb index 5fb90d4..c2670b0 100644 --- a/hardware/phase1-module/phase1-module.kicad_pcb +++ b/hardware/phase1-module/phase1-module.kicad_pcb @@ -179,197 +179,225 @@ (net 99 "unconnected-(U6-NC-Pad10)") (net 100 "unconnected-(U8-NC-Pad3)") - (footprint "Resistor_SMD:R_0603_1608Metric" (layer "F.Cu") - (tstamp 00dc8dfe-4994-4a77-941c-e81ffe626ddb) - (at 63.4 64) - (descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator") - (tags "resistor") + (footprint "labbench:PowerFET_SON5x6_GDS" (layer "F.Cu") + (tstamp 044c452f-1339-482d-aa24-43c8cfae0753) + (at 67.5 43 180) + (descr "TI SON 5x6 single NFET (Q5A/CSD18563Q5A land, SLPS444C 7.2); pads renumbered for Device:Q_NMOS_GDS (1=G 2=D 3=S)") + (tags "mosfet son 5x6 q5a nexfet") (attr smd) - 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112.495185 39.81686) + (xy 112.547989 39.771105) + (xy 112.615686 39.76096) ) ) ) diff --git a/hardware/phase1-module/tools/README.md b/hardware/phase1-module/tools/README.md index 01949e8..ad96172 100644 --- a/hardware/phase1-module/tools/README.md +++ b/hardware/phase1-module/tools/README.md @@ -36,7 +36,7 @@ eyeball; it has caught >15 real hardware bugs before any board was ordered. | `check_footprints.py` | Every component has a resolvable footprint; every netted pin has a matching pad | | `merge_vendor.py` | Merges only datasheet-VETTED vendor symbols into `lib/labbench.kicad_sym` | | `build_fplib.py` | Same for footprints -> `lib/labbench.pretty/`; also generates `PowerFET_SON5x6_GDS` from the TI Q5A land pattern (pads renumbered 1=G/2=D/3=S for the generic symbol) | -| `gen_board.py` | Netlist -> placed 120x80 4-layer board: PLACEMENT table, split In1 ground plane (PGND/AGND star at NT1 + AGND pocket under the LTC7004), In2 5V0/3V3 zones, 10 F.Cu power pours, pour/courtyard/edge checks | +| `gen_board.py` | Netlist -> placed 100x80 4-layer board: PLACEMENT table, split In1 ground plane (PGND/AGND star at NT1; the LTC7004 now sits on the AGND side, so no pocket), In2 5V0/3V3 zones, 10 F.Cu power pours, pour/courtyard (real polygons)/edge checks. The 120x80 layout is on branch `phase1-120x80` | | `route_board.py` | Deterministic copper: In2 heat patches, thermal/stitching/pad vias (seam-aware), critical routes (Kelvin pair, LM5145 gate fan-out, BST/ILIM/VIN, NT1 tie) | | `autoroute.py` | Superseded grid A* signal router (kept for reference) | | `fanout.py` | Routing pass 1b: placement nudges (NUDGES, empty now), solid-joined pads (SOLID_PADS), hand escapes for U3's boxed-in pins, then a via drop for every plane-net pad (PGND/AGND to In1, 3V3/5V0 to In2) and an escape for signal pads inside a foreign F.Cu pour | @@ -71,7 +71,8 @@ python3 export_dsn.py wip/p1.dsn xvfb-run -a java -Xss64m -jar freerouting-1.9.0.jar \ -de wip/p1.dsn -do wip/p1.ses -mp 20 -mt 1 # 2.x CLI never finishes python3 import_ses.py wip/p1.ses # 145 -> ~18 unconnected -python3 finish_routes.py --base=/tmp/base.kicad_pcb # -> 0 +python3 finish_routes.py ../phase1-module.kicad_pcb --base=/tmp/base.kicad_pcb # -> 0 (board path first) +python3 fb_reroute.py # FB run >= 5.5 mm from SW copper python3 ../../common/fix_fpids.py ../phase1-module.kicad_pcb python3 ../../common/finish_board.py ../phase1-module.kicad_pcb --silk --planes python3 run_drc.py # 0 unconnected, 0 errors diff --git a/hardware/phase1-module/tools/fanout.py b/hardware/phase1-module/tools/fanout.py index b3cf117..720e9b2 100644 --- a/hardware/phase1-module/tools/fanout.py +++ b/hardware/phase1-module/tools/fanout.py @@ -58,8 +58,9 @@ # SWDIO running under it on B.Cu and NRST beside it, so the AGND pour # gets one spoke in and DRC flags a starved thermal. The pin is also on # the In1 AGND plane; a solid B.Cu join on a 1 mm header pin still -# hand-solders fine. -SOLID_PADS = {("J2", "5")} +# hand-solders fine. J4.2 (output terminal PGND) carries the full load +# return straight into In1/B.Cu PGND, so spokes would only add resistance. +SOLID_PADS = {("J2", "5"), ("J4", "2")} # Hand-placed signal escapes: (ref, pad, via x, y board-relative mm), a # straight F.Cu stub from the pad centre to a through via. U3's left pins diff --git a/hardware/phase1-module/tools/fb_reroute.py b/hardware/phase1-module/tools/fb_reroute.py new file mode 100644 index 0000000..6348e8d --- /dev/null +++ b/hardware/phase1-module/tools/fb_reroute.py @@ -0,0 +1,81 @@ +"""Re-route Phase-1's VOUT_INT FB sense run >= 5.5 mm from every SW copper item. + + python3 fb_reroute.py # after finish_routes.py, before silk/planes + +Freerouting has no spacing rule between two particular nets, and on the +100 x 80 board it ran the FB run 0.25 mm past the SW island. This rips the +run between the R1/R25 island and the output side (VOUT_INT signal tracks +between x 43.2 and 65 mm, plus two of its vias), puts a keep-out of SW +copper grown by 5.5 mm on every routing layer, and lets finish_routes' +A* router join the two islands again. Check the result with run_drc.py. +The rip list is specific to the committed routing; re-check it if the +board is re-routed. +""" +import sys +sys.path.insert(0, ".") +import pcbnew +from shapely.geometry import LineString, Point, Polygon +from shapely.ops import unary_union +import finish_routes as fr + +KEEP = 5.5 +BOARD = "../phase1-module.kicad_pcb" +mm = pcbnew.ToMM +board = pcbnew.LoadBoard(BOARD) +pcbnew.ZONE_FILLER(board).Fill(board.Zones()) +G = [] +# 1. rip the FB run between the output pour and the R1/R25 island +for t in list(board.GetTracks()): + if t.GetNetname() != "VOUT_INT": + continue + if isinstance(t, pcbnew.PCB_VIA): + x, y = mm(t.GetPosition().x) - 20, mm(t.GetPosition().y) - 20 + if (round(x, 2), round(y, 2)) in {(48.42, 42.13), (46.42, 41.08)}: + board.Remove(t); G.append(t) + continue + if mm(t.GetWidth()) >= 1: + continue + xs = [mm(p.x) - 20 for p in (t.GetStart(), t.GetEnd())] + if min(xs) >= 43.2 and max(xs) <= 65.0: + board.Remove(t); G.append(t) +print("ripped", len(G)) +# 2. SW keep-out geometry (page mm), every copper layer +sw = [] +for t in board.GetTracks(): + if t.GetNetname() == "SW": + if isinstance(t, pcbnew.PCB_VIA): + sw.append(Point(mm(t.GetPosition().x), mm(t.GetPosition().y)).buffer(mm(t.GetWidth()) / 2)) + else: + sw.append(LineString([(mm(t.GetStart().x), mm(t.GetStart().y)), + (mm(t.GetEnd().x), mm(t.GetEnd().y))]).buffer(mm(t.GetWidth()) / 2)) +for fp in board.GetFootprints(): + for p in fp.Pads(): + if p.GetNetname() == "SW": + sw += fr.sps_polys(p.GetEffectivePolygon()) +for z in board.Zones(): + if z.GetNetname() == "SW": + sw += fr.sps_polys(z.GetFilledPolysList(z.GetLayer())) +keep = unary_union(sw).buffer(KEEP - 0.2) # route() adds clearance + half width + +class Cu(fr.Copper): + def __init__(self, b, base_keys=None): + super().__init__(b, base_keys) + for L in fr.ROUTE_LAYERS: + self.items.append(("", L, keep, "pad", None)) + +cu = Cu(board) +isl = cu.islands("VOUT_INT") +isl.sort(key=len, reverse=True) +print("islands", [len(i) for i in isl]) +assert len(isl) == 2 +bb = board.GetBoardEdgesBoundingBox() +bbx = (mm(bb.GetLeft()), mm(bb.GetTop()), mm(bb.GetRight()), mm(bb.GetBottom())) +fr.WINDOW = 40 +res, _ = fr.route(cu, "VOUT_INT", isl[1], isl[0], bbx) +assert res, "no path" +nets = {ni.GetNetname(): ni.GetNetCode() for ni in board.GetNetsByName().values()} +fr.commit(board, nets, "VOUT_INT", res) +pcbnew.ZONE_FILLER(board).Fill(board.Zones()) +fr.tidy(board, set()) +board.Save(BOARD) +print("routed:", res) diff --git a/hardware/phase1-module/tools/gen_board.py b/hardware/phase1-module/tools/gen_board.py index 7dd942d..8c8702b 100644 --- a/hardware/phase1-module/tools/gen_board.py +++ b/hardware/phase1-module/tools/gen_board.py @@ -23,7 +23,7 @@ FPDIRS = [os.path.join(HERE, "..", "lib"), "/usr/share/kicad/footprints"] ORG = (20.0, 20.0) # page position of board origin -W, H = 120.0, 80.0 # board size +W, H = 100.0, 80.0 # board size SEAM = 31.0 # y of PGND/AGND plane split (x > AUXW) AUXW = 30.0 # aux-rail column width (PGND region below seam) @@ -66,7 +66,7 @@ def parse_netlist(path): # ---- half bridge: Q1 tab in VBUS_F band, Q2 (rot180) tab right = SW "Q1": (47.5, 10.0, 0), # tab 44.05..49.65 VBUS_F; sources x50.58 SW "Q2": (47.5, 23.0, 180), # tab 45.35..50.3 SW; leads x44.42 PGND - "L1": (61.0, 15.0, 0), # pad1 SW (56.7), pad2 VOUT_INT (65.3) + "L1": (60.57, 15.0, 0), # 17 mm superset land: pad1 SW (54.17), pad2 VOUT_INT (66.98) "RT1": (44.0, 33.0, 0), # FET NTC below Q2, on AGND side of seam "RT2": (61.0, 28.7, 0), # inductor NTC below L1 # SW island taps (pad into pour at y<=26.5, other pad below) @@ -75,41 +75,41 @@ def parse_netlist(path): "R17": (52.0, 27.2, 270), # snub: pad1 up=SW, pad2 dn=SNUB "C17": (50.9, 30.4, 270), # pad1 up=SNUB, pad2 dn=PGND (in bar) # ---- output bank straddle - "C22": (86.2, 6.9, 90), # top-strip straddle like C78 # 220u poly - "C78": (75.5, 6.9, 90), # pad1 dn in VOUT_INT, pad2 up in PGND_TOP strip - "C23": (69.6, 16.9, 270), # 22u/25V bank - "C79": (73.3, 16.9, 270), - "C80": (77.0, 16.9, 270), - "C81": (80.7, 16.9, 270), - "R27": (84.7, 17.2, 270), # 2512 preload straddle + "C22": (83.16, 6.9, 90), # top-strip straddle like C78 # 220u poly + "C78": (74.34, 6.9, 90), # pad1 dn in VOUT_INT, pad2 up in PGND_TOP strip + "C23": (71.56, 16.9, 270), # 22u/25V bank + "C79": (74.78, 16.9, 270), + "C80": (78.0, 16.9, 270), + "C81": (81.22, 16.9, 270), + "R27": (89.52, 4.4, 90), # 2512 preload: pad1 dn VOUT_INT, pad2 up PGND_TOP # ---- Kelvin shunt + sense amps below it - "R30": (94.5, 10.0, 0), # pad1 VOUT_INT (91.54), pad2 VOUT_SW (97.46) - "U4": (94.5, 24.0, 90), # INA240: pin8 (92.59,21.53) faces shunt - "R31": (98.5, 29.0, 0), # INA240_OUT -> I_MEAS - "C31": (102.2, 29.0, 0), # I_MEAS filter (AGND pocket) - "C33": (99.6, 19.5, 0), # U4 5V0 - "U5": (94.5, 36.0, 90), # INA228 - "C34": (90.5, 36.0, 270), # U5 3V3 - "NT1": (97.5, 31.2, 0), # star tie on the seam + "R30": (86.7, 14.8, 0), # pad1 VOUT_INT (83.74), pad2 VOUT_SW (89.66) + "U4": (86.7, 28.8, 90), # INA240: pin8 (84.79,26.33) faces shunt + "R31": (79.6, 33.5, 270), # INA240_OUT -> I_MEAS + "C31": (79.6, 36.7, 270), # I_MEAS filter (AGND) + "C33": (86.8, 21.0, 90), # U4 5V0, inside the Kelvin pair + "U5": (86.7, 40.8, 90), # INA228 + "C34": (83.6, 40.0, 270), # U5 3V3 + "NT1": (91.2, 31.0, 0), # star tie on the seam # ---- disconnect pair + LTC7004 + VOUT - "Q3": (102.9, 10.0, 0), # tab VOUT_SW; sources 105.98 DISC_SRC - "Q4": (111.7, 10.0, 180), # tab VOUT 109.55..115.16; sources 108.62 - "U6": (107.0, 22.0, 0), # LTC7004 under the pair (AGND pocket) - "C41": (107.7, 16.6, 90), # BST: pad1 dn=LTC_BST, pad2 up in DISC pour - "C42": (102.0, 25.5, 270), # 5V0 1u (pad2 dn AGND pocket) - "C43": (92.8, 45.5, 270), # moved to U7 (audit DC-001) # 5V0 100n - "J4": (116.5, 27.0, 90), # pad1 VOUT (116.5,22), pad2 PGND (116.5,27) + "Q3": (95.5, 14.0, 270), # tab VOUT_SW (up); sources y17.08 DISC_SRC; gate (97.41,17.08) + "Q4": (95.5, 22.5, 90), # sources y19.42 DISC_SRC; tab VOUT (down); gate (93.59,19.42) + "U6": (95.8, 39.6, 180), # LTC7004 under J4 (AGND side); gate/source/BST pins face left + "C41": (91.5, 40.1, 90), # BST: pad1 dn LTC_BST (U6.9), pad2 up DISC_SRC (U6.8) + "C42": (97.6, 42.6, 0), # 5V0 1u below U6.1/2 + "C43": (77.0, 44.0, 270), # U7 5V0 100n + "J4": (96.65, 34.3, 90), # pad1 VOUT (96.65,34.3), pad2 PGND (96.65,29.3) # ---- OVP + disconnect logic (y 33..50) - "R45": (84.0, 33.0, 270), # VOUT_INT (B.Cu tap) -> OVP_DIV - "R46": (84.0, 38.0, 270), - "C44": (87.0, 38.0, 270), - "U7": (94.0, 42.0, 0), # TLV7011 (5V0 pocket at x92..103) - "R47": (104.5, 42.5, 270), # 3V3 -> REF_2V5 - "R48": (104.5, 48.5, 270), - "Q9": (89.0, 47.0, 0), # OVP_TRIP pulls DISC_INP - "Q7": (108.0, 45.5, 0), # EN_KILL pulls DISC_INP - "R43": (102.0, 46.0, 270), # OUT_REQ -> DISC_INP - "R44": (111.5, 45.5, 270), # DISC_INP -> AGND + "R45": (81.6, 33.5, 270), # VOUT_INT -> OVP_DIV + "R46": (81.6, 36.7, 270), + "C44": (81.6, 39.9, 270), + "U7": (79.5, 44.0, 0), # TLV7011 SC-70-5 (5V0 In2 island) + "R47": (82.8, 44.5, 270), # 3V3 -> REF_2V5 + "R48": (82.8, 47.7, 270), + "Q9": (79.5, 48.0, 0), # OVP_TRIP pulls DISC_INP + "Q7": (75.5, 48.0, 0), # EN_KILL pulls DISC_INP + "R43": (72.0, 48.0, 270), # OUT_REQ -> DISC_INP + "R44": (94.5, 42.6, 0), # DISC_INP -> AGND, below U6.4 # ---- controller + comp/FB + EN cluster "U3": (47.0, 36.0, 0), # LM5145: right col = LO/VCC/EP/BST/HO/SW "R29": (46.2, 16.6, 270), # VBUS_F (pad1 in band) -> PS_VIN corridor @@ -193,43 +193,57 @@ def parse_netlist(path): "J3": (26.0, 76.8, 90), # UART, runs +x to 31.1 "J2": (40.0, 76.8, 90), # SWD, runs +x to 50.2 # ---- CAN + backplane + VBUS telemetry divider - "U11": (98.0, 60.0, 0), # TCAN1042 - "C69": (93.0, 56.5, 0), # 5V0 (pocket) - "C70": (93.0, 63.5, 0), # 3V3 - "J5": (116.5, 50.0, 0), # 1x08 runs +y to 67.8 + "U11": (89.0, 60.0, 0), # TCAN1042 + "C69": (89.0, 56.3, 0), # 5V0 + "C70": (89.0, 63.7, 0), # 3V3 + "J5": (96.5, 52.7, 0), # 1x08 runs +y to 70.5 "R60": (63.5, 73.0, 0), # VBUS_F -> VBUS_SNS, divider by U10.14 (ADC) "R61": (65.0, 74.75, 0), "C62": (66.5, 73.0, 0), - # V_MEAS divider (0.1%) senses VOUT at the output connector corner - "R32": (110.5, 34.0, 270), - "R33": (110.5, 40.0, 270), - "C32": (107.5, 40.0, 270), + # V_MEAS divider (0.1%) senses VOUT by the output connector + "R32": (86.0, 46.0, 270), + "R33": (86.0, 49.2, 270), + "C32": (87.8, 49.2, 270), } -MOUNT_HOLES = [(4.0, 4.0), (W - 4.0, 36.0), (4.0, H - 4.0), (W - 4.0, H - 4.0)] -FIDUCIALS = [(10.0, 2.2), (110.0, 77.8), (2.5, 45.0)] # audit FD-001 +MOUNT_HOLES = [(4.0, 4.0), (W - 4.0, 47.0), (4.0, H - 4.0), (W - 4.0, H - 4.0)] +FIDUCIALS = [(10.0, 2.2), (88.0, 77.8), (2.5, 45.0)] # audit FD-001 # ------------------------------------------------------------------ zones -- # (net, layer, priority, [(x,y)...], pad_connection) -# The AGND "pocket" carves an island out of the PGND regions (higher priority -# wins) so the LTC7004 cluster -- AGND-referenced but living in the power -# strip -- gets correct plane reference without through-via shorts. -POCKET = [(100.0, 16.5), (112.5, 16.5), (112.5, SEAM + 0.2), (100.0, SEAM + 0.2)] +# The LTC7004 cluster sits below the seam on the AGND side, so the plain +# PGND/AGND split serves every part (the 120 x 80 layout needed an AGND +# pocket carved into the power strip; see branch phase1-120x80). PWR_POURS = { # name -> F.Cu polygon (also used by pour-connection checks) "VBUS_F": [(12.0, 5.0), (49.6, 5.0), (49.6, 16.0), (12.0, 16.0)], "PGND_IN": [(10.0, 17.3), (44.9, 17.3), (44.9, 30.0), (10.0, 30.0)], - "PGND_TOP": [(66.0, 0.8), (91.0, 0.8), (91.0, 3.9), (66.0, 3.9)], + "PGND_TOP": [(66.0, 0.8), (91.4, 0.8), (91.4, 3.9), (66.0, 3.9)], "PGND_BAR": [(38.0, 30.0), (54.4, 30.0), (54.4, 31.7), (38.0, 31.7)], "SW": [(50.5, 8.6), (56.9, 8.6), (56.9, 19.0), (58.4, 19.0), (58.4, 26.5), (47.0, 26.5), (47.0, 19.0), (50.5, 19.0)], - "VOUT_INT": [(64.3, 5.0), (91.7, 5.0), (91.7, 16.0), (64.3, 16.0)], - "PGND_OUT": [(66.0, 17.3), (91.0, 17.3), (91.0, 30.0), (66.0, 30.0)], - "VOUT_SW": [(97.4, 5.0), (104.7, 5.0), (104.7, 16.0), (97.4, 16.0)], - "DISC_SRC": [(105.5, 5.0), (109.9, 5.0), (109.9, 16.0), (105.5, 16.0)], - "VOUT": [(110.5, 5.0), (119.5, 5.0), (119.5, 29.0), (108.0, 29.0), - (108.0, 21.0), (110.5, 21.0)], + # stepped: full width under the top-strip caps and R27, then stops at + # R30 pad1 so the Kelvin VOUT_INT lead leaves from the bare pad edge + "VOUT_INT": [(64.3, 5.0), (91.4, 5.0), (91.4, 9.3), (83.8, 9.3), + (83.8, 16.0), (64.3, 16.0)], + "PGND_OUT": [(70.0, 17.3), (83.0, 17.3), (83.0, 30.0), (70.0, 30.0)], + # right column, top to bottom: R30 pad2 + Q3 tab, the source-to-source + # band (notched at the two gate pads: Q3 top right, Q4 bottom left), + # then Q4's tab wrapping J4.2 (PGND) down to J4.1, clear of NT1. + "VOUT_SW": [(89.6, 10.0), (99.5, 10.0), (99.5, 16.4), (89.6, 16.4)], + "DISC_SRC": [(92.9, 16.65), (96.75, 16.65), (96.75, 18.25), (98.1, 18.25), + (98.1, 20.0), (94.25, 20.0), (94.25, 18.25), (92.9, 18.25)], + "VOUT": [(91.2, 20.2), (99.5, 20.2), (99.5, 37.0), (93.0, 37.0), + (93.0, 27.0), (91.2, 27.0)], } +# In2 5V0 islands outside the aux column (priority 1 over the 3V3 plane): +# U4/C33 inside the Kelvin pair, U6/C42, U7/C43, U11/C69. +IN2_5V0 = [ + [(85.0, 17.2), (88.6, 17.2), (88.6, 30.6), (85.0, 30.6)], + [(90.4, 37.6), (99.5, 37.6), (99.5, 44.2), (90.4, 44.2)], + [(75.6, 42.4), (81.2, 42.4), (81.2, 45.6), (75.6, 45.6)], + [(84.5, 53.5), (93.5, 53.5), (93.5, 68.0), (84.5, 68.0)], +] def zone_polys(): @@ -242,17 +256,15 @@ def zone_polys(): # inner ground planes (split at SEAM/AUXW, joined only through NT1) ("PGND", IN1, 0, pgnd_l, "thermal"), ("AGND", IN1, 0, agnd_r, "thermal"), - ("AGND", IN1, 1, POCKET, "thermal"), # In2: logic power distribution ("5V0", IN2, 0, [(0.5, 0.5), (AUXW, 0.5), (AUXW, H - 0.5), (0.5, H - 0.5)], "thermal"), ("5V0", IN2, 0, [(AUXW, 56.0), (56.0, 56.0), (56.0, H - 0.5), (AUXW, H - 0.5)], "thermal"), - ("5V0", IN2, 1, [(92.0, 18.0), (103.0, 18.0), (103.0, 68.0), (92.0, 68.0)], "thermal"), + *[("5V0", IN2, 1, poly, "thermal") for poly in IN2_5V0], ("3V3", IN2, 0, [(AUXW, SEAM), (W - 0.5, SEAM), (W - 0.5, H - 0.5), (56.0, H - 0.5), (56.0, 56.0), (AUXW, 56.0)], "thermal"), # B.Cu ground fills (mirror the In1 split, tracks push through) ("PGND", B, 0, pgnd_l, "thermal"), ("AGND", B, 0, agnd_r, "thermal"), - ("AGND", B, 1, POCKET, "thermal"), ] for name, poly in PWR_POURS.items(): net = {"PGND_IN": "PGND", "PGND_BAR": "PGND", "PGND_OUT": "PGND", "PGND_TOP": "PGND"}.get(name, name) @@ -281,11 +293,10 @@ def zone_polys(): ("C79", "1", "VOUT_INT"), ("C79", "2", "PGND_OUT"), ("C80", "1", "VOUT_INT"), ("C80", "2", "PGND_OUT"), ("C81", "1", "VOUT_INT"), ("C81", "2", "PGND_OUT"), - ("R27", "1", "VOUT_INT"), ("R27", "2", "PGND_OUT"), + ("R27", "1", "VOUT_INT"), ("R27", "2", "PGND_TOP"), ("R30", "1", "VOUT_INT"), ("R30", "2", "VOUT_SW"), ("Q3", "2", "VOUT_SW"), ("Q3", "3", "DISC_SRC"), ("Q4", "3", "DISC_SRC"), ("Q4", "2", "VOUT"), - ("C41", "2", "DISC_SRC"), ("J4", "1", "VOUT"), ] @@ -303,35 +314,36 @@ def point_in_poly(x, y, poly): def check_courtyards(board): - """Fast bbox overlap report on F.CrtYd; placement iteration aid.""" - boxes = [] + """Courtyard overlap / board-edge report on the real F.CrtYd polygons + (bounding boxes flag false overlaps: L1's box, round mounting holes).""" + from shapely.geometry import Polygon, box + crt = [] for fp in board.GetFootprints(): - bb = None - for g in fp.GraphicalItems(): - if g.GetLayer() == pcbnew.F_CrtYd: - b = g.GetBoundingBox() - if bb is None: - bb = [b.GetLeft(), b.GetTop(), b.GetRight(), b.GetBottom()] - else: - bb = [min(bb[0], b.GetLeft()), min(bb[1], b.GetTop()), - max(bb[2], b.GetRight()), max(bb[3], b.GetBottom())] - if bb: - boxes.append((fp.GetReference(), bb)) + fp.BuildCourtyardCaches() + ps = fp.GetCourtyard(pcbnew.F_CrtYd) + polys = [] + for k in range(ps.OutlineCount()): + ol = ps.Outline(k) + pts = [(pcbnew.ToMM(ol.CPoint(i).x), pcbnew.ToMM(ol.CPoint(i).y)) + for i in range(ol.PointCount())] + if len(pts) >= 3: + polys.append(Polygon(pts).buffer(0)) + if polys: + crt.append((fp.GetReference(), polys)) fails = 0 - for i in range(len(boxes)): - for j in range(i + 1, len(boxes)): - (r1, a), (r2, b) = boxes[i], boxes[j] - ox = min(a[2], b[2]) - max(a[0], b[0]) - oy = min(a[3], b[3]) - max(a[1], b[1]) - if ox > 0 and oy > 0: - print(f"CRTYD {r1}<->{r2} overlap {pcbnew.ToMM(ox):.2f}x{pcbnew.ToMM(oy):.2f}mm") + for i in range(len(crt)): + for j in range(i + 1, len(crt)): + (r1, a), (r2, b) = crt[i], crt[j] + area = sum(p.intersection(q).area for p in a for q in b) + if area > 1e-4: + print(f"CRTYD {r1}<->{r2} overlap {area:.3f} mm^2") fails += 1 # board edge check (terminal blocks J1/J4 legitimately overhang for wire entry) - for ref, bb in boxes: + edge = box(ORG[0], ORG[1], ORG[0] + W, ORG[1] + H) + for ref, polys in crt: if ref in ("J1", "J4"): continue - if (pcbnew.ToMM(bb[0]) < ORG[0] or pcbnew.ToMM(bb[1]) < ORG[1] - or pcbnew.ToMM(bb[2]) > ORG[0] + W or pcbnew.ToMM(bb[3]) > ORG[1] + H): + if any(not edge.contains(p) for p in polys): print(f"CRTYD {ref} extends past board edge") fails += 1 return fails diff --git a/hardware/phase1-module/tools/route_board.py b/hardware/phase1-module/tools/route_board.py index 075a19e..3999317 100644 --- a/hardware/phase1-module/tools/route_board.py +++ b/hardware/phase1-module/tools/route_board.py @@ -5,7 +5,7 @@ Adds: - In2.Cu same-net patches under the F.Cu power pours (heat + current) - thermal via arrays on FET tabs / L1 pads (F pour -> In2 patch) - - EP vias (U3, U6), NT1 star-tie vias, J1/J4 PGND via clusters + - EP vias (U3, U6), NT1 star-tie vias, J1 PGND via cluster - seam-aware power-pad vias (PGND/AGND -> In1+B fills, 5V0/3V3 -> In2) - critical tracks: Kelvin sense pair, HO/LO/SW gate routes, BST, ILIM, VIN corridor, snubber, VBUS input link, aux VBUS_F trunk, 3V3 trunk @@ -17,7 +17,7 @@ import pcbnew from pcbnew import FromMM, VECTOR2I -from gen_board import ORG, W, H, SEAM, AUXW, POCKET, PWR_POURS, P, point_in_poly +from gen_board import ORG, W, H, SEAM, AUXW, IN2_5V0, PWR_POURS, P, point_in_poly HERE = os.path.dirname(os.path.abspath(__file__)) BOARD = os.path.join(HERE, "..", "phase1-module.kicad_pcb") @@ -28,10 +28,11 @@ IN2_PATCHES = [ ("VBUS_F", [(13.0, 5.5), (49.0, 5.5), (49.0, 15.5), (13.0, 15.5)]), ("SW", [(47.5, 9.0), (56.5, 9.0), (56.5, 26.0), (47.5, 26.0)]), - ("VOUT_INT", [(65.0, 5.5), (91.0, 5.5), (91.0, 15.5), (65.0, 15.5)]), - ("VOUT_SW", [(97.8, 5.5), (104.3, 5.5), (104.3, 15.5), (97.8, 15.5)]), - ("DISC_SRC", [(105.9, 5.5), (109.5, 5.5), (109.5, 15.5), (105.9, 15.5)]), - ("VOUT", [(110.9, 5.5), (119.0, 5.5), (119.0, 28.5), (110.9, 28.5)]), + ("VOUT_INT", [(65.0, 5.5), (90.9, 5.5), (90.9, 8.8), (83.3, 8.8), + (83.3, 15.5), (65.0, 15.5)]), + ("VOUT_SW", [(90.0, 10.5), (99.0, 10.5), (99.0, 15.9), (90.0, 15.9)]), + ("VOUT", [(91.6, 20.7), (99.0, 20.7), (99.0, 36.5), (93.4, 36.5), + (93.4, 26.6), (91.6, 26.6)]), ] # ---- explicit vias: (net, x, y) @@ -41,25 +42,27 @@ *[("SW", x, y) for x in (47.9, 49.5) for y in (21.8, 24.2)], *[("SW", 55.9, y) for y in (12.0, 18.0, 24.5)], *[("VOUT_INT", 65.8, y) for y in (11.0, 14.5)], # L1.2 / pour tie - *[("VOUT_SW", x, y) for x in (100.5, 102.0, 103.5) for y in (9.0, 11.0)], - *[("DISC_SRC", x, y) for x in (106.6, 108.6) for y in (13.5,)], - *[("VOUT", x, y) for x in (111.2, 112.7, 114.2) for y in (9.0, 11.0)], - # exposed pads (AGND): U3 at (47,36), U6 at (107,22) [AGND pocket] + *[("VOUT_SW", x, y) for x in (94.2, 95.5, 96.8) for y in (12.4, 14.9)], # Q3 tab + *[("VOUT_SW", 91.3, y) for y in (11.0, 13.5)], # R30.2 -> Q3 + ("DISC_SRC", 95.5, 18.25), # B.Cu landing for U6.8 + *[("VOUT", x, y) for x in (94.2, 95.5, 96.8) for y in (21.6, 24.1)], # Q4 tab + *[("VOUT", x, y) for x in (94.0, 98.9) for y in (28.5, 31.5)], # round J4.2 + # exposed pads (AGND): U3 at (47,36), U6 at (95.8,39.6) *[("AGND", x, y) for x in (46.55, 47.45) for y in (35.55, 36.45)], - *[("AGND", x, 22.0) for x in (106.6, 107.4)], + *[("AGND", x, 39.6) for x in (95.4, 96.2)], # NT1 star tie - ("AGND", 96.6, 32.6), ("PGND", 98.6, 29.8), - # connector grounds + ("AGND", 90.3, 32.4), ("PGND", 92.1, 29.6), + # connector grounds (J4.2 is a through pad in the In1/B.Cu PGND fills) ("PGND", 3.6, 16.4), ("PGND", 6.4, 16.4), # J1.2 - ("PGND", 115.2, 20.6), ("PGND", 117.8, 20.6), # J4.2 # output PGND band + top strip + bar ties into In1 - *[("PGND", x, 2.4) for x in (70.0, 78.0, 86.0)], # PGND_TOP strip + *[("PGND", x, 2.4) for x in (69.0, 78.7, 87.0)], # PGND_TOP strip *[("PGND", x, 30.9) for x in (40.5, 44.0, 47.5, 54.0)], # bar # VBUS_F pour -> In2 patch stitching (also carries aux feed) *[("VBUS_F", x, y) for x in (16.0, 24.0, 32.0, 40.0) for y in (6.5, 13.0)], ("VBUS_F", 13.0, 14.5), # aux trunk tap ("VBUS_F", 9.0, 28.6), # aux trunk drop - *[("VOUT_INT", x, y) for x in (70.0, 78.0, 86.0) for y in (6.5, 13.0)], + *[("VOUT_INT", x, 6.5) for x in (71.0, 78.7, 86.6)], + *[("VOUT_INT", x, 13.0) for x in (71.0, 78.7)], ] # ---- critical tracks: (net, layer, width_mm, [(x,y)...]) @@ -67,22 +70,21 @@ TRACKS = [ # input link J1.1 -> F1.1 (VBUS) ("VBUS", F, 2.5, [(5.0, 13.0), (5.0, 8.2), (6.7, 6.5), (10.8, 6.5)]), - # J1.2 / J4.2 pad stubs to their via pairs + # J1.2 pad stubs to its via pair ("PGND", F, 2.0, [(5.0, 18.0), (3.6, 19.6)]), ("PGND", F, 2.0, [(5.0, 18.0), (6.4, 19.6)]), - ("PGND", F, 2.0, [(116.5, 22.0), (115.2, 20.6)]), - ("PGND", F, 2.0, [(116.5, 22.0), (117.8, 20.6)]), - # Kelvin sense pair (0.3 mm): R30 inner edges -> U4 -> U5 - ("VOUT_INT", F, 0.3, [(92.2, 10.0), (92.59, 12.0), (92.59, 21.53)]), - ("VOUT_INT", F, 0.3, [(92.59, 21.53), (91.6, 22.5), (91.6, 31.0)]), - ("VOUT_INT", F, 0.24, [(91.6, 31.0), (93.5, 31.9), (93.5, 33.8)]), - ("VOUT_SW", F, 0.3, [(96.8, 10.0), (96.6, 12.0), (96.6, 19.0), - (97.6, 20.0), (97.6, 26.8), (96.8, 27.9), - (92.59, 27.9), (92.59, 26.47)]), - ("VOUT_SW", F, 0.24, [(94.0, 27.9), (94.0, 33.8)]), + # Kelvin sense pair (0.3 mm): R30 inner edges -> U4 -> U5. Same + # geometry as the 120 x 80 board, moved by (-7.8, +4.8) with its parts. + ("VOUT_INT", F, 0.3, [(84.4, 14.8), (84.79, 16.8), (84.79, 26.33)]), + ("VOUT_INT", F, 0.3, [(84.79, 26.33), (83.8, 27.3), (83.8, 35.8)]), + ("VOUT_INT", F, 0.24, [(83.8, 35.8), (85.7, 36.7), (85.7, 38.6)]), + ("VOUT_SW", F, 0.3, [(89.0, 14.8), (88.8, 16.8), (88.8, 23.8), + (89.8, 24.8), (89.8, 31.6), (89.0, 32.7), + (84.79, 32.7), (84.79, 31.27)]), + ("VOUT_SW", F, 0.24, [(86.2, 32.7), (86.2, 38.6)]), # NT1 stubs to its vias - ("AGND", F, 0.5, [(97.0, 31.2), (96.6, 32.6)]), - ("PGND", F, 0.5, [(98.0, 31.2), (98.6, 29.8)]), + ("AGND", F, 0.5, [(90.7, 31.0), (90.3, 32.4)]), + ("PGND", F, 0.5, [(91.7, 31.0), (92.1, 29.6)]), # LM5145 right-column fan-out: short stubs to a staggered via fan, # then B.Cu runs with non-crossing verticals. ("SW", F, 0.24, [(48.65, 34.25), (49.6, 32.35)]), @@ -133,16 +135,14 @@ # ---- stitching grids (collision-filtered at runtime) STITCH = ( [("PGND", x, y) for x in range(14, 45, 6) for y in (19.5, 24.0, 28.5)] + - [("PGND", x, y) for x in range(68, 91, 6) for y in (19.5, 24.0, 28.5)] + + [("PGND", x, y) for x in range(72, 83, 5) for y in (19.5, 24.0, 28.5)] + [("PGND", x, y) for x in (3, 9, 15, 21, 27) for y in (44, 52, 60, 68, 76)] + [("PGND", 3, y) for y in (4, 10, 16, 22, 28, 36)] + - [("AGND", x, y) for x in range(33, 118, 11) for y in (33.5, 48.5, 57.5, 73.5)] + [("AGND", x, y) for x in range(33, 98, 11) for y in (33.5, 48.5, 57.5, 73.5)] ) def in1_net_at(x, y): - if point_in_poly(x, y, POCKET): - return "AGND" if y < SEAM or x < AUXW: return "PGND" return "AGND" @@ -154,7 +154,7 @@ def in2_net_at(x, y): return net if x < AUXW: return "5V0" - if point_in_poly(x, y, [(92, 18), (103, 18), (103, 68), (92, 68)]): + if any(point_in_poly(x, y, poly) for poly in IN2_5V0): return "5V0" if point_in_poly(x, y, [(AUXW, 56), (56, 56), (56, H - 0.5), (AUXW, H - 0.5)]): return "5V0"