diff --git a/HANDOVER.md b/HANDOVER.md index ef23157..00eb381 100644 --- a/HANDOVER.md +++ b/HANDOVER.md @@ -4,9 +4,11 @@ Written 2026-07-16, last refreshed 2026-10-06 for the next agent (or future session) continuing this project. Read this + README.md before touching anything. **All four boards are routed with 0 unconnected and 0 DRC errors**, v0.1.0 was released from `master` on 2026-09-29, and the manager L2 / backplane C2 -part change (PR #16) landed on `development` on 2026-10-06. What stands -between the project and the first order is the owner's pick on the BOM -`CHECK:` rows and the gates under "Immediate next steps". +part change (PR #16) landed on `development` on 2026-10-06. On 2026-10-06 +the phase-1/phase-2 L2 moved to the manager's 5 × 5 mm land and the last +BOM `CHECK:` rows were closed, so no `CHECK:` row is left in any BOM. What +stands between the project and the first order is the gates under +"Immediate next steps". ## The user & working agreement @@ -48,9 +50,9 @@ manager, CAN 2.0B @500k. Docs 01–07 are the spec; read 05 (build plan) first | Design docs 01–07 | complete (07 = module firmware, new) | | Phase-1 schematic | **complete, v1**: 7 generated sheets, 137 components, ~90 nets machine-verified; audited (kicad-happy + ngspice 38/40 pass) | | Footprints | all vetted; custom lib `labbench.pretty` (LM5145 RGY, LMR36015 RNX, DAC80502 no-EP WSON, PowerFET_SON5x6_GDS) | -| PCB — Phase 1 | **100 × 80 mm, routed, 0 unconnected, 0 DRC errors** (2026-09-27, PR #9, merged; the 120 × 80 layout it replaces is kept on branch `phase1-120x80`). Re-placed from the netlist, so L1 now has the 17 mm MWSA1707S/XAL1510 superset land and U7 the SC-70-5 land the BOM orders (the 120 × 80 board still carried XAL1350 and SOT-23-5 lands: do not order it). Output bank tightened round the bigger L1; R30 Kelvin shunt, U4/U5 and their sense traces moved as one block with the same geometry; Q3/Q4, J4 and the LTC7004 stack down the right edge. Pipeline: pass-1 + `fanout.py` + Freerouting 1.9 + `finish_routes.py`; 1303 tracks / 353 vias. DRC = 11 silk *warnings*. Fab zip + CPL regenerated. 2026-09-28 (PR #13): OVP_TRIP routed to U10 PB4 for the firmware 0.2 OVP latch | +| PCB — Phase 1 | **100 × 80 mm, routed, 0 unconnected, 0 DRC errors** (2026-09-27, PR #9, merged; the 120 × 80 layout it replaces is kept on branch `phase1-120x80`). Re-placed from the netlist, so L1 now has the 17 mm MWSA1707S/XAL1510 superset land and U7 the SC-70-5 land the BOM orders (the 120 × 80 board still carried XAL1350 and SOT-23-5 lands: do not order it). Output bank tightened round the bigger L1; R30 Kelvin shunt, U4/U5 and their sense traces moved as one block with the same geometry; Q3/Q4, J4 and the LTC7004 stack down the right edge. Pipeline: pass-1 + `fanout.py` + Freerouting 1.9 + `finish_routes.py`; 1303 tracks / 353 vias. DRC = 11 silk *warnings*. Fab zip + CPL regenerated. 2026-09-28 (PR #13): OVP_TRIP routed to U10 PB4 for the firmware 0.2 OVP latch. **ECO 2026-10-06:** L2 1210 → 5×5 mm FNR5040S at (32.6, 61.25), SW_AUX stub re-ended on the new pad, a 0.4 mm F.Cu 5V0 link added from L2's via to C54's; C20/C75–C77 value now 10u/50V. DRC unchanged (10 silk warnings) | | PCB — Phase 3 backplane | **FAB-READY (2026-07-26, d9e1a7b)**: 0 DRC, 0 unconnected, silk 39/39 clean, no plane islands. Gerbers+drills in `fab/` (gitignored) via `python3 ../common/finish_board.py phase3-backplane.kicad_pcb`. Cross-checked: Edge_Cuts exactly 330.00×100.00 mm; drills 2×6.4 (M6 lugs), 16×2.8 (8 slots × 2 XT60 pins), 6×3.2 (M3), 86×1.0, 61×0.4. **Still gated on the XT60 polarity buzz-out before ordering** | -| PCB — Phase 2 | **130 × 90 mm, routed, 0 unconnected, 0 DRC errors (2026-09-27, PR #11, merged 2026-09-28)**; fab zip + CPL committed; pre-order review closed (see the resume section). The 83-unconnected history is kept below for its tooling notes | +| PCB — Phase 2 | **130 × 90 mm, routed, 0 unconnected, 0 DRC errors (2026-09-27, PR #11, merged 2026-09-28)**; fab zip + CPL committed; pre-order review closed (see the resume section). **ECO 2026-10-06:** L2 1210 → 5×5 mm FNR5040S at (68.4, 57.45) r270; its SW_AUX and 5V0 vias now sit in its pads, a 5V0 stub ties C55's via to L2. DRC unchanged (19 warnings, 0 errors). The 83-unconnected history is kept below for its tooling notes | | PCB — Phase 3 manager | **Routed, 0 unconnected, 0 DRC errors (2026-09-27, merged into `development`)**: placement reworked (15+ passives had been placed by stale refdes, far from their pins; U8 buck re-laid tight round its pinout; U11 turned so CAN faces J1; U12 in the USB path), PGND now poured on both layers (was F.Cu 3V3 / B.Cu PGND), USB + CAN pairs and buck power copper hand-drawn and locked (`route_critical.py`), rest Freerouting 1.9 + `finish_routes.py`, 283 PGND stitch vias. DRC = 5 warnings (4 silk, 1 U8 courtyard-override lib mismatch). Antenna keep-out copper-free. Pipeline: `phase3-manager/tools/README.md`. **ECO 2026-10-05:** L2 moved from the 1210 land (no stocked 33 µH above 0.5 A) to a 5×5 mm FNR5040S (FNR5040S330MT, Isat 1.3 A); C54/C55 turned 180° so 5V0 runs straight from L2; PRESENT1/4–7 re-routed round the bigger part with `finish_routes.py`. Still 0 unconnected, 0 DRC errors, 4 warnings (PR #16, merged 2026-10-06; fab zip, BOM and CPL regenerated) | | Module firmware | v0.2 builds clean (7.1 KB): full peripheral binding + CAN dispatch around the host-tested `module_core`. 0.2 (2026-09-28) closes the two protection gaps from the bench-test review: OCP backup #2 (`lb_core_ocp_sample`: INA240 ADC or INA228 SOVL alert >110 % i_max for >5 ms) and OVP latch #4 (OVP_TRIP routed to PB4 on the 100 × 80 board; EXTI4 kills EN, tick latches). Untested on silicon (no board yet) | | Host tests | `cd firmware/tests && make test` — must stay green. **5 suites now**: can, core, manager, scpi, ui | @@ -217,29 +219,28 @@ Notable route_board facts a future session needs: ## Immediate next steps (agreed order) -1. **Owner picks the five BOM `CHECK:` rows** (state 2026-10-06; the - notes in the BOM CSVs say what each one needs): - - Phase-1 C20/C75–C77: no 22 µF 50 V 1210 stocked, 10 µF 50 V fitted - (input ceramic drops from 88 to 40 µF; C21 is the bulk). - - Phase-1 L2: 33 µH on a 1210 land, the strongest stocked part is 0.5 A - against a 1.2 A value. Fine only if 5V0 stays well under ~0.4 A. - - Phase-1 Q1/Q2 and Q3/Q4: NTMFS5C670NLT1G stands in for the - out-of-stock CSD18563Q5A (same S-S-S-G / tab pinout); confirm the pad - overlay in the JLCPCB preview. - - Phase-2 U3: symbol says LM5143RHAR, the BOM orders the cheaper - LM5143QRHARQ1; confirm the RHA0040P land against the Q1 addendum. -2. **Open: Phase-1 and Phase-2 L2 still sit on 1210 lands** (phase-2 L2 - has no LCSC number yet). The manager had the same problem and was fixed - by moving to the 5 × 5 mm FNR5040S land as an ECO (PR #16); the same - change was offered for phase-1/2 and waits on the owner's call. +1. **BOM `CHECK:` rows: all closed 2026-10-06** (stock checked that day): + - Phase-1 C20/C75–C77: no 22 µF 50 V 1210 is stocked anywhere, so the + design value is now 10 µF 50 V X7R (GRM32ER71H106KA12L). About 0.3 Vpp + input ripple at 8 A, D = 0.5, 350 kHz; ~1 A RMS per cap; C21 is the bulk. + - Phase-1 and phase-2 L2: moved to the manager's 5 × 5 mm FNR5040S land + (FNR5040S330MT, C167973, Isat 1.3 A) as an ECO on both routed boards. + - Phase-1 Q1–Q4: CSD18563Q5A is still out of stock; NTMFS5C670NLT1G + stays. Its case 488AA terminals sit within 0.14 mm of the TI part's on + the TI Q5A land, with more clearance to the drain land (0.35 vs 0.24 mm). + - Phase-2 U3: LM5143QRHARQ1 is the LM5143A-Q1. Same pin map, and its + RHA0040N land equals RHA0040P (EP 3.3, 0.5 pitch, 5.8 span); only + wettable flanks differ. It now costs $6.29 (243 at LCSC). +2. **Thin stock (2026-10-06):** INA228AQDGSRQ1 has **5** at LCSC/JLCPCB + (the AIDGSR has 0): one per module plus the backplane, so buy them + first or from Mouser/DigiKey. LTC7004EMSE has 25 (now $11.62). 3. **Order files**: `python3 common/bom.py` (from `hardware/`) writes hidden LCSC/MPN/Manufacturer properties into the schematics (surgical, additive only) and emits `/bom/*-bom.csv` + `*-jlcpcb.csv`; `common/cpl.py` writes the placement files. The part table is `common/lcsc_parts.py`; `--check` fails if anything is stale. Still - open: generic R/C/jellybean/header numbers. The manager and backplane - order files bundled with the v0.1.0 release predate PR #16: regenerate - them from `development` before ordering those two boards. + open: generic R/C/jellybean/header numbers. The v0.1.0 release order + files are superseded; use the v0.2.0 set. 4. Review notes that still hold at order time: manager J3 is the GCT USB4105-GF-A (C3020560; JLCPCB assembly stock, backup -120 C5184243); 13 manager nets cross under the USB pair on B.Cu (fine at full speed). @@ -254,7 +255,8 @@ Notable route_board facts a future session needs: - **XT60 polarity continuity check** (MECHANICAL.md — verify J1 male vs backplane J-female in the *mated* orientation; the footprint descr still says pads 1/2 are ASSUMED +/−). -- **Re-verify LCSC stock** of the order-early parts (LTC7004, CSD19536KTT). +- **Re-verify LCSC stock** of the order-early parts (INA228AQDGSRQ1, + LTC7004, CSD19536KTT). - **Manager board only: confirm the fab quotes 0.2 mm drilling** on a 2-layer stackup — the board rule was relaxed from 0.3 to 0.2 for the stock ESP32 footprint's thermal-pad stitching, and that is above some cheapest-process diff --git a/README.md b/README.md index 26840db..9ad9955 100644 --- a/README.md +++ b/README.md @@ -73,13 +73,13 @@ module. v0.1.0 was released from `master` on 2026-09-29. | Area | State | |---|---| | Design docs | Complete: 01–10, plus the build guide (11) and Phase-1 bench test procedure (12) | -| Phase-1 module (150 W) | 100 × 80 mm, **routed, 0 unconnected, 0 DRC errors**, fab zip and CPL committed. OVP_TRIP routed to the MCU (PB4) for the firmware 0.2 OVP latch. Next: the owner picks the four Phase-1 BOM `CHECK:` rows, then order and run [docs/12](docs/12-phase1-bench-tests.md). The older 120 × 80 layout on branch `phase1-120x80` has wrong L1/U7 lands: do not order it | -| Phase-2 module (600 W) | 130 × 90 mm, **routed, 0 unconnected, 0 DRC errors**, fab zip and CPL committed; pre-order review closed (HANDOVER) | +| Phase-1 module (150 W) | 100 × 80 mm, **routed, 0 unconnected, 0 DRC errors**, fab zip and CPL committed. OVP_TRIP routed to the MCU (PB4) for the firmware 0.2 OVP latch. L2 moved to a 5 × 5 mm land (2026-10-06). Next: order and run [docs/12](docs/12-phase1-bench-tests.md). The older 120 × 80 layout on branch `phase1-120x80` has wrong L1/U7 lands: do not order it | +| Phase-2 module (600 W) | 130 × 90 mm, **routed, 0 unconnected, 0 DRC errors**, fab zip and CPL committed; pre-order review closed (HANDOVER); L2 moved to a 5 × 5 mm land (2026-10-06) | | Phase-3 backplane | 330 × 100 mm, fab-ready; gated on the XT60 polarity buzz-out ([MECHANICAL.md](hardware/MECHANICAL.md)) | | Phase-3 manager | 100 × 80 mm, **routed, 0 unconnected, 0 DRC errors**; L2 moved to a 5 × 5 mm land (2026-10-05) | | Module firmware | v0.2 builds (~7 KB, bare-metal STM32G431) with the OCP backup and OVP latch; control core host-tested | | Manager firmware | v0.2 builds on ESP-IDF 5.3.2; manager, SCPI and UI cores host-tested | -| BOM / sourcing | LCSC numbers in the schematics and per-board BOM and CPL files (`hardware/common/bom.py`); five `CHECK:` rows await the owner's pick (four Phase-1, one Phase-2); generic R/C parts not yet numbered | +| BOM / sourcing | LCSC numbers in the schematics and per-board BOM and CPL files (`hardware/common/bom.py`); no `CHECK:` rows left (closed 2026-10-06); INA228 stock is thin (5 at LCSC); generic R/C parts not yet numbered | | CI | GitHub Actions: host tests, module and manager firmware builds on every PR | Complete Phase-1 build (parts, five PCBs, stencil, shipping) ≈ US$100–125. diff --git a/docs/06-phase1-circuit-design.md b/docs/06-phase1-circuit-design.md index 755f217..1636c1b 100644 --- a/docs/06-phase1-circuit-design.md +++ b/docs/06-phase1-circuit-design.md @@ -37,8 +37,10 @@ e.g. Würth 744325550 class. Ripple ≈ ESR·ΔI ≈ 7.5 mΩ · 1.7 A ≈ 13 mVpp ✓. LC corner: f_LC = 1/(2π√(10 µH · ~480 µF)) ≈ **2.3 kHz**; ESR zero ≈ 1/(2π·7.5 mΩ·440 µF) ≈ **48 kHz** — both needed for compensation (§6). -- **Input:** 4 × 22 µF 50 V X7R close to the FETs (input RMS ripple ≈ I_out/2 = 4 A - at D = 0.5) + 220 µF 50 V electrolytic bulk. +- **Input:** 4 × 10 µF 50 V X7R close to the FETs (input RMS ripple ≈ I_out/2 = 4 A + at D = 0.5, ~1 A per cap) + 220 µF 50 V electrolytic bulk. 22 µF 50 V 1210 is + not stocked; at 30 V bias each 10 µF keeps ~4.5 µF, so ΔV ≈ 8 A · 0.25 / + (350 kHz · 18 µF) ≈ 0.3 Vpp at the worst duty cycle. - **Preload:** 2.2 kΩ across the output — gives DEM mode a minimum load so the output doesn't drift up at zero load, and discharges the caps when disabled. diff --git a/docs/11-build-guide.md b/docs/11-build-guide.md index 99a2ca6..d3e722a 100644 --- a/docs/11-build-guide.md +++ b/docs/11-build-guide.md @@ -17,10 +17,10 @@ takes over and checks that it actually meets the spec. | Board | What it is | Can you order it? | |---|---|---| -| **Phase-1 module** (`hardware/phase1-module/`) | Single 150 W channel: 24 V in, 0–20 V / 0–8 A out, CAN controlled | **Yes, once the parts in §3.3 are settled.** Order the 100 × 80 board on `development`/`master`; the 120 × 80 layout on branch `phase1-120x80` has wrong L1/U7 lands | -| Phase-2 module (`hardware/phase2-module/`) | 600 W channel, 0–28 V / 0–30 A, hot-swap input | Routed and fab-ready (2026-09-27). Wait for Phase-1 to pass its bench tests (docs/05 exit criteria) and settle the U3 `CHECK:` row | +| **Phase-1 module** (`hardware/phase1-module/`) | Single 150 W channel: 24 V in, 0–20 V / 0–8 A out, CAN controlled | **Yes.** Check the parts in §3.3, then order the 100 × 80 board on `development`/`master`; the 120 × 80 layout on branch `phase1-120x80` has wrong L1/U7 lands | +| Phase-2 module (`hardware/phase2-module/`) | 600 W channel, 0–28 V / 0–30 A, hot-swap input | Routed and fab-ready (2026-09-27). Wait for Phase-1 to pass its bench tests (docs/05 exit criteria) | | Phase-3 backplane (`hardware/phase3-backplane/`) | 8-slot bus with CAN, E-stop and bus metering | Fab-ready, but gated on the XT60 polarity check and only useful with Phase-2 modules and a manager | -| Phase-3 manager (`hardware/phase3-manager/`) | ESP32-S3 with display, encoder, USB SCPI | Routed and fab-ready. Confirm the fab quotes 0.2 mm drilling on 2 layers; regenerate the order files if yours predate 2026-10-06 (L2 changed) | +| Phase-3 manager (`hardware/phase3-manager/`) | ESP32-S3 with display, encoder, USB SCPI | Routed and fab-ready. Confirm the fab quotes 0.2 mm drilling on 2 layers; use the v0.2.0 order files or newer (L2 changed 2026-10-05) | So today this guide is about the **Phase-1 module**. It is the "learning board": every risky part of the design (analog CV/CC loops, sensing, @@ -126,13 +126,11 @@ tolerance matters in a few places: | Item | What to decide | |---|---| -| **Q1–Q4 (power and disconnect FETs)** | The CSD18563Q5A was out of stock on 2026-09-27; the BOM orders onsemi NTMFS5C670NLT1G (60 V, 6.1 mΩ, Qg 20 nC) with the same S-S-S-G / tab pinout. Confirm the pad overlay in the JLCPCB preview, or buy CSD18563Q5A if it is back | -| **C20, C75–C77 (input ceramics)** | No 22 µF 50 V 1210 is stocked; the BOM orders 10 µF 50 V, which drops the input ceramic from 88 to 40 µF (C21 is the bulk). Accept it or source 22 µF elsewhere | -| **L2 (5V0 aux buck inductor)** | The 1210 land only takes 33 µH parts rated about 0.5 A; the value asks for 1.2 A. Fine if the 5V0 load (fan included) stays well under ~0.4 A. A bigger 5 × 5 mm land, as on the manager, is an open option | +| **Q1–Q4 (power and disconnect FETs)** | The CSD18563Q5A is out of stock (2026-10-06); the BOM orders onsemi NTMFS5C670NLT1G (60 V, 6.1 mΩ, Qg 20 nC), same S-S-S-G / tab pinout, overlay on the land checked. If the CSD18563Q5A is back, either part fits | | **R30 (2 mΩ shunt)** | The LCSC part (C2994640) is cheap but its TCR is unverified. The CC accuracy depends on it. A Vishay WSLP-class part (~US$1.50) is the safe choice | | **U8, U11 variants** | The LCSC variants (LMR36015ARNXR, TCAN1042VDRQ1) differ from the symbol values. Both are the right function (adjustable buck, VIO-capable CAN transceiver) in the same package | | **J1, J4 terminal blocks** | The footprint is a 5.0 mm Phoenix PT; SOURCING.md lists 5.08 mm 2EDG plugs. Buy a header that matches the 5.0 mm footprint | -| **Order-early parts** | LTC7004EMSE had only 5 in stock at LCSC. Put it in the cart first | +| **Order-early parts** | INA228AQDGSRQ1 had 5 and LTC7004EMSE 25 in stock at LCSC (2026-10-06). Put them in the cart first | ## 4. Assemble @@ -179,7 +177,7 @@ is cheap; a short at 24 V is not. | J2 SWD | 1 = 3V3, 2 = SWDIO, 3 = SWCLK, 4 = NRST, 5 = GND | See the note on pin 1 below | | J3 UART | 1 = GND, 2 = TX (from MCU), 3 = RX (to MCU) | 115200 8N1, 3.3 V | | J5 BACKPLANE | 1 = CAN_H, 2 = CAN_L, 3 = HW_EN, 4–6 = SLOT_ID0–2, 7–8 = PGND | The bench harness plugs in here | -| J6 FAN | 1 = +5 V, 2 = fan return (switched low side) | Small 5 V fan; keep it under ~200 mA. The 5 V rail is sized for 0.5 A total, and the 1210 L2 the BOM fits is rated about 0.5 A, so keep the whole 5V0 load under ~0.4 A (§3.3) | +| J6 FAN | 1 = +5 V, 2 = fan return (switched low side) | Small 5 V fan; keep it under ~200 mA. The 5 V rail is sized for 0.5 A total; L2 (FNR5040S330MT) is rated 1.2 A, so the converter, not the inductor, sets that limit | **J2 pin 1:** a genuine ST-Link only senses target voltage on this pin. Many clone ST-Link V2 dongles *drive* 3.3 V onto it, which then fights the board's @@ -270,14 +268,14 @@ ADC sampling on the high-impedance V_MEAS divider, then the DAC80502 gain. aux and MCU blocks, with a 2-phase LM5143 power stage and LM5069 hot-swap input. Its assembly is the same as above plus heavier soldering on the power stage. The board is routed and the 220 µF caps are settled (EEHZA1V221P); - the one open BOM item is the LM5143 Q1-variant land check (U3), plus the - 1210 L2 question that Phase-1 has too. + the LM5143 Q1 variant (U3) was checked against its land on 2026-10-06, and + L2 moved to a 5 × 5 mm land like Phase-1's. - **Phase-3 backplane and manager** turn modules into a rack. Before ordering the backplane, mate one XT60PW-M/F pair and buzz out which pad connects to which, and which cavity is marked "+" ([hardware/MECHANICAL.md](../hardware/MECHANICAL.md)). Pads 1 = + on both sides is still an assumption. The manager board is - routed; its order files changed on 2026-10-06 (L2 on a 5 × 5 mm land), so - use ones generated from `development` or later. The manager firmware builds + routed; its order files changed on 2026-10-05 (L2 on a 5 × 5 mm land), so + use the v0.2.0 set or newer. The manager firmware builds in CI (`firmware/manager/idf`, ESP-IDF 5.3.2); its bring-up knobs are in [docs/10](10-manager-firmware.md). diff --git a/hardware/SOURCING.md b/hardware/SOURCING.md index 710ffea..0fd3c42 100644 --- a/hardware/SOURCING.md +++ b/hardware/SOURCING.md @@ -27,19 +27,19 @@ Decisions taken this pass (user-approved 2026-07-18): | Part | LCSC | $ qty-1 | Stock | Note | |---|---|---|---|---| -| LM5143QRHARQ1 | C5219258 | 2.93 | 52 | automotive variant CHEAPER than LM5143RHAR ($4.62/C5219297); same VQFN-40 6×6 — confirm RHA0040P land vs Q1 addendum at order | +| LM5143QRHARQ1 | C5219258 | 6.29 | 243 | the LM5143A-Q1 (TI ZHCSQC8). Checked 2026-10-06: same 40-pin map as the LM5143, and its RHA0040N land matches RHA0040P (6×6, 0.5 pitch, 0.25×0.6 pads at 5.8 span, EP 3.3 ±0.1); only wettable flanks differ. No longer cheaper than LM5143RHAR (C5219297) | | LM5069MM-2/NOPB | C111822 | 1.17 | 6.6k | | | CSD18540Q5B (TI) | C86513 | 1.43 | 953 | ×8/module. TOKMAS/“ES” clones at $0.45–0.57 exist — **do not substitute** power-stage FETs | | CSD19536KTT | C2687963 | 4.94 | **12** | hot-swap pass FET — SOA-critical, no clone. **Order early** | | STM32G431CBT6 | C529355 | 2.85 | 67k | | | DAC80502DRXR | C1880990 | 4.19 | 189 | | -| INA228AQDGSRQ1 | C5214669 | 17.16 | 142 | ×1/module + 1 backplane. The AIDGSR (C2887910, $3.83) was out of stock on 2026-09-28; the Q1 grade is pin- and register-identical. Swap back if it returns | +| INA228AQDGSRQ1 | C5214669 | 17.16 | **5** (2026-10-06) | ×1/module + 1 backplane. The AIDGSR (C2887910, $3.83) was out of stock on 2026-09-28; the Q1 grade is pin- and register-identical. Swap back if it returns | | INA240A3DR | C2060584 | 1.87 | 1.7k | | | OPA2333AIDGKR | C19608 | 1.14 | 1.3k | | | TCAN1042VDRQ1 | C485806 | 0.57 | 2.6k | V = VIO variant ✓ (Phase-1 finding) | | LMR36015ARNXR | C1850345 | 1.91 | 1.2k | | | NCP1117ST33T3G | C26537 | 0.21 | 14k | | -| LTC7004EMSE#PBF | C690105 | 5.77 | **5** | thinnest stock in the BOM; 3 needed + spares. **Order early** (IMSE $6.98/30 as fallback) | +| LTC7004EMSE#PBF | C690105 | 11.62 | **25** (2026-10-06) | thinnest stock in the BOM; 3 needed + spares. **Order early** (IMSE $6.98/30 as fallback) | | TLV7011DCKR | C193688 | 0.27 | 838 | **SC-70-5** instead of DBVR (SOT-23-5, $0.52, only 42 left); the boards carry the SC-70-5 land | | TL431BIDBZR | C41283 | 0.054 | 7.9k | | | TS5A3166DBVR | C353035 | 0.28 | 7.6k | replaces TMUX1101 (not stocked on LCSC). Verified + applied 2026-07-18 (§F) | @@ -47,7 +47,7 @@ Decisions taken this pass (user-approved 2026-07-18): | ESP32-S3-WROOM-1-N8R2 | C2913204 | 5.01 | 18k | | | TPD2E001DRLR | C150526 | 0.16 | 14k | | | LM5145RGYR (P1) | C485912 | 1.55 | 5.2k | | -| CSD18563Q5A (P1) | C77239 | 0.85 | 794 | out of stock 2026-09-27: the P1 BOM orders onsemi NTMFS5C670NLT1G (C179626, $0.49) for Q1–Q4 instead, same S-S-S-G / tab pinout. Still a `CHECK:` row: confirm the pad overlay in the JLCPCB preview | +| CSD18563Q5A (P1) | C77239 | 0.85 | 794 | still out of stock 2026-10-06: the P1 BOM orders onsemi NTMFS5C670NLT1G (C179626, $0.49, 13.7k) for Q1–Q4 instead, same S-S-S-G / tab pinout. Overlay checked against case 488AA: terminals within 0.14 mm of the TI part's on the Q5A land, 0.35 mm from the drain land (0.24 for the TI part) | | 2N7002 / BAT54W / 1N4148WS / SMBJ33A / AO3401A | — | 0.01–0.05 | ≫10k | jellybeans, any reputable line | ## B. Magnetics & power passives @@ -65,8 +65,8 @@ Decisions taken this pass (user-approved 2026-07-18): | 220 µF 35 V hybrid ×4 | C454349 | 1.42 | **1** | Panasonic EEHZA1V221P D10×10.2, 20 mΩ / 2.5 A — fits the CP_Elec_10x10.5 land. Stocked alternative on the same land: SUNCON 35HVH220M+P (C179812, D10×12.5, 8 in stock 2026-09-28). The earlier D8 SVZ pick (C2923769) did not fit the land and is out of stock | | 470 µF 50 V bulk | C106666 | 0.10 | 73k | **THT radial D10×20** — cheaper + stronger than SMD; phase-2 C14 carries the CP_Radial_D10 land | | 470 µF 50 V SMD (backplane C2) | C462700 | 1.63 | 633 (JLCPCB) | Nichicon UCX1H471MNS1MS, 16×16.5, 70 mΩ, 1.0 A @100 kHz, 135 °C. The board has an SMD CP_Elec_16x17.5 land (17×17 platform), not the THT D10 above; 16×16.5 cans fit it. Fallback: Panasonic EEEFK1H471AM (C178551, 131). Picked 2026-10-05 | -| 33 µH aux-buck inductor (manager L2) | C167973 | 0.06 | 51k (JLCPCB) | cjiang FNR5040S330MT, 5×5×4 mm: **Isat 1.30 A min / Irms 1.20 A min / DCR 0.244 Ω max** (cjiang FNR datasheet). No 1210 33 µH is stocked above 0.5 A, so the manager land grew to L_Changjiang_FNR5040S (2026-10-05). Phase-1/2 L2 are still 1210: see the next row | -| 33 µH 1210 (phase-1 L2) | C223226 | 0.25 | — | Taiyo Yuden CBC3225T330KR, 0.5 A: the strongest stocked 1210 33 µH, against a 1.2 A value. A BOM `CHECK:` row (fine only if 5V0 stays well under ~0.4 A). Phase-2 L2 has no number yet. Moving both to the manager's 5×5 land is offered and waits on the owner | +| 33 µH aux-buck inductor (manager L2) | C167973 | 0.06 | 51k (JLCPCB) | cjiang FNR5040S330MT, 5×5×4 mm: **Isat 1.30 A min / Irms 1.20 A min / DCR 0.244 Ω max** (cjiang FNR datasheet). No 1210 33 µH is stocked above 0.5 A, so the manager land grew to L_Changjiang_FNR5040S (2026-10-05) and the phase-1/phase-2 L2 lands followed (2026-10-06). Same part on all three boards | +| 10 µF 50 V X7R 1210 (phase-1 input C20/C75–C77) | C77102 | 0.33 | 28k | Murata GRM32ER71H106KA12L. No 22 µF 50 V 1210 is stocked, so 10 µF is the design value since 2026-10-06 (≈0.3 Vpp input ripple at 8 A) | | 10 µF 50 V X7S 1210 ×8+6 | C126612 | 0.144 | 43k | GCM32EC71H106KA03L; also replaces the 22 µF/50 V output MLCCs (that value barely exists) | | 8 MHz 3225 crystal | C400090 | 0.105 | 200k | cheap parts are CL=12 pF → C66/C67 = 18 p (APPLIED, both phases) | @@ -105,11 +105,13 @@ US$300–380** including boards, spares and the Coilcraft A/B pair. ## E. Order-early / risk list -1. **LTC7004EMSE — 5 in stock.** 3 boards need 3 + spares. First thing in - the cart, or accept IMSE ($6.98, 30 pcs). +1. **LTC7004EMSE — 25 in stock (2026-10-06, $11.62).** 3 boards need 3 + + spares. First thing in the cart. +1a. **INA228AQDGSRQ1 — 5 in stock (2026-10-06)**, the AIDGSR 0. One per + module + one backplane: buy them first, or from Mouser/DigiKey. 2. **CSD19536KTT — 12 in stock.** SOA-verified hot-swap FET, no substitute without redoing the SOA math. -3. LM5143QRHARQ1 (52) and MWSA1707S-6R8MT (67) — fine for this build, +3. LM5143QRHARQ1 (243) and MWSA1707S-6R8MT (163) — fine for this build, thin for a rebuy; recheck at order time. 4. Clones: FET clones rejected for the power path; UMW TCA9535 and generic EC11/2N7002/diodes accepted. diff --git a/hardware/common/eco_swap_fp.py b/hardware/common/eco_swap_fp.py new file mode 100644 index 0000000..172d08a --- /dev/null +++ b/hardware/common/eco_swap_fp.py @@ -0,0 +1,81 @@ +"""Engineering change on a routed board: swap one footprint for another land. + + python3.12 common/eco_swap_fp.py BOARD REF LIB:NAME X Y ROT + +X, Y are KiCad page mm (the generated boards put their origin at 20,20), +ROT in degrees. The new footprint is loaded from the system library (or +the project's labbench.pretty), placed at X, Y, ROT and given the old +footprint's reference, value, fields (sheet name included), schematic path and, +pad number by pad number, its nets. The old footprint is removed. Tracks +are not touched: re-attach them with the board's ECO script and check +with run_drc.py. + +Used for the 2026-10-06 phase-1 / phase-2 L2 change (1210 -> FNR5040S), +the same land change PR #16 made on the manager. +""" +import os +import sys + +import pcbnew +from pcbnew import FromMM + +HERE = os.path.dirname(os.path.abspath(__file__)) +LIBS = {"labbench": os.path.join(HERE, "..", "phase1-module", "lib", "labbench.pretty")} +SYSTEM_DIR = "/usr/share/kicad/footprints" +GRAVEYARD = [] + + +def load(fpid): + nick, name = fpid.split(":") + path = LIBS.get(nick, os.path.join(SYSTEM_DIR, nick + ".pretty")) + fp = pcbnew.FootprintLoad(path, name) + if fp is None: + sys.exit(f"cannot load {fpid} from {path}") + fp.SetFPID(pcbnew.LIB_ID(nick, name)) + return fp + + +def swap(board, ref, fpid, x, y, rot): + old = board.FindFootprintByReference(ref) + if old is None: + sys.exit(f"{ref} not on board") + new = load(fpid) + nets = {p.GetNumber(): p.GetNet() for p in old.Pads()} + missing = set(nets) - {p.GetNumber() for p in new.Pads()} + if missing: + sys.exit(f"{fpid} has no pad(s) {sorted(missing)} for {ref}") + new.SetReference(ref) + new.SetValue(old.GetValue()) + for k, v in old.GetProperties().items(): + new.SetProperty(k, v) + new.SetPath(old.GetPath()) + new.SetAttributes(old.GetAttributes()) + new.Reference().SetVisible(old.Reference().IsVisible()) + new.Value().SetVisible(old.Value().IsVisible()) + board.Add(new) + new.SetOrientationDegrees(rot) + new.SetPosition(pcbnew.VECTOR2I(FromMM(x), FromMM(y))) + for p in new.Pads(): + if p.GetNumber() in nets: + p.SetNet(nets[p.GetNumber()]) + new.SetLocked(old.IsLocked()) + board.Remove(old) + GRAVEYARD.append(old) # removed items must outlive their SWIG proxies + + +def main(): + if len(sys.argv) != 7: + sys.exit(__doc__) + path, ref, fpid = sys.argv[1:4] + x, y, rot = map(float, sys.argv[4:7]) + board = pcbnew.LoadBoard(path) + swap(board, ref, fpid, x, y, rot) + board.Save(path) + for p in board.FindFootprintByReference(ref).Pads(): + q = p.GetPosition() + print(f"{ref}.{p.GetNumber()} {p.GetNetname()} at " + f"({pcbnew.ToMM(q.x):.2f}, {pcbnew.ToMM(q.y):.2f})") + + +if __name__ == "__main__": + main() diff --git a/hardware/common/lcsc_parts.py b/hardware/common/lcsc_parts.py index cce2ab2..aff999a 100644 --- a/hardware/common/lcsc_parts.py +++ b/hardware/common/lcsc_parts.py @@ -19,9 +19,11 @@ PARTS = [ # ---- A. Semiconductors ------------------------------------------------- - ({P2: ["U3"]}, "C5219258", "LM5143QRHARQ1", "TI", 2.93, - "CHECK: symbol value says LM5143RHAR; SOURCING picked the cheaper Q1 " - "variant (same VQFN-40) - confirm RHA0040P land vs the Q1 addendum"), + ({P2: ["U3"]}, "C5219258", "LM5143QRHARQ1", "TI", 6.29, + "symbol value says LM5143RHAR; this is the LM5143A-Q1 (TI ZHCSQC8, " + "2022). Same 40-pin map and the same land: RHA0040N vs RHA0040P is " + "6x6 body, 0.5 pitch, 0.25x0.6 pads at 5.8 span, EP 3.3 +-0.1 in both; " + "the Q1 part only adds wettable flanks (checked 2026-10-06)"), ({P2: ["U12"]}, "C111822", "LM5069MM-2/NOPB", "TI", 1.17, ""), ({P2: ["Q1", "Q2", "Q3", "Q4", "Q10", "Q11", "Q12", "Q13"]}, "C86513", "CSD18540Q5B", "TI", 1.43, @@ -34,7 +36,8 @@ ({P1: ["U5"], P2: ["U5"], BP: ["U1"]}, "C5214669", "INA228AQDGSRQ1", "TI", 17.16, "automotive grade of INA228AIDGSR, same VSSOP-10 pinout and register " "map (no firmware change); the AIDGSR (C2887910) was still out of stock " - "on 2026-09-28 - swap back if it returns, it is about a quarter of the price"), + "on 2026-09-28 - swap back if it returns, it is about a quarter of the price. " + "Only 5 in stock on 2026-10-06: order early"), ({P1: ["U4"], P2: ["U4"]}, "C2060584", "INA240A3DR", "TI", 1.87, ""), ({P1: ["U2"], P2: ["U2"]}, "C19608", "OPA2333AIDGKR", "TI", 1.14, ""), ({P1: ["U11"], P2: ["U11"], MGR: ["U11"]}, @@ -47,8 +50,8 @@ "commercial ARNXR, same RNX package"), ({P1: ["U9"], P2: ["U9"], MGR: ["U9"]}, "C26537", "NCP1117ST33T3G", "onsemi", 0.21, ""), - ({P1: ["U6"], P2: ["U6"]}, "C690105", "LTC7004EMSE#PBF", "ADI", 5.77, - "thinnest stock in the BOM - order early (IMSE fallback)"), + ({P1: ["U6"], P2: ["U6"]}, "C690105", "LTC7004EMSE#PBF", "ADI", 11.62, + "thin stock (25 on 2026-10-06) - order early (IMSE fallback)"), ({P1: ["U7"], P2: ["U7"]}, "C193688", "TLV7011DCKR", "TI", 0.27, "SC-70-5 (DCK)"), ({P2: ["D8"]}, "C41283", "TL431BIDBZR", "TI", 0.054, ""), @@ -60,10 +63,12 @@ ({P1: ["U3"]}, "C485912", "LM5145RGYR", "TI", 1.55, ""), ({P1: ["Q1", "Q2", "Q3", "Q4"]}, "C179626", "NTMFS5C670NLT1G", "onsemi", 0.49, - "CHECK: stands in for CSD18563Q5A (C77239, out of stock 2026-09-27). " - "60 V, 6.1 mOhm, Qg 20 nC vs 5.7 mOhm / 15 nC; SO-8FL has the same " - "S-S-S-G / drain-tab pinout as the TI Q5A land - confirm the pad " - "overlay in the JLCPCB preview. Q3/Q4 dissipate about 0.6 W each at 10 A"), + "stands in for CSD18563Q5A (C77239, still out of stock 2026-10-06). " + "60 V, 6.1 mOhm, Qg 20 nC vs 5.7 mOhm / 15 nC; same S-S-S-G / drain-tab " + "pinout. Overlay on the TI Q5A land checked against case 488AA: " + "terminals within 0.14 mm of the TI part's (E 6.15 vs 6.00, L 0.575 vs " + "0.61, K 1.35 vs 1.10), 0.35 mm from the drain land edge vs 0.24 for " + "the TI part. Q3/Q4 dissipate about 0.6 W each at 10 A"), # ---- B. Magnetics & power passives ------------------------------------ ({P2: ["L1", "L3"]}, "C6238332", "MWSA1707S-6R8MT", "Sunlord", 1.72, @@ -121,7 +126,9 @@ # No 1210 33 uH is stocked above 0.5 A, so the manager's L2 land grew to # the 5x5 mm FNR5040S (board re-routed round it). Datasheet: 33 uH +-20 %, # DCR 0.244 ohm max, Isat 1.30 A min / 1.45 A typ, Irms 1.20 A min. - ({MGR: ["L2"]}, "C167973", "FNR5040S330MT", "cjiang (Changjiang Microelectronics)", + # Phase-1 and phase-2 L2 had the same 1210 land and moved to the same + # part on 2026-10-06 (ECO on both routed boards). + ({MGR: ["L2"], P1: ["L2"], P2: ["L2"]}, "C167973", "FNR5040S330MT", "cjiang (Changjiang Microelectronics)", 0.06, "5x5x4 mm shielded, KiCad L_Changjiang_FNR5040S land; Isat 1.30 A " "min covers the 33u/1.2A value. Any 5040-size 33 uH >=1.2 A part with " "the same 2.3 mm pad gap fits"), @@ -161,7 +168,9 @@ ({P1: ["C66", "C67"]}, "C1647", "CL10C180JB8NNNC", "Samsung Electro-Mechanics", 0.0157, "C0G"), ({P1: ["C20", "C75", "C76", "C77"]}, "C77102", "GRM32ER71H106KA12L", "Murata Electronics", 0.3274, - "CHECK: symbol says 22u/50V but no 22 uF 50 V 1210 is stocked at JLCPCB; this is 10 uF 50 V X7R (the phase-2 input part is also 10 uF) - input ceramic drops from 88 to 40 uF nominal, C21 is the bulk"), + "10 uF 50 V X7R: no 22 uF 50 V 1210 is stocked, so the design value is " + "now 10u (phase-2 uses 10 uF too). 4 x ~4.5 uF at 30 V bias gives about " + "0.3 Vpp input ripple at 8 A, D = 0.5, 350 kHz; ~1 A RMS each; C21 is the bulk"), ({P1: ["C21"]}, "C2887271", "RVT220UF50V67RV0021", "KNSCHA", 0.1412, "SMD D10x10.2 aluminium, fits CP_Elec_10x10.5"), ({P1: ["C22", "C78"]}, "C46550471", "MA35V220M8X12", "jieerrui", 0.2872, @@ -180,8 +189,6 @@ "1N4148WS is the SOD-323 version (1N4148W is SOD-123)"), ({P1: ["D7"]}, "C2286", "KT-0603R", "Hubei KENTO Elec", 0.0075, "red 0603 LED (Basic)"), - ({P1: ["L2"]}, "C223226", "CBC3225T330KR", "Taiyo Yuden", 0.2475, - "CHECK: value says 33u/1.2A but no 1210 33 uH is rated near 1.2 A; this is the strongest stocked one (0.5 A). Fine if the 5V0 load stays well under ~0.4 A, otherwise move to a bigger inductor footprint"), ({P1: ["Q5", "Q6", "Q7", "Q8", "Q9"]}, "C8545", "2N7002", "Jiangsu Changjing Electronics Technology Co., Ltd.", 0.0178, ""), ({P1: ["R1"]}, "C861257", "RT0603BRD0725K5L", "YAGEO", 0.0353, diff --git a/hardware/common/sheets_common.py b/hardware/common/sheets_common.py index f17c4ea..c41a70c 100644 --- a/hardware/common/sheets_common.py +++ b/hardware/common/sheets_common.py @@ -406,7 +406,7 @@ def build_aux_rails(sh, p): ll("AUX_VCC", c53, 1) sh.power("PGND", *c53.pin_pos(2), ground=True) l2 = sh.add(kg.Placed(L, "L2", "33u/1.2A", 113.03, 91.44, rot=90, - footprint="Inductor_SMD:L_1210_3225Metric")) + footprint="Inductor_SMD:L_Changjiang_FNR5040S")) ll("SW_AUX", l2, 1) sh.power("5V0", *l2.pin_pos(2)) r50 = res("R50", "100K 1%", 127.0, 88.9) diff --git a/hardware/phase1-module/aux-rails.kicad_sch b/hardware/phase1-module/aux-rails.kicad_sch index 06b5ab1..240b222 100644 --- a/hardware/phase1-module/aux-rails.kicad_sch +++ b/hardware/phase1-module/aux-rails.kicad_sch @@ -473,11 +473,11 @@ (uuid 5fdd283b-3019-4bfb-a2d4-552f25eec200) (property "Reference" "L2" (at 113.03 87.63 0) (effects (font (size 1.27 1.27)))) (property "Value" "33u/1.2A" (at 113.03 95.25 0) (effects (font (size 1.27 1.27)))) - (property "Footprint" "Inductor_SMD:L_1210_3225Metric" (at 113.03 91.44 0) (effects (font (size 1.27 1.27)) hide)) + (property "Footprint" "Inductor_SMD:L_Changjiang_FNR5040S" (at 113.03 91.44 0) (effects (font (size 1.27 1.27)) hide)) (property "Datasheet" "~" (at 113.03 91.44 0) (effects (font (size 1.27 1.27)) hide)) - (property "LCSC" "C223226" (at 113.03 91.44 0) (effects (font (size 1.27 1.27)) hide)) - (property "MPN" "CBC3225T330KR" (at 113.03 91.44 0) (effects (font (size 1.27 1.27)) hide)) - (property "Manufacturer" "Taiyo Yuden" (at 113.03 91.44 0) (effects (font (size 1.27 1.27)) hide)) + (property "LCSC" "C167973" (at 113.03 91.44 0) (effects (font (size 1.27 1.27)) hide)) + (property "MPN" "FNR5040S330MT" (at 113.03 91.44 0) (effects (font (size 1.27 1.27)) hide)) + (property "Manufacturer" "cjiang (Changjiang Microelectronics)" (at 113.03 91.44 0) (effects (font (size 1.27 1.27)) hide)) (pin "1" (uuid a3671b80-29c5-483a-a42e-467184df3acd)) (pin "2" (uuid 15d0e84c-2dee-467f-97b8-641fa3f8f460)) (instances (project "phase1-module" (path "/e63e39d7-6ac0-4ffa-9e5c-2b84c50a0001/e63e39d7-6ac0-4ffa-9e5c-2b84c50a0014" (reference "L2") (unit 1)))) diff --git a/hardware/phase1-module/bom/phase1-module-bom.csv b/hardware/phase1-module/bom/phase1-module-bom.csv index 037b05c..714d8b9 100644 --- a/hardware/phase1-module/bom/phase1-module-bom.csv +++ b/hardware/phase1-module/bom/phase1-module-bom.csv @@ -6,7 +6,7 @@ Item,Qty,References,Value,Footprint,LCSC,MPN,Manufacturer,Unit USD,Ext USD,Note 5,1,C17,DNP,Capacitor_SMD:C_0603_1608Metric,,,,,,do not populate (value says DNP) 6,1,C18,47n,Capacitor_SMD:C_0603_1608Metric,C1622,CL10B473KB8NNNC,Samsung Electro-Mechanics,0.0073,0.007, 7,1,C19,15p,Capacitor_SMD:C_0603_1608Metric,C1644,CL10C150JB8NNNC,Samsung Electro-Mechanics,0.0113,0.011,C0G -8,4,C20 C75 C76 C77,22u/50V X7R,Capacitor_SMD:C_1210_3225Metric,C77102,GRM32ER71H106KA12L,Murata Electronics,0.3274,1.31,"CHECK: symbol says 22u/50V but no 22 uF 50 V 1210 is stocked at JLCPCB; this is 10 uF 50 V X7R (the phase-2 input part is also 10 uF) - input ceramic drops from 88 to 40 uF nominal, C21 is the bulk" +8,4,C20 C75 C76 C77,10u/50V X7R,Capacitor_SMD:C_1210_3225Metric,C77102,GRM32ER71H106KA12L,Murata Electronics,0.3274,1.31,"10 uF 50 V X7R: no 22 uF 50 V 1210 is stocked, so the design value is now 10u (phase-2 uses 10 uF too). 4 x ~4.5 uF at 30 V bias gives about 0.3 Vpp input ripple at 8 A, D = 0.5, 350 kHz; ~1 A RMS each; C21 is the bulk" 9,1,C21,220u/50V,Capacitor_SMD:CP_Elec_10x10.5,C2887271,RVT220UF50V67RV0021,KNSCHA,0.1412,0.141,"SMD D10x10.2 aluminium, fits CP_Elec_10x10.5" 10,2,C22 C78,220u/25V poly,Capacitor_SMD:CP_Elec_8x11.9,C46550471,MA35V220M8X12,jieerrui,0.2872,0.574,"35 V polymer SMD D8x11.5, 16 mOhm; fits CP_Elec_8x11.9" 11,4,C23 C79 C80 C81,22u/25V X7R,Capacitor_SMD:C_1210_3225Metric,C5341638,CC1210KKX7R8BB226,YAGEO,0.596,2.384,22 uF 25 V X7R 1210; the 5V0/3V3 positions (16 V/10 V in the value) get the same part @@ -35,9 +35,9 @@ Item,Qty,References,Value,Footprint,LCSC,MPN,Manufacturer,Unit USD,Ext USD,Note 34,1,J5,BACKPLANE,Connector_PinHeader_2.54mm:PinHeader_1x08_P2.54mm_Vertical,,,,,,through-hole pin header: hand-solder (or pay for JLCPCB THT assembly) 35,1,J6,FAN,Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical,,,,,,through-hole pin header: hand-solder (or pay for JLCPCB THT assembly) 36,1,L1,10u MWSA1707S-100/XAL1350,labbench:L_1707_XAL1510,C5240401,MWSA1707S-100MT,Sunlord,1.68,1.68,16.5 A Isat / 10.5 A Irms; L_1707_XAL1510 superset land -37,1,L2,33u/1.2A,Inductor_SMD:L_1210_3225Metric,C223226,CBC3225T330KR,Taiyo Yuden,0.2475,0.247,"CHECK: value says 33u/1.2A but no 1210 33 uH is rated near 1.2 A; this is the strongest stocked one (0.5 A). Fine if the 5V0 load stays well under ~0.4 A, otherwise move to a bigger inductor footprint" -38,2,Q1 Q2,CSD18563Q5A,labbench:PowerFET_SON5x6_GDS,C179626,NTMFS5C670NLT1G,onsemi,0.49,0.98,"CHECK: stands in for CSD18563Q5A (C77239, out of stock 2026-09-27). 60 V, 6.1 mOhm, Qg 20 nC vs 5.7 mOhm / 15 nC; SO-8FL has the same S-S-S-G / drain-tab pinout as the TI Q5A land - confirm the pad overlay in the JLCPCB preview. Q3/Q4 dissipate about 0.6 W each at 10 A" -39,2,Q3 Q4,60V NFET,labbench:PowerFET_SON5x6_GDS,C179626,NTMFS5C670NLT1G,onsemi,0.49,0.98,"CHECK: stands in for CSD18563Q5A (C77239, out of stock 2026-09-27). 60 V, 6.1 mOhm, Qg 20 nC vs 5.7 mOhm / 15 nC; SO-8FL has the same S-S-S-G / drain-tab pinout as the TI Q5A land - confirm the pad overlay in the JLCPCB preview. Q3/Q4 dissipate about 0.6 W each at 10 A" +37,1,L2,33u/1.2A,Inductor_SMD:L_Changjiang_FNR5040S,C167973,FNR5040S330MT,cjiang (Changjiang Microelectronics),0.06,0.06,"5x5x4 mm shielded, KiCad L_Changjiang_FNR5040S land; Isat 1.30 A min covers the 33u/1.2A value. Any 5040-size 33 uH >=1.2 A part with the same 2.3 mm pad gap fits" +38,2,Q1 Q2,CSD18563Q5A,labbench:PowerFET_SON5x6_GDS,C179626,NTMFS5C670NLT1G,onsemi,0.49,0.98,"stands in for CSD18563Q5A (C77239, still out of stock 2026-10-06). 60 V, 6.1 mOhm, Qg 20 nC vs 5.7 mOhm / 15 nC; same S-S-S-G / drain-tab pinout. Overlay on the TI Q5A land checked against case 488AA: terminals within 0.14 mm of the TI part's (E 6.15 vs 6.00, L 0.575 vs 0.61, K 1.35 vs 1.10), 0.35 mm from the drain land edge vs 0.24 for the TI part. Q3/Q4 dissipate about 0.6 W each at 10 A" +39,2,Q3 Q4,60V NFET,labbench:PowerFET_SON5x6_GDS,C179626,NTMFS5C670NLT1G,onsemi,0.49,0.98,"stands in for CSD18563Q5A (C77239, still out of stock 2026-10-06). 60 V, 6.1 mOhm, Qg 20 nC vs 5.7 mOhm / 15 nC; same S-S-S-G / drain-tab pinout. Overlay on the TI Q5A land checked against case 488AA: terminals within 0.14 mm of the TI part's (E 6.15 vs 6.00, L 0.575 vs 0.61, K 1.35 vs 1.10), 0.35 mm from the drain land edge vs 0.24 for the TI part. Q3/Q4 dissipate about 0.6 W each at 10 A" 40,5,Q5 Q6 Q7 Q8 Q9,2N7002,Package_TO_SOT_SMD:SOT-23,C8545,2N7002,"Jiangsu Changjing Electronics Technology Co., Ltd.",0.0178,0.089, 41,1,R1,25.5K 0.1%,Resistor_SMD:R_0603_1608Metric,C861257,RT0603BRD0725K5L,YAGEO,0.0353,0.035,0.1 % 25 ppm thin film 42,1,R2,1.0K 0.1%,Resistor_SMD:R_0603_1608Metric,C110776,RT0603BRD071KL,YAGEO,0.0327,0.033,0.1 % 25 ppm thin film @@ -73,12 +73,12 @@ Item,Qty,References,Value,Footprint,LCSC,MPN,Manufacturer,Unit USD,Ext USD,Note 72,1,U2,OPA2333,Package_SO:VSSOP-8_3.0x3.0mm_P0.65mm,C19608,OPA2333AIDGKR,TI,1.14,1.14, 73,1,U3,LM5145RGYR,labbench:LM5145_RGY0020B,C485912,LM5145RGYR,TI,1.55,1.55, 74,1,U4,INA240A3,Package_SO:SOIC-8_3.9x4.9mm_P1.27mm,C2060584,INA240A3DR,TI,1.87,1.87, -75,1,U5,INA228,Package_SO:VSSOP-10_3x3mm_P0.5mm,C5214669,INA228AQDGSRQ1,TI,17.16,17.16,"automotive grade of INA228AIDGSR, same VSSOP-10 pinout and register map (no firmware change); the AIDGSR (C2887910) was still out of stock on 2026-09-28 - swap back if it returns, it is about a quarter of the price" -76,1,U6,LTC7004,Package_SO:MSOP-10-1EP_3x3mm_P0.5mm_EP1.68x1.88mm,C690105,LTC7004EMSE#PBF,ADI,5.77,5.77,thinnest stock in the BOM - order early (IMSE fallback) +75,1,U5,INA228,Package_SO:VSSOP-10_3x3mm_P0.5mm,C5214669,INA228AQDGSRQ1,TI,17.16,17.16,"automotive grade of INA228AIDGSR, same VSSOP-10 pinout and register map (no firmware change); the AIDGSR (C2887910) was still out of stock on 2026-09-28 - swap back if it returns, it is about a quarter of the price. Only 5 in stock on 2026-10-06: order early" +76,1,U6,LTC7004,Package_SO:MSOP-10-1EP_3x3mm_P0.5mm_EP1.68x1.88mm,C690105,LTC7004EMSE#PBF,ADI,11.62,11.62,thin stock (25 on 2026-10-06) - order early (IMSE fallback) 77,1,U7,TLV7011DCK,Package_TO_SOT_SMD:SOT-353_SC-70-5,C193688,TLV7011DCKR,TI,0.27,0.27,SC-70-5 (DCK) 78,1,U8,LMR36015AQRNXRQ1,labbench:LMR36015_RNX_VQFN-HR-12,C1850345,LMR36015ARNXR,TI,1.91,1.91,"symbol value says LMR36015AQRNXRQ1 (automotive); SOURCING picked the commercial ARNXR, same RNX package" 79,1,U9,NCP1117-3.3,Package_TO_SOT_SMD:SOT-223-3_TabPin2,C26537,NCP1117ST33T3G,onsemi,0.21,0.21, 80,1,U10,STM32G431CBT6,Package_QFP:LQFP-48_7x7mm_P0.5mm,C529355,STM32G431CBT6,ST,2.85,2.85, 81,1,U11,TCAN1042HGV,Package_SO:SOIC-8_3.9x4.9mm_P1.27mm,C485806,TCAN1042VDRQ1,TI,0.57,0.57,"symbol value says TCAN1042HGV; SOURCING picked the V (VIO) variant, same SOIC-8 pinout" 82,1,Y1,8MHz,Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm,C403948,TAXM8M4RFDCET2T,Yajingxin,0.147,0.147,"8 MHz 3225, CL = 12 pF (load caps 18 p); replaces C400090, which is the CL = 10 pF version" -,136,,,,,,,,50.24,"127/136 placements have an LCSC number; total covers those only (qty-1, SOURCING.md 2026-07-18)" +,136,,,,,,,,55.9,"127/136 placements have an LCSC number; total covers those only (qty-1, SOURCING.md 2026-07-18)" diff --git a/hardware/phase1-module/bom/phase1-module-cpl.csv b/hardware/phase1-module/bom/phase1-module-cpl.csv index 47343d4..ac131ef 100644 --- a/hardware/phase1-module/bom/phase1-module-cpl.csv +++ b/hardware/phase1-module/bom/phase1-module-cpl.csv @@ -66,7 +66,7 @@ J4,116.6500mm,-51.8000mm,Top,90 J5,116.5000mm,-81.5900mm,Top,0 J6,30.8700mm,-94.0000mm,Top,90 L1,80.5700mm,-35.0000mm,Top,0 -L2,33.0000mm,-61.0000mm,Top,0 +L2,32.6000mm,-61.2500mm,Top,0 Q1,67.5000mm,-30.0000mm,Top,0 Q2,67.5000mm,-43.0000mm,Top,180 Q3,115.5000mm,-34.0000mm,Top,270 diff --git a/hardware/phase1-module/bom/phase1-module-jlcpcb.csv b/hardware/phase1-module/bom/phase1-module-jlcpcb.csv index 8e16697..8601c47 100644 --- a/hardware/phase1-module/bom/phase1-module-jlcpcb.csv +++ b/hardware/phase1-module/bom/phase1-module-jlcpcb.csv @@ -5,7 +5,7 @@ Comment,Designator,Footprint,LCSC Part # 150n,C4,C_0603_1608Metric,C513735 47n,C18,C_0603_1608Metric,C1622 15p,C19,C_0603_1608Metric,C1644 -22u/50V X7R,"C20,C75,C76,C77",C_1210_3225Metric,C77102 +10u/50V X7R,"C20,C75,C76,C77",C_1210_3225Metric,C77102 220u/50V,C21,CP_Elec_10x10.5,C2887271 220u/25V poly,"C22,C78",CP_Elec_8x11.9,C46550471 22u/25V X7R,"C23,C79,C80,C81",C_1210_3225Metric,C5341638 @@ -34,7 +34,7 @@ OUTPUT,J4,"TerminalBlock_Phoenix_PT-1,5-2-5.0-H_1x02_P5.00mm_Horizontal", BACKPLANE,J5,PinHeader_1x08_P2.54mm_Vertical, FAN,J6,PinHeader_1x02_P2.54mm_Vertical, 10u MWSA1707S-100/XAL1350,L1,L_1707_XAL1510,C5240401 -33u/1.2A,L2,L_1210_3225Metric,C223226 +33u/1.2A,L2,L_Changjiang_FNR5040S,C167973 CSD18563Q5A,"Q1,Q2",PowerFET_SON5x6_GDS,C179626 60V NFET,"Q3,Q4",PowerFET_SON5x6_GDS,C179626 2N7002,"Q5,Q6,Q7,Q8,Q9",SOT-23,C8545 diff --git a/hardware/phase1-module/lib/PARTS-TO-DOWNLOAD.md b/hardware/phase1-module/lib/PARTS-TO-DOWNLOAD.md index 4147dc9..93dcffa 100644 --- a/hardware/phase1-module/lib/PARTS-TO-DOWNLOAD.md +++ b/hardware/phase1-module/lib/PARTS-TO-DOWNLOAD.md @@ -64,7 +64,7 @@ from the vetted vendor drops + one generated pattern). New/changed orderables: |---|---|---|---| | 4 | **CSD18563Q5A** (TI) | SON 5×6 → `labbench:PowerFET_SON5x6_GDS` (generated from SLPS444C §7.2; pads renumbered 1=G 2=D 3=S for the generic symbol) | Q1/Q2 half-bridge, Q3/Q4 output disconnect | | 1 | **XAL1350-103ME_** (Coilcraft; suffix B/C/D = packaging) | 13×13 flat-wire → official `L_Coilcraft_XAL1350-XXX` | L1 main inductor, 10 µH / Isat ≈ 18 A @ 30 % drop, DCR ≈ 8.7 mΩ (Coilcraft Doc373 selector — earlier "28 A" here was wrong; 18 A still clears the ~14 A peak at valley ILIM) | -| 4 | 22 µF 50 V X7R 1210 (e.g. Murata GRM32EC72A226KE05) | C_1210 | input bank C20/C75–C77 | +| 4 | 10 µF 50 V X7R 1210 (Murata GRM32ER71H106KA12L; 22 µF 50 V is not stocked) | C_1210 | input bank C20/C75–C77 | | 1 | 220 µF 50 V SMD electrolytic (e.g. Panasonic EEE-FK1H221AM, Ø10×10.2) | CP_Elec_10x10.5 | input bulk C21 | | 2 | 220 µF 25 V polymer (e.g. Panasonic 25SVPF220M OS-CON, Ø8×11.9) | CP_Elec_8x11.9 | output bulk C22/C78 | | 4 | 22 µF 25 V X7R 1210 | C_1210 | output bank C23/C79–C81 | diff --git a/hardware/phase1-module/phase1-module-fab.zip b/hardware/phase1-module/phase1-module-fab.zip index dcf9a30..8bc9346 100644 Binary files a/hardware/phase1-module/phase1-module-fab.zip and b/hardware/phase1-module/phase1-module-fab.zip differ diff --git a/hardware/phase1-module/phase1-module.kicad_pcb b/hardware/phase1-module/phase1-module.kicad_pcb index cfecd08..77461d3 100644 --- a/hardware/phase1-module/phase1-module.kicad_pcb +++ b/hardware/phase1-module/phase1-module.kicad_pcb @@ -745,6 +745,63 @@ ) ) + (footprint "Inductor_SMD:L_Changjiang_FNR5040S" (layer "F.Cu") + (tstamp 186118f2-3e37-4da6-bc07-c98eb9a9e609) + (at 32.6 61.25) + (descr "Inductor, Changjiang, FNR5040S, 5.0x5.0x4.0mm, https://datasheet.lcsc.com/lcsc/1806131217_cjiang-Changjiang-Microelectronics-Tech-FNR5040S3R3NT_C167960.pdf") + (tags "Inductor wirewound power shielded") + (attr smd) + (fp_text reference "L2" (at -3.949999 0) (layer "F.SilkS") + (effects (font (size 0.8 0.8) (thickness 0.12))) + (tstamp f7656ad3-6c7f-4a2d-b925-33612c2f295d) + ) + (fp_text value "33u/1.2A" (at 0 3.5) (layer "F.Fab") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp f82f320b-a61a-4171-8f7a-c3a564525541) + ) + (fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab") + (effects (font (size 0.5 0.5) (thickness 0.075))) + (tstamp cdf16f9c-5dda-4312-81ea-a9656baccb40) + ) + (fp_line (start -2.76 -2.76) (end -2.76 -2.36) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp a6583018-10f7-4292-a804-47ae5eade1ba)) + (fp_line (start -2.76 -2.76) (end 2.76 -2.76) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 37b6bb7d-cbaf-4afe-aa16-e0cf6e75a078)) + (fp_line (start -2.76 2.76) (end -2.76 2.36) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp a5c6b7e8-fde4-4e77-bf7f-f64a089a6266)) + (fp_line (start -2.76 2.76) (end 2.76 2.76) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 6ad1f1d3-6ddb-471c-9236-5be9040c97c6)) + (fp_line (start 2.76 -2.76) (end 2.76 -2.36) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 04ec3b76-252e-4512-b08c-111c226d9843)) + (fp_line (start 2.76 2.76) (end 2.76 2.36) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp c924bd36-1f82-4de4-a9b5-f046b3f3cf13)) + (fp_line (start -2.8 -2.75) (end -2.8 2.75) + (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 6220be7f-43dc-4f0e-9f56-1a6fbeefd85f)) + (fp_line (start -2.8 2.75) (end 2.8 2.75) + (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 58ffba08-4804-42b9-8ca1-a2991766f015)) + (fp_line (start 2.8 -2.75) (end -2.8 -2.75) + (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp f2ab1788-e695-406f-bbef-3df4ddd498cb)) + (fp_line (start 2.8 2.75) (end 2.8 -2.75) + (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp ed404f57-eec9-427a-a1f0-988df46ebcd7)) + (fp_line (start -2.5 -2.5) (end -2.5 2.5) + (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 5712f0f5-818c-4e88-9537-3819b537c1bd)) + (fp_line (start -2.5 2.5) (end 2.5 2.5) + (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 572dd027-cc54-4ec8-b66f-d3c75d3fd2ae)) + (fp_line (start 2.5 -2.5) (end -2.5 -2.5) + (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 5ae2a07f-0967-4f62-8b07-b9af20c18075)) + (fp_line (start 2.5 2.5) (end 2.5 -2.5) + (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 283d5761-5c45-4e9b-b0d5-26d591f0f121)) + (pad "1" smd rect (at -1.85 0) (size 1.4 4.2) (layers "F.Cu" "F.Paste" "F.Mask") + (net 76 "SW_AUX") (tstamp f50a7fdb-9da1-46a0-81a4-e6ebce30ed6d)) + (pad "2" smd rect (at 1.85 0) (size 1.4 4.2) (layers "F.Cu" "F.Paste" "F.Mask") + (net 2 "5V0") (tstamp 72c45c94-9cd6-4448-a429-b76082d6a6a0)) + (model "${KICAD7_3DMODEL_DIR}/Inductor_SMD.3dshapes/L_Changjiang_FNR5040S.wrl" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + (footprint "Capacitor_SMD:C_0603_1608Metric" (layer "F.Cu") (tstamp 19c80740-34c7-49f0-a757-b3bb4fb004ec) (at 96.7 75.8) @@ -1046,7 +1103,7 @@ (effects (font (size 0.8 0.8) (thickness 0.12))) (tstamp 264c37f6-50ca-4475-9476-00f4499cabee) ) - (fp_text value "22u/50V X7R" (at 0 2.3 -90) (layer "F.Fab") + (fp_text value "10u/50V X7R" (at 0 2.3 -90) (layer "F.Fab") (effects (font (size 1 1) (thickness 0.15))) (tstamp 2a6056c2-ce18-4a75-bd36-f0f904c4294a) ) @@ -1210,7 +1267,7 @@ (effects (font (size 0.8 0.8) (thickness 0.12))) (tstamp 9dd61a21-cae3-4c46-9ae1-496477ccc6c5) ) - (fp_text value "22u/50V X7R" (at 0 2.3 -90) (layer "F.Fab") + (fp_text value "10u/50V X7R" (at 0 2.3 -90) (layer "F.Fab") (effects (font (size 1 1) (thickness 0.15))) (tstamp 1c526b10-6f97-46ef-8b50-46159bc5e281) ) @@ -1737,55 +1794,6 @@ ) ) - (footprint "Inductor_SMD:L_1210_3225Metric" (layer "F.Cu") - (tstamp 3fd8929d-68fd-4ceb-aa22-6681eeabc6c7) - (at 33 61) - (descr "Inductor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator") - (tags "inductor") - (attr smd) - (fp_text reference "L2" (at 0 2.279999) (layer "F.SilkS") - (effects (font (size 0.8 0.8) (thickness 0.12))) - (tstamp 839705b7-d8fd-4b8b-ae11-a5dd1406073f) - ) - (fp_text value "33u/1.2A" (at 0 2.28) (layer "F.Fab") - (effects (font (size 1 1) (thickness 0.15))) - (tstamp 122938f8-7b30-4fed-8051-b5b478b2f191) - ) - (fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab") - (effects (font (size 0.8 0.8) (thickness 0.12))) - (tstamp 6b874bfa-78eb-4057-a000-be3a516ad978) - ) - (fp_line (start -0.602064 -1.36) (end 0.602064 -1.36) - (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 4be511c3-409b-4ab3-aec5-b0161f5bd244)) - (fp_line (start -0.602064 1.36) (end 0.602064 1.36) - (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp e539f520-f7f4-4362-bfea-9f6826f9a8bf)) - (fp_line (start -2.28 -1.58) (end 2.28 -1.58) - (stroke (width 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-1.6 1.25) - (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp bbb2373f-c73b-4b24-a713-15d557a3bd67)) - (pad "1" smd roundrect (at -1.4 0) (size 1.25 2.65) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.2) - (net 76 "SW_AUX") (tstamp c35b4741-f284-4e84-93e5-fc06342620b5)) - (pad "2" smd roundrect (at 1.4 0) (size 1.25 2.65) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.2) - (net 2 "5V0") (tstamp e003a6bc-5435-4a62-9a24-3580595936a6)) - (model "${KICAD6_3DMODEL_DIR}/Inductor_SMD.3dshapes/L_1210_3225Metric.wrl" - (offset (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) - ) - ) - (footprint "Capacitor_SMD:C_0603_1608Metric" (layer "F.Cu") (tstamp 3ff22a0b-5407-4ad7-b639-190e44597db8) (at 60.2 64) @@ -3159,7 +3167,7 @@ (effects (font (size 0.8 0.8) (thickness 0.12))) (tstamp 8ad954fb-18e5-4742-9dac-1ccbf10c6976) ) - (fp_text value "22u/50V X7R" (at 0 2.3 -90) (layer "F.Fab") + (fp_text value "10u/50V X7R" (at 0 2.3 -90) (layer "F.Fab") (effects (font (size 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81.492345) (xy 86.432819 81.492344) @@ -39451,13 +39432,9 @@ (xy 93.138181 67.552563) (xy 93.171666 67.613886) (xy 93.1745 67.640244) - (xy 93.1745 81.060438) - (xy 93.157023 81.123911) - (xy 93.143964 81.145826) - (xy 93.143961 81.145834) - (xy 93.134417 81.191347) - (xy 93.101392 81.252919) - (xy 93.100738 81.253578) + (xy 93.1745 81.128455) + (xy 93.154815 81.195494) + (xy 93.138181 81.216136) (xy 92.711955 81.642361) (xy 92.692104 81.658483) (xy 92.681586 81.665356) diff --git a/hardware/phase1-module/power-stage.kicad_sch b/hardware/phase1-module/power-stage.kicad_sch index 2f8cd22..ed6ed24 100644 --- a/hardware/phase1-module/power-stage.kicad_sch +++ b/hardware/phase1-module/power-stage.kicad_sch @@ -1415,7 +1415,7 @@ (in_bom yes) (on_board yes) (dnp no) (uuid baa06fe0-2b9d-4d94-b3ce-79dab1937783) (property "Reference" "C20" (at 148.59 140.97 0) (effects (font (size 1.27 1.27)) (justify left))) - (property "Value" "22u/50V X7R" (at 148.59 143.51000000000002 0) (effects (font (size 1.27 1.27)) (justify left))) + (property "Value" "10u/50V X7R" (at 148.59 143.51000000000002 0) (effects (font (size 1.27 1.27)) (justify left))) (property "Footprint" "Capacitor_SMD:C_1210_3225Metric" (at 146.05 146.05 0) (effects (font (size 1.27 1.27)) hide)) (property "Datasheet" "~" (at 146.05 146.05 0) (effects (font (size 1.27 1.27)) hide)) (property "LCSC" "C77102" (at 146.05 146.05 0) (effects (font (size 1.27 1.27)) hide)) @@ -1429,7 +1429,7 @@ (in_bom yes) (on_board yes) (dnp no) (uuid 620e1db3-0310-40e3-a78f-1d5f4c50b82b) (property "Reference" "C75" (at 157.48 140.97 0) (effects (font (size 1.27 1.27)) (justify left))) - (property "Value" "22u/50V X7R" (at 157.48 143.51000000000002 0) (effects (font (size 1.27 1.27)) (justify left))) + (property "Value" "10u/50V X7R" (at 157.48 143.51000000000002 0) (effects (font (size 1.27 1.27)) (justify left))) (property "Footprint" "Capacitor_SMD:C_1210_3225Metric" (at 154.94 146.05 0) (effects (font (size 1.27 1.27)) hide)) (property "Datasheet" "~" (at 154.94 146.05 0) (effects (font (size 1.27 1.27)) hide)) (property "LCSC" "C77102" (at 154.94 146.05 0) (effects (font (size 1.27 1.27)) hide)) @@ -1443,7 +1443,7 @@ (in_bom yes) (on_board yes) (dnp no) (uuid 061ff472-012b-4ef3-bb4a-3a0fee77283a) (property "Reference" "C76" (at 166.37 140.97 0) (effects (font (size 1.27 1.27)) (justify left))) - (property "Value" "22u/50V X7R" (at 166.37 143.51000000000002 0) (effects (font (size 1.27 1.27)) (justify left))) + (property "Value" "10u/50V X7R" (at 166.37 143.51000000000002 0) (effects (font (size 1.27 1.27)) (justify left))) (property "Footprint" "Capacitor_SMD:C_1210_3225Metric" (at 163.83 146.05 0) (effects (font (size 1.27 1.27)) hide)) (property "Datasheet" "~" (at 163.83 146.05 0) (effects (font (size 1.27 1.27)) hide)) (property "LCSC" "C77102" (at 163.83 146.05 0) (effects (font (size 1.27 1.27)) hide)) @@ -1457,7 +1457,7 @@ (in_bom yes) (on_board yes) (dnp no) (uuid 1987a1e8-3c49-43e9-aa78-0843ab7f1b63) (property "Reference" "C77" (at 175.26 140.97 0) (effects (font (size 1.27 1.27)) (justify left))) - (property "Value" "22u/50V X7R" (at 175.26 143.51000000000002 0) (effects (font (size 1.27 1.27)) (justify left))) + (property "Value" "10u/50V X7R" (at 175.26 143.51000000000002 0) (effects (font (size 1.27 1.27)) (justify left))) (property "Footprint" "Capacitor_SMD:C_1210_3225Metric" (at 172.72 146.05 0) (effects (font (size 1.27 1.27)) hide)) (property "Datasheet" "~" (at 172.72 146.05 0) (effects (font (size 1.27 1.27)) hide)) (property "LCSC" "C77102" (at 172.72 146.05 0) (effects (font (size 1.27 1.27)) hide)) diff --git a/hardware/phase1-module/tools/README.md b/hardware/phase1-module/tools/README.md index ad96172..2312129 100644 --- a/hardware/phase1-module/tools/README.md +++ b/hardware/phase1-module/tools/README.md @@ -106,6 +106,24 @@ put the new positions in `gen_board.py` PLACEMENT (page mm minus the board for every footprint. `gen_board.py` still fails its own L1/C23 courtyard check, as before. +### Swapping a land on the routed board + +A footprint change (not just a move) is done with +`../../common/eco_swap_fp.py`, which replaces the footprint in place and +carries the reference, value, fields and pad nets over. The 2026-10-06 L2 +change (1210 -> 5 x 5 mm FNR5040S, same as the manager's in PR #16): + +```bash +python3 ../../common/eco_swap_fp.py ../phase1-module.kicad_pcb L2 \ + Inductor_SMD:L_Changjiang_FNR5040S 32.6 61.25 0 +``` + +then the SW_AUX diagonal was re-ended on the new pad 1 at (30.75, 60.15), +a 0.4 mm F.Cu 5V0 link was added from L2's via (35.5, 61) to C54's +(36.425, 61), and `finish_board --silk --planes`, `run_drc.py`, `--fab` and +`common/cpl.py` were rerun. The spot came from `eco_move.py --find L2`. +PLACEMENT in `gen_board.py` carries the new position. + Any schematic change: rerun the whole chain. Any placement change: rerun from gen_board. `EXPECTED_NETS` must be updated in the same commit as connectivity changes. diff --git a/hardware/phase1-module/tools/gen_board.py b/hardware/phase1-module/tools/gen_board.py index 8c8702b..b588565 100644 --- a/hardware/phase1-module/tools/gen_board.py +++ b/hardware/phase1-module/tools/gen_board.py @@ -59,7 +59,7 @@ def parse_netlist(path): "F1": (10.8, 6.5, 0), # pad1 VBUS (5,6.5) -> J1.1; pad2 (13,6.5) in pour "D5": (13.0, 16.9, 270), # SMBJ33A: pad1 VBUS_F band, pad2 PGND band "C21": (22.3, 16.9, 270), # 220u/50V straddle - "C20": (30.0, 16.9, 270), # 22u/50V bank straddle: pad1 up (VBUS_F) + "C20": (30.0, 16.9, 270), # 10u/50V bank straddle: pad1 up (VBUS_F) "C75": (34.0, 16.9, 270), "C76": (38.0, 16.9, 270), "C77": (42.0, 16.9, 270), @@ -142,7 +142,7 @@ def parse_netlist(path): "C51": (8.2, 35.6, 0), "C52": (17.0, 32.5, 270), # AUX_BOOT up / SW_AUX down "C53": (17.5, 37.5, 0), # AUX_VCC - "L2": (13.0, 41.0, 0), # pad1 SW_AUX, pad2 5V0 + "L2": (12.6, 41.25, 0), # FNR5040S 5x5: pad1 SW_AUX (west), pad2 5V0 (east) "C54": (19.0, 41.0, 0), "C55": (19.0, 44.6, 0), "R50": (14.0, 45.5, 0), diff --git a/hardware/phase1-module/tools/gen_phase1.py b/hardware/phase1-module/tools/gen_phase1.py index e8ec837..ce73669 100644 --- a/hardware/phase1-module/tools/gen_phase1.py +++ b/hardware/phase1-module/tools/gen_phase1.py @@ -189,7 +189,7 @@ def build_power_stage(): gl("VOUT_INT", l1, 2, shape="output") # input/output banks + preload + snubber (DNP); one component per physical cap CPOL = kg.get_symbol("Device", "C_Polarized") - cin = [cap(r, "22u/50V X7R", x, 146.05, fp="Capacitor_SMD:C_1210_3225Metric") + cin = [cap(r, "10u/50V X7R", x, 146.05, fp="Capacitor_SMD:C_1210_3225Metric") for r, x in (("C20", 146.05), ("C75", 154.94), ("C76", 163.83), ("C77", 172.72))] c21 = sh.add(kg.Placed(CPOL, "C21", "220u/50V", 181.61, 146.05, footprint="Capacitor_SMD:CP_Elec_10x10.5")) diff --git a/hardware/phase2-module/aux-rails.kicad_sch b/hardware/phase2-module/aux-rails.kicad_sch index a5612ca..e86698a 100644 --- a/hardware/phase2-module/aux-rails.kicad_sch +++ b/hardware/phase2-module/aux-rails.kicad_sch @@ -757,12 +757,21 @@ (property "Value" "33u/1.2A" (at 81.28 110.49 90) (effects (font (size 1.27 1.27))) ) - (property "Footprint" "Inductor_SMD:L_1210_3225Metric" (at 85.09 110.49 0) + (property "Footprint" "Inductor_SMD:L_Changjiang_FNR5040S" (at 85.09 110.49 0) (effects (font (size 1.27 1.27)) hide) ) (property "Datasheet" "~" (at 85.09 110.49 0) (effects (font (size 1.27 1.27)) hide) ) + (property "LCSC" "C167973" (at 85.09 110.49 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "MPN" "FNR5040S330MT" (at 85.09 110.49 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Manufacturer" "cjiang (Changjiang Microelectronics)" (at 85.09 110.49 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid ff8426d9-1fa8-4943-94fa-1c8cb294d78b)) (pin "2" (uuid b4647212-4917-4c53-822d-9418ee96df68)) (instances diff --git a/hardware/phase2-module/bom/phase2-module-bom.csv b/hardware/phase2-module/bom/phase2-module-bom.csv index bd917c6..248450d 100644 --- a/hardware/phase2-module/bom/phase2-module-bom.csv +++ b/hardware/phase2-module/bom/phase2-module-bom.csv @@ -34,7 +34,7 @@ Item,Qty,References,Value,Footprint,LCSC,MPN,Manufacturer,Unit USD,Ext USD,Note 33,1,J5,SLOT SIGNALS,Connector_PinHeader_2.54mm:PinHeader_1x08_P2.54mm_Vertical,,,,,, 34,1,J6,FAN,Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical,,,,,, 35,2,L1 L3,6.8u MWSA1707S/XAL1510,labbench:L_1707_XAL1510,C6238332,MWSA1707S-6R8MT,Sunlord,1.72,3.44,17 A Irms / 22 A Isat; L_1707_XAL1510 superset land (also takes the XAL1510 spares) -36,1,L2,33u/1.2A,Inductor_SMD:L_1210_3225Metric,,,,,, +36,1,L2,33u/1.2A,Inductor_SMD:L_Changjiang_FNR5040S,C167973,FNR5040S330MT,cjiang (Changjiang Microelectronics),0.06,0.06,"5x5x4 mm shielded, KiCad L_Changjiang_FNR5040S land; Isat 1.30 A min covers the 33u/1.2A value. Any 5040-size 33 uH >=1.2 A part with the same 2.3 mm pad gap fits" 37,8,Q1 Q2 Q3 Q4 Q10 Q11 Q12 Q13,CSD18540Q5B,labbench:PowerFET_SON5x6_GDS,C86513,CSD18540Q5B,TI,1.43,11.44,do not substitute clone power-stage FETs 38,5,Q5 Q6 Q7 Q8 Q9,2N7002,Package_TO_SOT_SMD:SOT-23,,,,,, 39,1,Q14,CSD19536KTT,Package_TO_SOT_SMD:TO-263-2,C2687963,CSD19536KTT,TI,4.94,4.94,"hot-swap pass FET, SOA-critical, thin stock - order early" @@ -74,10 +74,10 @@ Item,Qty,References,Value,Footprint,LCSC,MPN,Manufacturer,Unit USD,Ext USD,Note 73,2,RT1 RT2,10K B3950,Resistor_SMD:R_0603_1608Metric,,,,,, 74,1,U1,DAC80502DRXT,labbench:DAC80502_DRX_WSON-10,C1880990,DAC80502DRXR,TI,4.19,4.19,value says DRXT; R/T differ only in reel size 75,1,U2,OPA2333,Package_SO:VSSOP-8_3.0x3.0mm_P0.65mm,C19608,OPA2333AIDGKR,TI,1.14,1.14, -76,1,U3,LM5143RHAR,labbench:LM5143_RHA0040P,C5219258,LM5143QRHARQ1,TI,2.93,2.93,CHECK: symbol value says LM5143RHAR; SOURCING picked the cheaper Q1 variant (same VQFN-40) - confirm RHA0040P land vs the Q1 addendum +76,1,U3,LM5143RHAR,labbench:LM5143_RHA0040P,C5219258,LM5143QRHARQ1,TI,6.29,6.29,"symbol value says LM5143RHAR; this is the LM5143A-Q1 (TI ZHCSQC8, 2022). Same 40-pin map and the same land: RHA0040N vs RHA0040P is 6x6 body, 0.5 pitch, 0.25x0.6 pads at 5.8 span, EP 3.3 +-0.1 in both; the Q1 part only adds wettable flanks (checked 2026-10-06)" 77,1,U4,INA240A3,Package_SO:SOIC-8_3.9x4.9mm_P1.27mm,C2060584,INA240A3DR,TI,1.87,1.87, -78,1,U5,INA228,Package_SO:VSSOP-10_3x3mm_P0.5mm,C5214669,INA228AQDGSRQ1,TI,17.16,17.16,"automotive grade of INA228AIDGSR, same VSSOP-10 pinout and register map (no firmware change); the AIDGSR (C2887910) was still out of stock on 2026-09-28 - swap back if it returns, it is about a quarter of the price" -79,1,U6,LTC7004,Package_SO:MSOP-10-1EP_3x3mm_P0.5mm_EP1.68x1.88mm,C690105,LTC7004EMSE#PBF,ADI,5.77,5.77,thinnest stock in the BOM - order early (IMSE fallback) +78,1,U5,INA228,Package_SO:VSSOP-10_3x3mm_P0.5mm,C5214669,INA228AQDGSRQ1,TI,17.16,17.16,"automotive grade of INA228AIDGSR, same VSSOP-10 pinout and register map (no firmware change); the AIDGSR (C2887910) was still out of stock on 2026-09-28 - swap back if it returns, it is about a quarter of the price. Only 5 in stock on 2026-10-06: order early" +79,1,U6,LTC7004,Package_SO:MSOP-10-1EP_3x3mm_P0.5mm_EP1.68x1.88mm,C690105,LTC7004EMSE#PBF,ADI,11.62,11.62,thin stock (25 on 2026-10-06) - order early (IMSE fallback) 80,1,U7,TLV7011DCK,Package_TO_SOT_SMD:SOT-353_SC-70-5,C193688,TLV7011DCKR,TI,0.27,0.27,SC-70-5 (DCK) 81,1,U8,LMR36015AQRNXRQ1,labbench:LMR36015_RNX_VQFN-HR-12,C1850345,LMR36015ARNXR,TI,1.91,1.91,"symbol value says LMR36015AQRNXRQ1 (automotive); SOURCING picked the commercial ARNXR, same RNX package" 82,1,U9,NCP1117-3.3,Package_TO_SOT_SMD:SOT-223-3_TabPin2,C26537,NCP1117ST33T3G,onsemi,0.21,0.21, @@ -86,4 +86,4 @@ Item,Qty,References,Value,Footprint,LCSC,MPN,Manufacturer,Unit USD,Ext USD,Note 85,1,U12,LM5069MM-2,Package_SO:VSSOP-10_3x3mm_P0.5mm,C111822,LM5069MM-2/NOPB,TI,1.17,1.17, 86,1,U13,TS5A3166,Package_TO_SOT_SMD:SOT-23-5,C353035,TS5A3166DBVR,TI,0.28,0.28, 87,1,Y1,8MHz,Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm,C403948,TAXM8M4RFDCET2T,Yajingxin,0.147,0.147,"8 MHz 3225, CL = 12 pF (load caps 18 p); replaces C400090, which is the CL = 10 pF version" -,172,,,,,,,,69.9,"55/172 placements have an LCSC number; total covers those only (qty-1, SOURCING.md 2026-07-18)" +,172,,,,,,,,79.17,"56/172 placements have an LCSC number; total covers those only (qty-1, SOURCING.md 2026-07-18)" diff --git a/hardware/phase2-module/bom/phase2-module-cpl.csv b/hardware/phase2-module/bom/phase2-module-cpl.csv index 9fd887a..a49a894 100644 --- a/hardware/phase2-module/bom/phase2-module-cpl.csv +++ b/hardware/phase2-module/bom/phase2-module-cpl.csv @@ -82,7 +82,7 @@ J4,142.8500mm,-58.2000mm,Top,180 J5,22.5000mm,-88.8900mm,Top,0 J6,51.2700mm,-107.6000mm,Top,90 L1,105.5000mm,-34.0000mm,Top,0 -L2,67.0000mm,-56.8000mm,Top,270 +L2,68.4000mm,-57.4500mm,Top,270 L3,105.5000mm,-76.0000mm,Top,0 Q1,92.0000mm,-29.0000mm,Top,0 Q2,92.0000mm,-42.0000mm,Top,180 diff --git a/hardware/phase2-module/bom/phase2-module-jlcpcb.csv b/hardware/phase2-module/bom/phase2-module-jlcpcb.csv index ebdc091..30a5fac 100644 --- a/hardware/phase2-module/bom/phase2-module-jlcpcb.csv +++ b/hardware/phase2-module/bom/phase2-module-jlcpcb.csv @@ -33,7 +33,7 @@ XT60PW-M OUTPUT,J4,XT60PW-M,C98732 SLOT SIGNALS,J5,PinHeader_1x08_P2.54mm_Vertical, FAN,J6,PinHeader_1x02_P2.54mm_Vertical, 6.8u MWSA1707S/XAL1510,"L1,L3",L_1707_XAL1510,C6238332 -33u/1.2A,L2,L_1210_3225Metric, +33u/1.2A,L2,L_Changjiang_FNR5040S,C167973 CSD18540Q5B,"Q1,Q2,Q3,Q4,Q10,Q11,Q12,Q13",PowerFET_SON5x6_GDS,C86513 2N7002,"Q5,Q6,Q7,Q8,Q9",SOT-23, CSD19536KTT,Q14,TO-263-2,C2687963 diff --git a/hardware/phase2-module/drc-report.txt b/hardware/phase2-module/drc-report.txt index 69d021e..a7e97a8 100644 --- a/hardware/phase2-module/drc-report.txt +++ b/hardware/phase2-module/drc-report.txt @@ -1,11 +1,11 @@ ** Drc report for ../phase2-module.kicad_pcb ** -** Created on 2026-09-27 23:24:25 ** +** Created on 2026-10-06 07:17:22 ** ** Found 19 DRC violations ** [silk_overlap]: Silkscreen overlap Rule: board setup constraints silk; Severity: warning - @(110.5800 mm, 50.9700 mm): Reference 'R8' - @(110.5800 mm, 50.5200 mm): Reference 'C24' + @(131.1500 mm, 83.5400 mm): Line on F.Silkscreen + @(131.0600 mm, 74.6044 mm): Line on F.Silkscreen [silk_overlap]: Silkscreen overlap Rule: board setup constraints silk; Severity: warning @(92.5300 mm, 92.0300 mm): Reference 'C64' @@ -14,6 +14,10 @@ Rule: board setup constraints silk; Severity: warning @(95.1300 mm, 105.0700 mm): Reference 'R67' @(97.0000 mm, 105.0700 mm): Reference 'R68' +[silk_overlap]: Silkscreen overlap + Rule: board setup constraints silk; Severity: warning + @(110.5800 mm, 50.9700 mm): Reference 'R8' + @(110.5800 mm, 50.5200 mm): Reference 'C24' [silk_overlap]: Silkscreen overlap Rule: board setup constraints silk; Severity: warning @(102.3200 mm, 94.8200 mm): Reference 'R52' @@ -26,10 +30,6 @@ Rule: board setup constraints silk; Severity: warning @(103.9700 mm, 100.9000 mm): Reference 'C43' @(103.3700 mm, 100.7300 mm): Reference 'R64' -[silk_overlap]: Silkscreen overlap - Rule: board setup constraints silk; Severity: warning - @(131.1500 mm, 83.5400 mm): Line on F.Silkscreen - @(131.0600 mm, 74.6044 mm): Line on F.Silkscreen [silk_overlap]: Silkscreen overlap Rule: board setup constraints silk; Severity: warning @(60.2200 mm, 46.4000 mm): Reference 'R73' diff --git a/hardware/phase2-module/phase2-module-fab.zip b/hardware/phase2-module/phase2-module-fab.zip index f64cab7..2f55b26 100644 Binary files a/hardware/phase2-module/phase2-module-fab.zip and b/hardware/phase2-module/phase2-module-fab.zip differ diff --git a/hardware/phase2-module/phase2-module.kicad_pcb b/hardware/phase2-module/phase2-module.kicad_pcb index 1ab68ef..6b9d8ee 100644 --- a/hardware/phase2-module/phase2-module.kicad_pcb +++ b/hardware/phase2-module/phase2-module.kicad_pcb @@ -1317,6 +1317,63 @@ ) ) + (footprint "Inductor_SMD:L_Changjiang_FNR5040S" (layer "F.Cu") + (tstamp 18908867-e3b9-4f2e-bb48-cf039623540b) + (at 68.4 57.45 -90) + (descr "Inductor, Changjiang, FNR5040S, 5.0x5.0x4.0mm, https://datasheet.lcsc.com/lcsc/1806131217_cjiang-Changjiang-Microelectronics-Tech-FNR5040S3R3NT_C167960.pdf") + (tags "Inductor wirewound power shielded") + (attr smd) + (fp_text reference "L2" (at -3.499999 0 -90) (layer "F.SilkS") + (effects (font (size 0.8 0.8) (thickness 0.12))) + (tstamp 7d2e211b-a9d7-4d0a-8600-17b41185dc8a) + ) + (fp_text value "33u/1.2A" (at 0 3.5 -90) (layer "F.Fab") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 60f7b54b-5232-414a-bba5-23b4d370f741) + ) + (fp_text user "${REFERENCE}" (at 0 0 -90) (layer "F.Fab") + (effects (font (size 0.5 0.5) (thickness 0.075))) + (tstamp 5c533a56-0e7e-4c88-8deb-58bd48f7e317) + ) + (fp_line (start -2.76 -2.76) (end -2.76 -2.36) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp e8e43aab-c7b5-47e2-9a03-c92dd7d1a46d)) + (fp_line (start -2.76 -2.76) (end 2.76 -2.76) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 4f17aef9-d4d7-493c-88a2-fe092094a25f)) + (fp_line (start -2.76 2.76) (end -2.76 2.36) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 8123a148-5a16-44f3-8bf3-91afb2a70358)) + (fp_line (start -2.76 2.76) (end 2.76 2.76) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp dc80a332-40c0-454f-ab95-61d9ae79b5b7)) + (fp_line (start 2.76 -2.76) (end 2.76 -2.36) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 66d9b4e4-7d5b-4565-bb10-487a95e402a2)) + (fp_line (start 2.76 2.76) (end 2.76 2.36) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp f8faf4f0-56f2-4fa7-946d-b33d4c818857)) + (fp_line (start -2.8 -2.75) (end -2.8 2.75) + (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp d3491828-074e-47e3-9657-04e42bf23456)) + (fp_line (start -2.8 2.75) (end 2.8 2.75) + (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 0342680b-389d-44ce-a77a-3c5333729de3)) + (fp_line (start 2.8 -2.75) (end -2.8 -2.75) + (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp a30ba3e2-64d3-471e-9209-db26f6386255)) + (fp_line (start 2.8 2.75) (end 2.8 -2.75) + (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 53eca180-abcd-4665-bd97-1882ad9c5316)) + (fp_line (start -2.5 -2.5) (end -2.5 2.5) + (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp c2012128-3ba1-40ba-b590-5e06db32ae35)) + (fp_line (start -2.5 2.5) (end 2.5 2.5) + (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 2defbbf1-8a17-4e7f-8efc-a6ad2817d1e1)) + (fp_line (start 2.5 -2.5) (end -2.5 -2.5) + (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 62f78c24-ffd1-4131-b42f-c1f585115a06)) + (fp_line (start 2.5 2.5) (end 2.5 -2.5) + (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp ed25a943-ea4e-4d07-b2fd-cf0b2f323de9)) + (pad "1" smd rect (at -1.85 0 270) (size 1.4 4.2) (layers "F.Cu" "F.Paste" "F.Mask") + (net 93 "SW_AUX") (tstamp afaf195f-55e3-4317-8f3e-3667221edf9b)) + (pad "2" smd rect (at 1.85 0 270) (size 1.4 4.2) (layers "F.Cu" "F.Paste" "F.Mask") + (net 2 "5V0") (tstamp 683fe1e5-8464-45fa-af70-0d5de82431c5)) + (model "${KICAD7_3DMODEL_DIR}/Inductor_SMD.3dshapes/L_Changjiang_FNR5040S.wrl" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + (footprint "labbench:DAC80502_DRX_WSON-10" (layer "F.Cu") (tstamp 1fa6db94-a8ce-4c0d-bef5-0b8cd4251cf6) (at 54 96) @@ -3407,7 +3464,7 @@ (descr "Capacitor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator") (tags "capacitor") (attr smd) - (fp_text reference "C55" (at 0 -2.299999) (layer "F.SilkS") + (fp_text reference "C55" (at 0 2.299999) (layer "F.SilkS") (effects (font (size 0.8 0.8) (thickness 0.12))) (tstamp bac31ea4-77bc-47d9-8913-901fddb47a3f) ) @@ -4819,55 +4876,6 @@ (net 23 "DISC_SRC") (thermal_bridge_angle 45) (tstamp 8eb5d8be-6661-4136-ac09-9794a8d0adbc)) ) - (footprint "Inductor_SMD:L_1210_3225Metric" (layer "F.Cu") - (tstamp 81358c32-f920-4245-b071-dc0c8077eee0) - (at 67 56.8 -90) - (descr "Inductor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator") - (tags "inductor") - (attr smd) - (fp_text reference "L2" (at 2.979999 0 -90) (layer "F.SilkS") - (effects (font (size 0.8 0.8) (thickness 0.12))) - (tstamp fc029fd2-eef7-4130-bba3-63b40f9ddf87) - ) - (fp_text value "33u/1.2A" (at 0 2.28 -90) (layer "F.Fab") - (effects (font (size 1 1) (thickness 0.15))) - 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Strip one blocking net and re-route it after the stuck net instead. +## Engineering changes on the routed board + +The 2026-10-06 L2 change (1210 -> 5 x 5 mm FNR5040S, as on the manager) +was an ECO, not a re-route: + +```bash +python3 ../../common/eco_swap_fp.py ../phase2-module.kicad_pcb L2 \ + Inductor_SMD:L_Changjiang_FNR5040S 68.4 57.45 270 +``` + +The bigger pads swallow the old SW_AUX via (68.85, 55.4) and 5V0 via +(68.575, 59.175), so the two F.Cu stubs that reached them from the old pads +were deleted and a 0.3 mm 5V0 stub ties C55's via (68.6, 60.4) to pad 2. +Then zone refill, `finish_board --silk --planes`, `run_drc.py`, `--fab` and +`common/cpl.py`. `gen_board.py` PLACEMENT carries the new position. + ## Finishing ```bash diff --git a/hardware/phase2-module/tools/gen_board.py b/hardware/phase2-module/tools/gen_board.py index 2a190f9..92b4d38 100644 --- a/hardware/phase2-module/tools/gen_board.py +++ b/hardware/phase2-module/tools/gen_board.py @@ -141,7 +141,7 @@ def parse_netlist(path): "C50": (52.9, 24.0, 180), "C51": (52.9, 27.4, 180), "U8": (47.0, 31.0, 0), "C52": (43.5, 31.0, 270), "C53": (43.6, 35.0, 0), - "L2": (47.0, 36.8, 270), + "L2": (48.4, 37.45, 270), # FNR5040S 5x5: pad1 SW_AUX (north), pad2 5V0 "C54": (43.0, 42.0, 0), "C55": (51.0, 42.0, 0), "R50": (53.7, 38.6, 270), "R51": (53.7, 45.6, 270), "U9": (47.0, 50.0, 0), diff --git a/hardware/phase3-backplane/bom/phase3-backplane-bom.csv b/hardware/phase3-backplane/bom/phase3-backplane-bom.csv index a48b679..a2e34c8 100644 --- a/hardware/phase3-backplane/bom/phase3-backplane-bom.csv +++ b/hardware/phase3-backplane/bom/phase3-backplane-bom.csv @@ -26,5 +26,5 @@ Item,Qty,References,Value,Footprint,LCSC,MPN,Manufacturer,Unit USD,Ext USD,Note 25,1,R2,120R slot0-end,Resistor_SMD:R_0603_1608Metric,,,,,, 26,1,R3,120R slot7-end,Resistor_SMD:R_0603_1608Metric,,,,,, 27,2,RS1 RS2,0m5 3920,labbench:R3920_BVS,C466580,BVS-M-R0005,Isabellenhuette,0.6,1.2,2 in parallel = 0.25 mOhm; verify power rating on datasheet -28,1,U1,INA228,Package_SO:VSSOP-10_3x3mm_P0.5mm,C5214669,INA228AQDGSRQ1,TI,17.16,17.16,"automotive grade of INA228AIDGSR, same VSSOP-10 pinout and register map (no firmware change); the AIDGSR (C2887910) was still out of stock on 2026-09-28 - swap back if it returns, it is about a quarter of the price" +28,1,U1,INA228,Package_SO:VSSOP-10_3x3mm_P0.5mm,C5214669,INA228AQDGSRQ1,TI,17.16,17.16,"automotive grade of INA228AIDGSR, same VSSOP-10 pinout and register map (no firmware change); the AIDGSR (C2887910) was still out of stock on 2026-09-28 - swap back if it returns, it is about a quarter of the price. Only 5 in stock on 2026-10-06: order early" ,30,,,,,,,,24.47,"12/30 placements have an LCSC number; total covers those only (qty-1, SOURCING.md 2026-07-18)"