diff --git a/HANDOVER.md b/HANDOVER.md
index 532d2be..ef23157 100644
--- a/HANDOVER.md
+++ b/HANDOVER.md
@@ -1,19 +1,24 @@
 # Session Handover — Lab_Bench modular PSU
 
-Written 2026-07-16, updated 2026-07-26 for the next agent (or future session)
-continuing this project. Read this + README.md before touching anything.
-**Phase-2 PCB is routed (2026-09-27): 0 unconnected, 0 DRC errors, fab
-outputs generated** — see "Phase-2 PCB — resume point" below and
-`hardware/phase2-module/tools/README.md`. Manager firmware is done.
+Written 2026-07-16, last refreshed 2026-10-06 for the next agent (or future
+session) continuing this project. Read this + README.md before touching anything.
+**All four boards are routed with 0 unconnected and 0 DRC errors**, v0.1.0
+was released from `master` on 2026-09-29, and the manager L2 / backplane C2
+part change (PR #16) landed on `development` on 2026-10-06. What stands
+between the project and the first order is the owner's pick on the BOM
+`CHECK:` rows and the gates under "Immediate next steps".
 
 ## The user & working agreement
 
 - Hobbyist building a **multi-channel modular bench PSU**, learning along the
   way — explain the *why* of engineering decisions, not just the what.
-- **Git: ask per-commit, NEVER `git push`.** The user's global CLAUDE.md rule
-  (per-action commit approval) OVERRIDES the older "standing permission" line
-  that used to be here — do the work, then stop and ask before each
-  `git commit`. The user has been committing the PCB work themselves.
+- **Git: ask before committing, never push to `master`.** The user's global
+  CLAUDE.md rule (per-action commit approval) OVERRIDES the older "standing
+  permission" line that used to be here. Since 2026-09-27 all work goes to
+  the `development` branch through a feature branch and a pull request;
+  `master` only receives batched merges from `development` (it stays the
+  GitHub default branch). A major board redesign goes on its own branch,
+  and the prior design is saved as a branch first (e.g. `phase1-120x80`).
 - **The KiCad schematics are hand-owned now (since 2026-07-19).** The user
   hand-rearranged every `.kicad_sch` for readability (commits 7485036 /
   f9c5ff6 / b6402a7). **Never rerun the schematic generators** (gen_phase2.py
@@ -43,12 +48,10 @@ manager, CAN 2.0B @500k. Docs 01–07 are the spec; read 05 (build plan) first
 | Design docs 01–07 | complete (07 = module firmware, new) |
 | Phase-1 schematic | **complete, v1**: 7 generated sheets, 137 components, ~90 nets machine-verified; audited (kicad-happy + ngspice 38/40 pass) |
 | Footprints | all vetted; custom lib `labbench.pretty` (LM5145 RGY, LMR36015 RNX, DAC80502 no-EP WSON, PowerFET_SON5x6_GDS) |
-| PCB — Phase 1 | **100 × 80 mm, routed, 0 unconnected, 0 DRC errors** (2026-09-27, draft PR from `claude/phase1-100x80`; the 120 × 80 layout it replaces is kept on branch `phase1-120x80`). Re-placed from the netlist, so L1 now has the 17 mm MWSA1707S/XAL1510 superset land and U7 the SC-70-5 land the BOM orders (the 120 × 80 board still carried XAL1350 and SOT-23-5 lands: do not order it). Output bank tightened round the bigger L1; R30 Kelvin shunt, U4/U5 and their sense traces moved as one block with the same geometry; Q3/Q4, J4 and the LTC7004 stack down the right edge. Pipeline: pass-1 + `fanout.py` + Freerouting 1.9 + `finish_routes.py`; 1303 tracks / 353 vias. DRC = 11 silk *warnings*. Fab zip + CPL regenerated |
+| PCB — Phase 1 | **100 × 80 mm, routed, 0 unconnected, 0 DRC errors** (2026-09-27, PR #9, merged; the 120 × 80 layout it replaces is kept on branch `phase1-120x80`). Re-placed from the netlist, so L1 now has the 17 mm MWSA1707S/XAL1510 superset land and U7 the SC-70-5 land the BOM orders (the 120 × 80 board still carried XAL1350 and SOT-23-5 lands: do not order it). Output bank tightened round the bigger L1; R30 Kelvin shunt, U4/U5 and their sense traces moved as one block with the same geometry; Q3/Q4, J4 and the LTC7004 stack down the right edge. Pipeline: pass-1 + `fanout.py` + Freerouting 1.9 + `finish_routes.py`; 1303 tracks / 353 vias. DRC = 11 silk *warnings*. Fab zip + CPL regenerated. 2026-09-28 (PR #13): OVP_TRIP routed to U10 PB4 for the firmware 0.2 OVP latch |
 | PCB — Phase 3 backplane | **FAB-READY (2026-07-26, d9e1a7b)**: 0 DRC, 0 unconnected, silk 39/39 clean, no plane islands. Gerbers+drills in `fab/` (gitignored) via `python3 ../common/finish_board.py phase3-backplane.kicad_pcb`. Cross-checked: Edge_Cuts exactly 330.00×100.00 mm; drills 2×6.4 (M6 lugs), 16×2.8 (8 slots × 2 XT60 pins), 6×3.2 (M3), 86×1.0, 61×0.4. **Still gated on the XT60 polarity buzz-out before ordering** |
-| PCB — Phase 2 | **83 unconnected, 0 copper DRC, silk clean (2026-07-26, c1a86eb)** — see the resume section; finish by hand in KiCad. Older detail below: |
-| PCB — Phase 2 (history) | **(2026-07-25, 27fb2d1).** `gen_board.py` placement green (173 comps, all pour/courtyard/edge assertions pass, 130×90 4-layer); `route_board.py` pass-1 done (power pours, In2 heat patches, both phases' gate fan-outs, Kelvin pairs, disconnect trunk). DRC: **copper down to ~19 clearance + ~11 dangling/mask/hole in 3 known clusters** (see resume section); 243 unconnected = signal nets, autoroute not yet run. Found & fixed a real LM5143 land-pattern bug in the process (see load-bearing decisions) |
-| PCB — Phase 3 backplane | **COMPLETE pass-1 (2026-07-25)**: `phase3-backplane/tools/gen_board.py` (single-script: placement + 2oz bus pours + stitching + ALL signal routing) — **0 copper DRC, 0 unconnected**; only lib-bookkeeping (39) + 1 silk nick remain. 8 slots @30mm (XT60PW-F rot-90 mates the module pad-for-pad, socket y60..77.8 = module J5 1:1), M6 lugs -> RS1‖RS2 0.5mΩ Kelvin-sensed by INA228, nested PRESENT L-bus, CAN terminated past both end slots, E-stop chain threaded per docs. Netlist from `tools/wip/bp.net` (regenerate via kicad-cli) |
-| PCB — Phase 3 manager | **Routed, 0 unconnected, 0 DRC errors (2026-09-27, draft PR into `development` from `claude/route-manager-shxsg1`)**: placement reworked (15+ passives had been placed by stale refdes, far from their pins; U8 buck re-laid tight round its pinout; U11 turned so CAN faces J1; U12 in the USB path), PGND now poured on both layers (was F.Cu 3V3 / B.Cu PGND), USB + CAN pairs and buck power copper hand-drawn and locked (`route_critical.py`), rest Freerouting 1.9 + `finish_routes.py`, 283 PGND stitch vias. DRC = 5 warnings (4 silk, 1 U8 courtyard-override lib mismatch). Antenna keep-out copper-free. Pipeline: `phase3-manager/tools/README.md`. **ECO 2026-10-05:** L2 moved from the 1210 land (no stocked 33 µH above 0.5 A) to a 5×5 mm FNR5040S (FNR5040S330MT, Isat 1.3 A); C54/C55 turned 180° so 5V0 runs straight from L2; PRESENT1/4–7 re-routed round the bigger part with `finish_routes.py`. Still 0 unconnected, 0 DRC errors, 4 warnings |
+| PCB — Phase 2 | **130 × 90 mm, routed, 0 unconnected, 0 DRC errors (2026-09-27, PR #11, merged 2026-09-28)**; fab zip + CPL committed; pre-order review closed (see the resume section). The 83-unconnected history is kept below for its tooling notes |
+| PCB — Phase 3 manager | **Routed, 0 unconnected, 0 DRC errors (2026-09-27, merged into `development`)**: placement reworked (15+ passives had been placed by stale refdes, far from their pins; U8 buck re-laid tight round its pinout; U11 turned so CAN faces J1; U12 in the USB path), PGND now poured on both layers (was F.Cu 3V3 / B.Cu PGND), USB + CAN pairs and buck power copper hand-drawn and locked (`route_critical.py`), rest Freerouting 1.9 + `finish_routes.py`, 283 PGND stitch vias. DRC = 5 warnings (4 silk, 1 U8 courtyard-override lib mismatch). Antenna keep-out copper-free. Pipeline: `phase3-manager/tools/README.md`. **ECO 2026-10-05:** L2 moved from the 1210 land (no stocked 33 µH above 0.5 A) to a 5×5 mm FNR5040S (FNR5040S330MT, Isat 1.3 A); C54/C55 turned 180° so 5V0 runs straight from L2; PRESENT1/4–7 re-routed round the bigger part with `finish_routes.py`. Still 0 unconnected, 0 DRC errors, 4 warnings (PR #16, merged 2026-10-06; fab zip, BOM and CPL regenerated) |
 | Module firmware | v0.2 builds clean (7.1 KB): full peripheral binding + CAN dispatch around the host-tested `module_core`. 0.2 (2026-09-28) closes the two protection gaps from the bench-test review: OCP backup #2 (`lb_core_ocp_sample`: INA240 ADC or INA228 SOVL alert >110 % i_max for >5 ms) and OVP latch #4 (OVP_TRIP routed to PB4 on the 100 × 80 board; EXTI4 kills EN, tick latches). Untested on silicon (no board yet) |
 | Host tests | `cd firmware/tests && make test` — must stay green. **5 suites now**: can, core, manager, scpi, ui |
 | Manager firmware | **v0.2 COMPLETE (2026-07-25, commit 174595e)**: `scpi_core` + `ui_core` join `manager_core` as host-tested cores; ESP-IDF shell fully written (display/encoder/USB-SCPI/app_main). **First compile 2026-09-27: builds clean on IDF v5.3.2** (355 KB image, two build fixes). Untested on silicon. See docs/10 |
@@ -56,7 +59,7 @@ manager, CAN 2.0B @500k. Docs 01–07 are the spec; read 05 (build plan) first
 | Phase-2 schematic | **complete, v1, audited (2026-07-17)**: 8 sheets, 171 components, 116 nets machine-verified; kicad-happy audit triaged (all errors = known false-positive classes or the deferred MPN pass — same baseline as Phase-1); ngspice **45/47 pass** (crystal warn + bridge skip = same model limitations as Phase-1's 38/40) |
 | Phase-3 schematics | **complete, v1, audited (2026-07-17)**: backplane (29 comps, EXACT net assertions) + manager (80 comps) — audit caught a real omission (manager I²C pull-ups specified in docs/09 but not drawn; fixed, PR-001 clear). SPICE: manager 16/16, backplane 3/3. Backplane "missing I²C pull-up" findings = by design (manager owns them) |
 | Manager firmware — detail | manager_core v0.1 (2026-07-18) + **scpi_core & ui_core v0.2 (2026-07-25)**, all host-tested. Shell modules: `display.c` (esp_lcd ILI9341, 8×16 VGA font generated by `idf/tools/gen_font.py` from the system PSF — never hand-typed), `encoder.c` (PCNT ×4 quadrature, push/hold), `scpi_usb.c` (TinyUSB CDC), `app_main.c` (one mutex over the three cores; TCA9535 keys; backplane INA228 meter). Managed components in `main/idf_component.yml`. **Bring-up knobs (expect wrong on first light-up): display rotation + RGB565 byte order, then encoder direction** — docs/10 §Bring-up 6–7 |
-| Ordering/BOM | **China-first sourcing pass done (hardware/SOURCING.md, 2026-07-18)**: LCSC prices/stock verified for all phases (~$135 parts for the Phase-3 build, ~$300–380 all-in); inductor + slot-connector decisions taken (Sunlord + 3.75 mΩ shunts APPLIED to gen_phase2; XT60PW slots queued); order-early list: LTC7004 (5 pcs), CSD19536KTT (12 pcs). MPN-properties pass into symbols still pending |
+| Ordering/BOM | **China-first sourcing pass done (hardware/SOURCING.md, 2026-07-18)**: LCSC prices/stock verified for all phases (~$135 parts for the Phase-3 build, ~$300–380 all-in); inductor + slot-connector decisions taken (Sunlord + 3.75 mΩ shunts APPLIED to gen_phase2; XT60PW slots queued); order-early list: LTC7004 (5 pcs), CSD19536KTT (12 pcs). MPN/LCSC pass done (`common/bom.py`, see next steps). Picks since: ENC1/F1/BZ1 (PR #10), phase-2 C15/16/36/37 EEHZA1V221P and U5 INA228AQDGSRQ1 (PR #11), manager J3 USB4105-GF-A (C3020560, PR #12), manager L2 FNR5040S330MT (C167973) and backplane C2 Nichicon UCX1H471MNS1MS (C462700, fallback EEEFK1H471AM C178551) (PR #16) |
 
 ## Phase-2 PCB — resume point (routed, 2026-09-27)
 
@@ -75,7 +78,8 @@ heat. Expect NTC_FET to lag and read low: log it against a thermocouple
 on Q2 at full load and set the derate/OTP thresholds from that offset.
 
 Everything below in this section is the 2026-07-26 history (83 open
-connections), kept for its Freerouting and PS-002 notes. The old recipe:
+connections, since finished), kept for its Freerouting and PS-002 notes.
+The old recipe:
 
 ```bash
 cd hardware/phase2-module/tools
@@ -87,7 +91,7 @@ python3 check_planes.py           # PS-002 island advisory
 python3 run_drc.py                # -> ../drc-report.txt
 ```
 
-### What is left: finish 83 connections by hand in KiCad
+### History: the 83 connections left on 2026-07-26 (all routed since)
 
 This is the honest recommendation, not a fallback. A grid maze router
 cannot finish fine-pitch escapes; KiCad's interactive push-and-shove can,
@@ -118,9 +122,11 @@ verify the spot is on the right side of SEAM 67.3 (a via on the wrong
 side shorts AGND to PGND), then rerun the checker. Current advisory: 6
 islands, all electrically connected — quality, not a break.
 
-### Freerouting: ruled out, with evidence
+### Freerouting: the 2026-07 failure notes
 
-Do not spend another session on it without reading this.
+Superseded: Freerouting 1.9 with a zone-free DSN and `-oit` finished the
+board on 2026-09-27 (`tools/README.md`). The notes below explain why the
+plugin route and 2.x still fail.
 
 - **With zones** (what the KiCad Freerouting *plugin* exports):
   `java.lang.StackOverflowError` in `PolylineTrace.combine`. Both v1.9
@@ -211,28 +217,37 @@ Notable route_board facts a future session needs:
 
 ## Immediate next steps (agreed order)
 
-1. **Phase-2 board — routed (2026-09-27).** Review the items listed in the
-   resume section before ordering.
-2. **Phase-3 manager board — routed (2026-09-27).** Review before ordering:
-   J3 is the GCT USB4105-GF-A (C3020560, picked 2026-09-28 to match the
-   routed land; JLCPCB assembly stock, backup -120 C5184243); 13 nets cross under the USB pair on B.Cu (fine at
-   full speed); the 0.2 mm drilling gate below still applies.
-3. **Order files** — the MPN/LCSC pass is done for every part SOURCING.md
-   verified: `python3 common/bom.py` (from `hardware/`) writes hidden
+1. **Owner picks the five BOM `CHECK:` rows** (state 2026-10-06; the
+   notes in the BOM CSVs say what each one needs):
+   - Phase-1 C20/C75–C77: no 22 µF 50 V 1210 stocked, 10 µF 50 V fitted
+     (input ceramic drops from 88 to 40 µF; C21 is the bulk).
+   - Phase-1 L2: 33 µH on a 1210 land, the strongest stocked part is 0.5 A
+     against a 1.2 A value. Fine only if 5V0 stays well under ~0.4 A.
+   - Phase-1 Q1/Q2 and Q3/Q4: NTMFS5C670NLT1G stands in for the
+     out-of-stock CSD18563Q5A (same S-S-S-G / tab pinout); confirm the pad
+     overlay in the JLCPCB preview.
+   - Phase-2 U3: symbol says LM5143RHAR, the BOM orders the cheaper
+     LM5143QRHARQ1; confirm the RHA0040P land against the Q1 addendum.
+2. **Open: Phase-1 and Phase-2 L2 still sit on 1210 lands** (phase-2 L2
+   has no LCSC number yet). The manager had the same problem and was fixed
+   by moving to the 5 × 5 mm FNR5040S land as an ECO (PR #16); the same
+   change was offered for phase-1/2 and waits on the owner's call.
+3. **Order files**: `python3 common/bom.py` (from `hardware/`) writes hidden
    LCSC/MPN/Manufacturer properties into the schematics (surgical, additive
-   only) and emits `<board>/bom/*-bom.csv` + `*-jlcpcb.csv`. The part table
-   is `common/lcsc_parts.py`; `--check` fails if anything is stale. Still
-   open: generic R/C/jellybean/header numbers, and the `CHECK:` rows in the
-   BOMs (footprint/variant mismatches vs SOURCING.md).
-4. **Phase-1 board** — shrunk to 100 × 80 mm and re-routed (0
-   unconnected, 0 DRC errors, 2026-09-27) with the BOM's L1 and U7 lands;
-   the 120 × 80 version (wrong L1/U7 lands) is on branch `phase1-120x80`.
-   Earlier review items still hold: C28 sits on U3.20, the VBUS divider
-   (R60/R61/C62) sits by U10.14, and every part offset is in `gen_board.py`
-   PLACEMENT. The VOUT_INT FB sense run (52 mm, tapped at L1.2) keeps
-   5.5 mm or more from SW copper on every layer, enforced by
-   `tools/fb_reroute.py` after routing. Next: owner picks the BOM `CHECK:` parts,
-   then order.
+   only) and emits `<board>/bom/*-bom.csv` + `*-jlcpcb.csv`;
+   `common/cpl.py` writes the placement files. The part table is
+   `common/lcsc_parts.py`; `--check` fails if anything is stale. Still
+   open: generic R/C/jellybean/header numbers. The manager and backplane
+   order files bundled with the v0.1.0 release predate PR #16: regenerate
+   them from `development` before ordering those two boards.
+4. Review notes that still hold at order time: manager J3 is the GCT
+   USB4105-GF-A (C3020560; JLCPCB assembly stock, backup -120 C5184243);
+   13 manager nets cross under the USB pair on B.Cu (fine at full speed).
+   Phase-1: C28 sits on U3.20, the VBUS divider (R60/R61/C62) by U10.14,
+   every part offset is in `gen_board.py` PLACEMENT, and the VOUT_INT FB
+   sense run keeps 5.5 mm or more from SW copper (`tools/fb_reroute.py`).
+   Phase-2 bring-up: calibrate NTC_FET against a thermocouple (resume
+   section).
 
 **Gates before ordering ANY board — including the fab-ready backplane:**
 
@@ -250,13 +265,6 @@ Notable route_board facts a future session needs:
   "FB divider too low-Z" is the injection scheme working as designed; RS-001
   set identical to the audited Phase-1 baseline.
 
-(This section used to carry three orphaned list items — "backplane + manager
-schematics", "manager firmware", "batch PCB pass for phase-1" — left behind
-by an earlier edit of the next-steps list above. All three were either
-complete or superseded, and one repeated the stale "phase-1 has 33
-unconnected" figure. Removed 2026-07-26; the live list is the numbered one
-above.)
-
 ## Shared layout tooling (hardware/common, 2026-07-26)
 
 Board-agnostic — use these instead of writing per-phase copies:
@@ -395,9 +403,9 @@ that the average is servo'd but ripple is skip-mode coarse.
   zone-free DSN, `-oit` bounds the optimizer; see tools/README.md). The
   older failure notes: the KiCad plugin hits the same StackOverflowError. On phase-1 it
   works headless as **1.9.0** under `xvfb-run` with `-Xss64m` (2.x's CLI
-  never finished); see phase1-module/tools/README.md. phase-2's
-  `import_ses.py` is broken (KiCad 7 `ImportSpecctraSES` takes no board);
-  phase-1's has a working SES parser to port.
+  never finished); see phase1-module/tools/README.md. both
+  boards' `import_ses.py` now use their own SES parser (KiCad 7's
+  `ImportSpecctraSES` takes no board, so it cannot run headless).
 - Phase-1 `autoroute.py` is superseded by fanout.py + Freerouting +
   finish_routes.py (the board is routed); kept for reference.
 - Phase-1/2 DRC noise is now **silk only** (9 and 11 warnings, cosmetic). The
diff --git a/README.md b/README.md
index 37d76f5..26840db 100644
--- a/README.md
+++ b/README.md
@@ -65,20 +65,21 @@ firmware/
   tools/lbcan.py              Bench helper: build cansend frames, decode candump
 ```
 
-## Status (2026-09-27)
+## Status (2026-10-06)
 
-Nothing has run on silicon yet; the first board to be built is the Phase-1 module.
+Nothing has run on silicon yet; the first board to be built is the Phase-1
+module. v0.1.0 was released from `master` on 2026-09-29.
 
 | Area | State |
 |---|---|
 | Design docs | Complete: 01–10, plus the build guide (11) and Phase-1 bench test procedure (12) |
-| Phase-1 module (150 W) | Schematic verified and audited; **board routed, 0 unconnected, 0 DRC errors**, fab zip committed. Layout review fixes in PR #5. Next: settle the open BOM items (Q3/Q4 part, R30 shunt, the BOM `CHECK:` rows), then order and run [docs/12](docs/12-phase1-bench-tests.md) |
-| Phase-2 module (600 W) | Schematic verified and audited; board placed and pass-1 routed, **83 connections left** to finish by hand in KiCad |
-| Phase-3 backplane | Board fab-ready; gated on the XT60 polarity buzz-out ([MECHANICAL.md](hardware/MECHANICAL.md)) |
-| Phase-3 manager | Schematic verified; board placed, signal routing not started |
-| Module firmware | v0.1 builds (~6 KB, bare-metal STM32G431); control core host-tested |
+| Phase-1 module (150 W) | 100 × 80 mm, **routed, 0 unconnected, 0 DRC errors**, fab zip and CPL committed. OVP_TRIP routed to the MCU (PB4) for the firmware 0.2 OVP latch. Next: the owner picks the four Phase-1 BOM `CHECK:` rows, then order and run [docs/12](docs/12-phase1-bench-tests.md). The older 120 × 80 layout on branch `phase1-120x80` has wrong L1/U7 lands: do not order it |
+| Phase-2 module (600 W) | 130 × 90 mm, **routed, 0 unconnected, 0 DRC errors**, fab zip and CPL committed; pre-order review closed (HANDOVER) |
+| Phase-3 backplane | 330 × 100 mm, fab-ready; gated on the XT60 polarity buzz-out ([MECHANICAL.md](hardware/MECHANICAL.md)) |
+| Phase-3 manager | 100 × 80 mm, **routed, 0 unconnected, 0 DRC errors**; L2 moved to a 5 × 5 mm land (2026-10-05) |
+| Module firmware | v0.2 builds (~7 KB, bare-metal STM32G431) with the OCP backup and OVP latch; control core host-tested |
 | Manager firmware | v0.2 builds on ESP-IDF 5.3.2; manager, SCPI and UI cores host-tested |
-| BOM / sourcing | LCSC numbers in the schematics and per-board BOM CSVs (`hardware/common/bom.py`); five `CHECK:` part mismatches await a pick; generic R/C parts not yet numbered |
+| BOM / sourcing | LCSC numbers in the schematics and per-board BOM and CPL files (`hardware/common/bom.py`); five `CHECK:` rows await the owner's pick (four Phase-1, one Phase-2); generic R/C parts not yet numbered |
 | CI | GitHub Actions: host tests, module and manager firmware builds on every PR |
 
 Complete Phase-1 build (parts, five PCBs, stencil, shipping) ≈ US$100–125.
diff --git a/docs/09-phase3-circuit-design.md b/docs/09-phase3-circuit-design.md
index aa731cb..267b2a0 100644
--- a/docs/09-phase3-circuit-design.md
+++ b/docs/09-phase3-circuit-design.md
@@ -174,19 +174,22 @@ header (generic 1×14).
 | MCU module | ESP32-S3-WROOM-1-N8R2 | quad PSRAM keeps IO35–37 (§3) |
 | I/O expander | TCA9535PWR (TSSOP-24) | 16 ch: PRESENT + keys |
 | USB ESD | TPD2E001DRLR | SOT-5X3 |
-| USB-C | 16-pin USB2.0 receptacle (GCT USB4105-class) | verify at sourcing |
-| Bus shunt | 250 µΩ ±1 % ≥8 W bolt/bar | WSBS8518-class, verify at sourcing |
+| USB-C | GCT USB4105-GF-A (C3020560) | picked 2026-09-28 to match the routed land; backup USB4105-GF-A-120 (C5184243) |
+| Bus shunt | 2 × BVS-M-R0005 (0.5 mΩ 3920, C466580) in parallel = 250 µΩ | chosen at sourcing (hardware/SOURCING.md); verify the power rating on the datasheet |
+| Backplane bulk C2 | Nichicon UCX1H471MNS1MS 470 µF 50 V SMD (C462700) | picked 2026-10-05, fits the CP_Elec_16x17.5 land; fallback Panasonic EEEFK1H471AM (C178551) |
+| Manager aux-buck L2 | cjiang FNR5040S330MT 33 µH (C167973) | 2026-10-05: 5 × 5 mm land, Isat 1.30 A; no stocked 1210 33 µH is rated above 0.5 A |
 | Display | 2.8" ILI9341+XPT2046 SPI module | off-the-shelf, header-mounted |
-| Encoder | EC11 w/ switch | panel part |
+| Encoder | Alps EC11E18244A5 (C255515) | EC11 with switch, panel part |
 | E-stop | NC mushroom switch (panel) | + shipped bench jumper |
 | P-FET | SOT-23 PMOS (AO3401A-class) | backlight switch, verify at sourcing |
 | Everything else | Phase-1/2 BOM carries over | |
 
 ## 6. Open items → resolve at capture / bring-up
 
-1. Backplane slot connector family — decided at the batch PCB pass
-   together with the module edge (docs/08 §12); schematic uses the same
-   generic 1×04 + 1×08 pair per slot.
+1. ~~Backplane slot connector family~~ — resolved at sourcing
+   (2026-07-18): Amass XT60PW-F per slot (XT60PW-M on the module) plus the
+   2.54 mm signal row. The XT60 polarity buzz-out (MECHANICAL.md) still
+   gates the backplane order.
 2. Encoder RC values + TCA9535 key debounce (firmware) **(bench)**.
 3. NCP1117 thermal under Wi-Fi soak **(bench)**, escape hatches in §3.
 4. Display module VCC jumper convention varies by vendor — confirm the
diff --git a/docs/11-build-guide.md b/docs/11-build-guide.md
index 40236a5..99a2ca6 100644
--- a/docs/11-build-guide.md
+++ b/docs/11-build-guide.md
@@ -6,8 +6,8 @@ it up the first time without letting the smoke out. When the board passes the
 first power-up in §7, [docs/12-phase1-bench-tests.md](12-phase1-bench-tests.md)
 takes over and checks that it actually meets the spec.
 
-> **Read this first — honest status (2026-09-27).** Nothing in this repository
-> has run on real silicon yet. The Phase-1 board is routed and DRC-clean, the
+> **Read this first — honest status (2026-10-06).** Nothing in this repository
+> has run on real silicon yet. All four boards are routed and DRC-clean, the
 > firmware builds and passes its host tests in CI, but the first board has not
 > been built. You would be building alongside the project owner, not after a
 > proven design. Expect to debug; the bench-test doc is written with that in
@@ -17,10 +17,10 @@ takes over and checks that it actually meets the spec.
 
 | Board | What it is | Can you order it? |
 |---|---|---|
-| **Phase-1 module** (`hardware/phase1-module/`) | Single 150 W channel: 24 V in, 0–20 V / 0–8 A out, CAN controlled | **Yes, once PR #5 is merged** (layout review fixes, regenerated fab zip) and the parts in §3.3 are settled |
-| Phase-2 module (`hardware/phase2-module/`) | 600 W channel, 0–28 V / 0–30 A, hot-swap input | No. 83 connections are still unrouted |
+| **Phase-1 module** (`hardware/phase1-module/`) | Single 150 W channel: 24 V in, 0–20 V / 0–8 A out, CAN controlled | **Yes, once the parts in §3.3 are settled.** Order the 100 × 80 board on `development`/`master`; the 120 × 80 layout on branch `phase1-120x80` has wrong L1/U7 lands |
+| Phase-2 module (`hardware/phase2-module/`) | 600 W channel, 0–28 V / 0–30 A, hot-swap input | Routed and fab-ready (2026-09-27). Wait for Phase-1 to pass its bench tests (docs/05 exit criteria) and settle the U3 `CHECK:` row |
 | Phase-3 backplane (`hardware/phase3-backplane/`) | 8-slot bus with CAN, E-stop and bus metering | Fab-ready, but gated on the XT60 polarity check and only useful with Phase-2 modules and a manager |
-| Phase-3 manager (`hardware/phase3-manager/`) | ESP32-S3 with display, encoder, USB SCPI | No. Placement is done, signal routing is not |
+| Phase-3 manager (`hardware/phase3-manager/`) | ESP32-S3 with display, encoder, USB SCPI | Routed and fab-ready. Confirm the fab quotes 0.2 mm drilling on 2 layers; regenerate the order files if yours predate 2026-10-06 (L2 changed) |
 
 So today this guide is about the **Phase-1 module**. It is the "learning
 board": every risky part of the design (analog CV/CC loops, sensing,
@@ -29,7 +29,7 @@ cheap. §9 says what changes for the later boards.
 
 ## 2. Skills and tools
 
-The board is 4-layer, 120 × 80 mm, almost all SMD, and hand-assembled. The
+The board is 4-layer, 100 × 80 mm, almost all SMD, and hand-assembled. The
 hard parts are small leadless packages:
 
 | Part | Package | Why it is hard |
@@ -71,7 +71,7 @@ file. Upload the zip as is.
 | Setting | Value |
 |---|---|
 | Layers | 4 |
-| Size | 120 × 80 mm |
+| Size | 100 × 80 mm |
 | Thickness | 1.6 mm |
 | Copper | 1 oz outer (JLCPCB standard stackup `JLC04161H-7628` is what the design assumes) |
 | Stencil | Yes, top side |
@@ -126,9 +126,11 @@ tolerance matters in a few places:
 
 | Item | What to decide |
 |---|---|
-| **Q3, Q4 (output disconnect FETs)** | The BOM says only "60V NFET" on the 5 × 6 mm SON footprint. No part is pinned. The CSD18563Q5A used for Q1/Q2 fits the footprint and the 60 V rating (inferred from the footprint and docs/06, not yet checked against its gate-drive needs with the LTC7004) |
+| **Q1–Q4 (power and disconnect FETs)** | The CSD18563Q5A was out of stock on 2026-09-27; the BOM orders onsemi NTMFS5C670NLT1G (60 V, 6.1 mΩ, Qg 20 nC) with the same S-S-S-G / tab pinout. Confirm the pad overlay in the JLCPCB preview, or buy CSD18563Q5A if it is back |
+| **C20, C75–C77 (input ceramics)** | No 22 µF 50 V 1210 is stocked; the BOM orders 10 µF 50 V, which drops the input ceramic from 88 to 40 µF (C21 is the bulk). Accept it or source 22 µF elsewhere |
+| **L2 (5V0 aux buck inductor)** | The 1210 land only takes 33 µH parts rated about 0.5 A; the value asks for 1.2 A. Fine if the 5V0 load (fan included) stays well under ~0.4 A. A bigger 5 × 5 mm land, as on the manager, is an open option |
 | **R30 (2 mΩ shunt)** | The LCSC part (C2994640) is cheap but its TCR is unverified. The CC accuracy depends on it. A Vishay WSLP-class part (~US$1.50) is the safe choice |
-| **U8, U11 variants** | The BOM flags that the LCSC variants (LMR36015ARNXR, TCAN1042VDRQ1) differ from the symbol values. Both are the right function (adjustable buck, VIO-capable CAN transceiver); confirm the footprint |
+| **U8, U11 variants** | The LCSC variants (LMR36015ARNXR, TCAN1042VDRQ1) differ from the symbol values. Both are the right function (adjustable buck, VIO-capable CAN transceiver) in the same package |
 | **J1, J4 terminal blocks** | The footprint is a 5.0 mm Phoenix PT; SOURCING.md lists 5.08 mm 2EDG plugs. Buy a header that matches the 5.0 mm footprint |
 | **Order-early parts** | LTC7004EMSE had only 5 in stock at LCSC. Put it in the cart first |
 
@@ -177,7 +179,7 @@ is cheap; a short at 24 V is not.
 | J2 SWD | 1 = 3V3, 2 = SWDIO, 3 = SWCLK, 4 = NRST, 5 = GND | See the note on pin 1 below |
 | J3 UART | 1 = GND, 2 = TX (from MCU), 3 = RX (to MCU) | 115200 8N1, 3.3 V |
 | J5 BACKPLANE | 1 = CAN_H, 2 = CAN_L, 3 = HW_EN, 4–6 = SLOT_ID0–2, 7–8 = PGND | The bench harness plugs in here |
-| J6 FAN | 1 = +5 V, 2 = fan return (switched low side) | Small 5 V fan; keep it under ~200 mA, the 5 V rail is sized for 0.5 A total |
+| J6 FAN | 1 = +5 V, 2 = fan return (switched low side) | Small 5 V fan; keep it under ~200 mA. The 5 V rail is sized for 0.5 A total, and the 1210 L2 the BOM fits is rated about 0.5 A, so keep the whole 5V0 load under ~0.4 A (§3.3) |
 
 **J2 pin 1:** a genuine ST-Link only senses target voltage on this pin. Many
 clone ST-Link V2 dongles *drive* 3.3 V onto it, which then fights the board's
@@ -267,13 +269,15 @@ ADC sampling on the high-impedance V_MEAS divider, then the DAC80502 gain.
 - **Phase-2 module (600 W)** reuses the Phase-1 control, sensing, disconnect,
   aux and MCU blocks, with a 2-phase LM5143 power stage and LM5069 hot-swap
   input. Its assembly is the same as above plus heavier soldering on the power
-  stage. It becomes orderable when its last 83 connections are routed and the
-  BOM `CHECK:` items for the LM5143 land pattern and the 220 µF caps are
-  settled.
+  stage. The board is routed and the 220 µF caps are settled (EEHZA1V221P);
+  the one open BOM item is the LM5143 Q1-variant land check (U3), plus the
+  1210 L2 question that Phase-1 has too.
 - **Phase-3 backplane and manager** turn modules into a rack. Before ordering
   the backplane, mate one XT60PW-M/F pair and buzz out which pad connects to
   which, and which cavity is marked "+" ([hardware/MECHANICAL.md](../hardware/MECHANICAL.md)).
-  Pads 1 = + on both sides is still an assumption. The manager firmware builds
+  Pads 1 = + on both sides is still an assumption. The manager board is
+  routed; its order files changed on 2026-10-06 (L2 on a 5 × 5 mm land), so
+  use ones generated from `development` or later. The manager firmware builds
   in CI (`firmware/manager/idf`, ESP-IDF 5.3.2); its bring-up knobs are in
   [docs/10](10-manager-firmware.md).
 
diff --git a/docs/12-phase1-bench-tests.md b/docs/12-phase1-bench-tests.md
index afb5ccf..fbc917b 100644
--- a/docs/12-phase1-bench-tests.md
+++ b/docs/12-phase1-bench-tests.md
@@ -407,8 +407,8 @@ Setpoint 12 V / 4 A, load at 3 A.
 - 750 Ω: T_fet reads ≥ 100 °C, output off, FAULT `OTP` latched. With the
   resistor still fitted, `reset clear` must not leave the module running (the
   fault re-latches on the next tick). Remove the resistor, then `reset clear`
-  clears it. docs/04 says clearing needs < 70 °C; firmware 0.1 only re-latches
-  at ≥ 100 °C, so note the actual behaviour.
+  clears it. docs/04 says clearing needs < 70 °C; firmware 0.2 (like 0.1) only
+  re-latches at ≥ 100 °C, so note the actual behaviour.
 - Record the reported temperature, the bits, and the output current at each
   step.
 
diff --git a/hardware/LAYOUT.md b/hardware/LAYOUT.md
index df2a6b9..25bb566 100644
--- a/hardware/LAYOUT.md
+++ b/hardware/LAYOUT.md
@@ -1,6 +1,6 @@
 # PCB layout guide — placement rules per board
 
-Status of layout work as of 2026-07-19, and per-cluster placement guidance for
+Status of layout work (table refreshed 2026-10-06), and per-cluster placement guidance for
 hand-layout in KiCad. Net names below are exactly as in the verified netlists
 (`check_netlist.py` green on phase-2 and backplane). Pin numbers were verified
 against the footprints + netlist, not memory.
@@ -9,14 +9,15 @@ against the footprints + netlist, not memory.
 
 | Board | Schematic | Netlist check | PCB |
 |---|---|---|---|
-| phase1-module | done | green | **done** — `phase1-module.kicad_pcb`: placement, pours, planes, critical routes, 0 DRC copper errors; some signal nets unrouted (autoroute.py is WIP) |
-| phase2-module | done (hand-arranged) | green (173 comps, 116 nets) | not started — this doc is the placement plan |
-| phase3-backplane | done | green (30 comps) | not started |
-| phase3-manager | done | green (80 comps, 86 nets) | **routed** 2026-09-27: 0 unconnected, 0 DRC errors (see `phase3-manager/tools/README.md`) |
+| phase1-module | done | green | **routed** 2026-09-27 at 100 × 80 mm: 0 unconnected, 0 DRC errors (see `phase1-module/tools/README.md`) |
+| phase2-module | done (hand-arranged) | green (173 comps, 116 nets) | **routed** 2026-09-27 at 130 × 90 mm: 0 unconnected, 0 DRC errors; the placement plan below is what was built |
+| phase3-backplane | done | green (30 comps) | **fab-ready** 2026-07-26: 0 unconnected, 0 DRC errors |
+| phase3-manager | done | green (80 comps, 86 nets) | **routed** 2026-09-27: 0 unconnected, 0 DRC errors; L2 moved to a 5 × 5 mm land 2026-10-05 (see `phase3-manager/tools/README.md`) |
 
 Phase-1's board is the reference implementation: open it next to this doc —
 every rule below is applied there and visible (input band → FET straddle →
-SW island → inductor → output band; the ground seam; the AGND pocket).
+SW island → inductor → output band; the ground seam. The 100 × 80 board has
+no AGND pocket: the LTC7004 cluster sits on the AGND side of the seam).
 
 ---
 
diff --git a/hardware/MECHANICAL.md b/hardware/MECHANICAL.md
index 19229f1..248f715 100644
--- a/hardware/MECHANICAL.md
+++ b/hardware/MECHANICAL.md
@@ -24,7 +24,7 @@ component + airflow:
 
 | Board | Size | Layers/copper | Notes |
 |---|---|---|---|
-| phase2-module | **130 × 90 mm** | 4-layer (stackup below) | grows from P1's 120×80 for hot-swap + 4 FETs; XT60PW-M + signal row on the bottom edge (power connector proud by ~2 mm for power-first mating) |
+| phase2-module | **130 × 90 mm** | 4-layer (stackup below) | grows from P1's original 120×80 for hot-swap + 4 FETs; XT60PW-M + signal row on the bottom edge (power connector proud by ~2 mm for power-first mating) |
 | phase1-module | **100 × 80 mm** (was 120 × 80; that layout is kept on branch `phase1-120x80`) | 4-layer | shrunk to fit JLCPCB's ≤100 × 100 mm tier; gets the same bottom-edge connector pair so it can plug the backplane too |
 | phase3-backplane | **~330 × 100 mm** | 2-layer 2 oz | 8 × 30 mm slots + end margins + manager header zone; M6 lug bolts at entry; bus rails solder-reinforced |
 | phase3-manager | **100 × 80 mm** | 2-layer 1 oz | display module on standoffs above (or panel-mounted via ribbon); encoder/keys wired to panel |
diff --git a/hardware/SOURCING.md b/hardware/SOURCING.md
index 0873001..710ffea 100644
--- a/hardware/SOURCING.md
+++ b/hardware/SOURCING.md
@@ -4,7 +4,9 @@ Verified 2026-07-18 via the jlcsearch API (LCSC stock + qty-1 USD prices)
 and JLCPCB part pages for critical ratings. **Strategy: everything from
 LCSC/JLCPCB in one consolidated shipment to Sri Lanka** (LCSC parts +
 JLCPCB boards combine into one DHL parcel; modules/AliExpress items noted
-separately). Prices move — re-check stock the week of ordering.
+separately). Prices move — re-check stock the week of ordering. Individual
+rows were re-checked and changed later (dated in their notes, latest
+2026-10-05); the per-board BOM CSVs are the current source of truth.
 
 The LCSC numbers below are applied to the schematic symbols and the per-board
 BOMs by `common/bom.py` (table: `common/lcsc_parts.py`) — change a part there,
@@ -38,14 +40,14 @@ Decisions taken this pass (user-approved 2026-07-18):
 | LMR36015ARNXR | C1850345 | 1.91 | 1.2k | |
 | NCP1117ST33T3G | C26537 | 0.21 | 14k | |
 | LTC7004EMSE#PBF | C690105 | 5.77 | **5** | thinnest stock in the BOM; 3 needed + spares. **Order early** (IMSE $6.98/30 as fallback) |
-| TLV7011DCKR | C193688 | 0.27 | 838 | **SC-70-5** — footprint changes from DBVR (SOT-23-5, $0.52, only 42 left) at the PCB pass |
+| TLV7011DCKR | C193688 | 0.27 | 838 | **SC-70-5** instead of DBVR (SOT-23-5, $0.52, only 42 left); the boards carry the SC-70-5 land |
 | TL431BIDBZR | C41283 | 0.054 | 7.9k | |
 | TS5A3166DBVR | C353035 | 0.28 | 7.6k | replaces TMUX1101 (not stocked on LCSC). Verified + applied 2026-07-18 (§F) |
 | TCA9535PWR | C130204 | 0.44 | 11k | UMW clone $0.33 acceptable here (non-critical) |
 | ESP32-S3-WROOM-1-N8R2 | C2913204 | 5.01 | 18k | |
 | TPD2E001DRLR | C150526 | 0.16 | 14k | |
 | LM5145RGYR (P1) | C485912 | 1.55 | 5.2k | |
-| CSD18563Q5A (P1) | C77239 | 0.85 | 794 | |
+| CSD18563Q5A (P1) | C77239 | 0.85 | 794 | out of stock 2026-09-27: the P1 BOM orders onsemi NTMFS5C670NLT1G (C179626, $0.49) for Q1–Q4 instead, same S-S-S-G / tab pinout. Still a `CHECK:` row: confirm the pad overlay in the JLCPCB preview |
 | 2N7002 / BAT54W / 1N4148WS / SMBJ33A / AO3401A | — | 0.01–0.05 | ≫10k | jellybeans, any reputable line |
 
 ## B. Magnetics & power passives
@@ -61,9 +63,10 @@ Decisions taken this pass (user-approved 2026-07-18):
 | 2 mΩ 2512 3 W 1 % (P1) | C2994640 | 0.060 | 167k | same TCR caveat |
 | Bus shunt 0.5 mΩ 3920 ×2 ∥ | C466580 | 0.60 | 2.9k | BVS-M-R0005: 2 in parallel = 0.25 mΩ (0.5 W each @62 A); verify power rating on ds. Alt: ARCS8518 100 µΩ bar $3.64/49 |
 | 220 µF 35 V hybrid ×4 | C454349 | 1.42 | **1** | Panasonic EEHZA1V221P D10×10.2, 20 mΩ / 2.5 A — fits the CP_Elec_10x10.5 land. Stocked alternative on the same land: SUNCON 35HVH220M+P (C179812, D10×12.5, 8 in stock 2026-09-28). The earlier D8 SVZ pick (C2923769) did not fit the land and is out of stock |
-| 470 µF 50 V bulk | C106666 | 0.10 | 73k | **THT radial D10×20** — cheaper + stronger than SMD; footprint changes at PCB pass |
+| 470 µF 50 V bulk | C106666 | 0.10 | 73k | **THT radial D10×20** — cheaper + stronger than SMD; phase-2 C14 carries the CP_Radial_D10 land |
 | 470 µF 50 V SMD (backplane C2) | C462700 | 1.63 | 633 (JLCPCB) | Nichicon UCX1H471MNS1MS, 16×16.5, 70 mΩ, 1.0 A @100 kHz, 135 °C. The board has an SMD CP_Elec_16x17.5 land (17×17 platform), not the THT D10 above; 16×16.5 cans fit it. Fallback: Panasonic EEEFK1H471AM (C178551, 131). Picked 2026-10-05 |
-| 33 µH aux-buck inductor (manager L2) | C167973 | 0.06 | 51k (JLCPCB) | cjiang FNR5040S330MT, 5×5×4 mm: **Isat 1.30 A min / Irms 1.20 A min / DCR 0.244 Ω max** (cjiang FNR datasheet). No 1210 33 µH is stocked above 0.5 A, so the manager land grew to L_Changjiang_FNR5040S (2026-10-05). Phase-1/2 L2 are still 1210 |
+| 33 µH aux-buck inductor (manager L2) | C167973 | 0.06 | 51k (JLCPCB) | cjiang FNR5040S330MT, 5×5×4 mm: **Isat 1.30 A min / Irms 1.20 A min / DCR 0.244 Ω max** (cjiang FNR datasheet). No 1210 33 µH is stocked above 0.5 A, so the manager land grew to L_Changjiang_FNR5040S (2026-10-05). Phase-1/2 L2 are still 1210: see the next row |
+| 33 µH 1210 (phase-1 L2) | C223226 | 0.25 | — | Taiyo Yuden CBC3225T330KR, 0.5 A: the strongest stocked 1210 33 µH, against a 1.2 A value. A BOM `CHECK:` row (fine only if 5V0 stays well under ~0.4 A). Phase-2 L2 has no number yet. Moving both to the manager's 5×5 land is offered and waits on the owner |
 | 10 µF 50 V X7S 1210 ×8+6 | C126612 | 0.144 | 43k | GCM32EC71H106KA03L; also replaces the 22 µF/50 V output MLCCs (that value barely exists) |
 | 8 MHz 3225 crystal | C400090 | 0.105 | 200k | cheap parts are CL=12 pF → C66/C67 = 18 p (APPLIED, both phases) |
 
@@ -131,9 +134,8 @@ green (137/173/30/80 components):
 - 470 µF bulk → THT radial D10; output MLCCs 22 µF→10 µF/50 V X7S
 - module slot power + P2 output → XT60PW-M (2-pin); backplane slots →
   XT60PW-F; bus shunt → 2× BVS-M-R0005 parallel
-- buzzer value → MLT-8530
+- buzzer value → MLT-8530 (since replaced by the 5 V-rated YX-SMD8530P, §C)
 
-Placeholder FOOTPRINTS remain for: XT60PW, MWSA1707S (17.2×17.2), BVS
-3920, MLT-8530 — land patterns from vendor drawings at the footprint pass
-(hardware/MECHANICAL.md lists them; the JLC datasheet CDN links expire,
-fetch fresh from part pages at that point).
+The placeholder footprints for XT60PW, MWSA1707S (17.2×17.2), BVS 3920 and
+MLT-8530 were replaced by vendor-drawing land patterns in the footprint pass
+(commit d281f94; `labbench.pretty`).
diff --git a/hardware/common/lcsc_parts.py b/hardware/common/lcsc_parts.py
index fda52b2..cce2ab2 100644
--- a/hardware/common/lcsc_parts.py
+++ b/hardware/common/lcsc_parts.py
@@ -67,9 +67,9 @@
 
     # ---- B. Magnetics & power passives ------------------------------------
     ({P2: ["L1", "L3"]}, "C6238332", "MWSA1707S-6R8MT", "Sunlord", 1.72,
-     "17 A Irms / 22 A Isat; placeholder footprint until the land pass"),
+     "17 A Irms / 22 A Isat; L_1707_XAL1510 superset land (also takes the XAL1510 spares)"),
     ({P1: ["L1"]}, "C5240401", "MWSA1707S-100MT", "Sunlord", 1.68,
-     "16.5 A Isat / 10.5 A Irms; placeholder footprint until the land pass"),
+     "16.5 A Isat / 10.5 A Irms; L_1707_XAL1510 superset land"),
     ({P2: ["R36", "R37", "R42", "R57"]}, "C49837985", "", "", 0.025,
      "7.5 mOhm 1206 1 W 1 %, phase-shunt pairs"),
     ({P2: ["R30", "R34"]}, "C46634444", "", "", 0.058,
diff --git a/hardware/phase1-module/bom/phase1-module-bom.csv b/hardware/phase1-module/bom/phase1-module-bom.csv
index 824b078..037b05c 100644
--- a/hardware/phase1-module/bom/phase1-module-bom.csv
+++ b/hardware/phase1-module/bom/phase1-module-bom.csv
@@ -34,7 +34,7 @@ Item,Qty,References,Value,Footprint,LCSC,MPN,Manufacturer,Unit USD,Ext USD,Note
 33,1,J4,OUTPUT,"TerminalBlock_Phoenix:TerminalBlock_Phoenix_PT-1,5-2-5.0-H_1x02_P5.00mm_Horizontal",,,,,,"through-hole, hand-solder; SOURCING lists 2EDG 5.08 plugs C3697 for P1 bench IO, but this footprint is a 5.0 mm Phoenix PT - pick the matching header"
 34,1,J5,BACKPLANE,Connector_PinHeader_2.54mm:PinHeader_1x08_P2.54mm_Vertical,,,,,,through-hole pin header: hand-solder (or pay for JLCPCB THT assembly)
 35,1,J6,FAN,Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical,,,,,,through-hole pin header: hand-solder (or pay for JLCPCB THT assembly)
-36,1,L1,10u MWSA1707S-100/XAL1350,labbench:L_1707_XAL1510,C5240401,MWSA1707S-100MT,Sunlord,1.68,1.68,16.5 A Isat / 10.5 A Irms; placeholder footprint until the land pass
+36,1,L1,10u MWSA1707S-100/XAL1350,labbench:L_1707_XAL1510,C5240401,MWSA1707S-100MT,Sunlord,1.68,1.68,16.5 A Isat / 10.5 A Irms; L_1707_XAL1510 superset land
 37,1,L2,33u/1.2A,Inductor_SMD:L_1210_3225Metric,C223226,CBC3225T330KR,Taiyo Yuden,0.2475,0.247,"CHECK: value says 33u/1.2A but no 1210 33 uH is rated near 1.2 A; this is the strongest stocked one (0.5 A). Fine if the 5V0 load stays well under ~0.4 A, otherwise move to a bigger inductor footprint"
 38,2,Q1 Q2,CSD18563Q5A,labbench:PowerFET_SON5x6_GDS,C179626,NTMFS5C670NLT1G,onsemi,0.49,0.98,"CHECK: stands in for CSD18563Q5A (C77239, out of stock 2026-09-27). 60 V, 6.1 mOhm, Qg 20 nC vs 5.7 mOhm / 15 nC; SO-8FL has the same S-S-S-G / drain-tab pinout as the TI Q5A land - confirm the pad overlay in the JLCPCB preview. Q3/Q4 dissipate about 0.6 W each at 10 A"
 39,2,Q3 Q4,60V NFET,labbench:PowerFET_SON5x6_GDS,C179626,NTMFS5C670NLT1G,onsemi,0.49,0.98,"CHECK: stands in for CSD18563Q5A (C77239, out of stock 2026-09-27). 60 V, 6.1 mOhm, Qg 20 nC vs 5.7 mOhm / 15 nC; SO-8FL has the same S-S-S-G / drain-tab pinout as the TI Q5A land - confirm the pad overlay in the JLCPCB preview. Q3/Q4 dissipate about 0.6 W each at 10 A"
diff --git a/hardware/phase1-module/lib/PARTS-TO-DOWNLOAD.md b/hardware/phase1-module/lib/PARTS-TO-DOWNLOAD.md
index 29c3079..4147dc9 100644
--- a/hardware/phase1-module/lib/PARTS-TO-DOWNLOAD.md
+++ b/hardware/phase1-module/lib/PARTS-TO-DOWNLOAD.md
@@ -83,6 +83,11 @@ verifies every component's footprint resolves and every netted pin has a pad.
 
 ## E. Pricing snapshot — verified 2026-07-16 (LCSC via jlcsearch, qty 1–10 USD)
 
+> Historical snapshot. The parts actually ordered changed since (for example
+> INA228AQDGSRQ1, TLV7011DCKR, NTMFS5C670NLT1G for Q1–Q4, MWSA1707S-100MT for
+> L1, and the board is now 100 × 80 mm). Current picks and prices:
+> `hardware/SOURCING.md` and `hardware/phase1-module/bom/`.
+
 | Part | Unit $ | Stock | Note |
 |---|---|---|---|
 | LTC7004EMSE#PBF | 5.77 | **5** | priciest IC, thin stock — order early or Mouser (~1.5×) |
diff --git a/hardware/phase2-module/bom/phase2-module-bom.csv b/hardware/phase2-module/bom/phase2-module-bom.csv
index 53a4e99..bd917c6 100644
--- a/hardware/phase2-module/bom/phase2-module-bom.csv
+++ b/hardware/phase2-module/bom/phase2-module-bom.csv
@@ -33,7 +33,7 @@ Item,Qty,References,Value,Footprint,LCSC,MPN,Manufacturer,Unit USD,Ext USD,Note
 32,1,J4,XT60PW-M OUTPUT,labbench:XT60PW-M,C98732,XT60PW-M,Amass,0.54,0.54,
 33,1,J5,SLOT SIGNALS,Connector_PinHeader_2.54mm:PinHeader_1x08_P2.54mm_Vertical,,,,,,
 34,1,J6,FAN,Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical,,,,,,
-35,2,L1 L3,6.8u MWSA1707S/XAL1510,labbench:L_1707_XAL1510,C6238332,MWSA1707S-6R8MT,Sunlord,1.72,3.44,17 A Irms / 22 A Isat; placeholder footprint until the land pass
+35,2,L1 L3,6.8u MWSA1707S/XAL1510,labbench:L_1707_XAL1510,C6238332,MWSA1707S-6R8MT,Sunlord,1.72,3.44,17 A Irms / 22 A Isat; L_1707_XAL1510 superset land (also takes the XAL1510 spares)
 36,1,L2,33u/1.2A,Inductor_SMD:L_1210_3225Metric,,,,,,
 37,8,Q1 Q2 Q3 Q4 Q10 Q11 Q12 Q13,CSD18540Q5B,labbench:PowerFET_SON5x6_GDS,C86513,CSD18540Q5B,TI,1.43,11.44,do not substitute clone power-stage FETs
 38,5,Q5 Q6 Q7 Q8 Q9,2N7002,Package_TO_SOT_SMD:SOT-23,,,,,,