diff --git a/cranelift/codegen/meta/src/gen_inst.rs b/cranelift/codegen/meta/src/gen_inst.rs
index 7acf965885c9..f5ca4ae7b469 100644
--- a/cranelift/codegen/meta/src/gen_inst.rs
+++ b/cranelift/codegen/meta/src/gen_inst.rs
@@ -1593,6 +1593,66 @@ fn gen_bitwise_not_builders(fmt: &mut Formatter) {
     }
 }
 
+/// Emit the `uload8`, `uload16`, `uload32`, `sload8`, `sload16`, `sload32`,
+/// `istore8`, `istore16`, and `istore32` `InstBuilder`
+/// backwards-compat/convenience methods.
+fn gen_extending_load_store_builders(fmt: &mut Formatter) {
+    for (bits, ty) in [(8, "I8"), (16, "I16"), (32, "I32")] {
+        for (prefix, ext_method, ext_doc) in [
+            ("u", "uextend", "zero-extend"),
+            ("s", "sextend", "sign-extend"),
+        ] {
+            // `{u,s}loadN` => `load` + `{u,s}extend`.
+            let method = format!("{prefix}load{bits}");
+            let tyvar = format!("iExt{bits}");
+            fmt.doc_comment(format!(
+                "Load {bits} bits from memory at ``p + Offset`` and {ext_doc}.\
+                 \n\nThis emits a `load` of the narrow type followed by a \
+                 `{ext_method}`.",
+            ));
+            fmt.line("#[allow(non_snake_case, reason = \"generated code\")]");
+            fmt.add_block(
+                &format!(
+                    "fn {method}<T1: Into<ir::MemFlagsData>, T2: Into<ir::immediates::Offset32>>(mut self, {tyvar}: crate::ir::Type, MemFlags: T1, p: ir::Value, Offset: T2) -> Value"
+                ),
+                |fmt| {
+                    fmt.line("let MemFlags = MemFlags.into();");
+                    fmt.line("let Offset = Offset.into();");
+                    fmt.line("let MemFlags = self.data_flow_graph_mut().mem_flags.insert(MemFlags).unwrap();");
+                    fmtln!(
+                        fmt,
+                        "let load = self.build_aux_inst(InstructionData::Load {{ opcode: Opcode::Load, arg: p, flags: MemFlags, offset: Offset }}, types::{ty});"
+                    );
+                    fmt.line("let load = self.data_flow_graph().first_result(load);");
+                    fmtln!(fmt, "self.{ext_method}({tyvar}, load)");
+                },
+            );
+            fmt.empty_line();
+        }
+
+        // `istoreN` => `ireduce` + `store`.
+        fmt.doc_comment(format!(
+            "Store the low {bits} bits of ``x`` to memory at ``p + Offset``.\
+             \n\nThis emits an `ireduce` to the narrow type followed by a `store`.",
+        ));
+        fmt.line("#[allow(non_snake_case, reason = \"generated code\")]");
+        fmt.add_block(
+            &format!(
+                "fn istore{bits}<T1: Into<ir::MemFlagsData>, T2: Into<ir::immediates::Offset32>>(mut self, MemFlags: T1, x: ir::Value, p: ir::Value, Offset: T2) -> Inst"
+            ),
+            |fmt| {
+                fmtln!(
+                    fmt,
+                    "let narrow = self.build_aux_inst(InstructionData::Unary {{ opcode: Opcode::Ireduce, arg: x }}, types::{ty});"
+                );
+                fmt.line("let narrow = self.data_flow_graph().first_result(narrow);");
+                fmt.line("self.store(MemFlags, narrow, p, Offset)");
+            },
+        );
+        fmt.empty_line();
+    }
+}
+
 /// Generate a Builder trait with methods for all instructions.
 fn gen_builder(
     instructions: &AllInstructions,
@@ -1631,6 +1691,8 @@ fn gen_builder(
         gen_stack_access_builders(fmt);
         fmt.empty_line();
         gen_bitwise_not_builders(fmt);
+        fmt.empty_line();
+        gen_extending_load_store_builders(fmt);
         for (i, format) in formats.iter().enumerate() {
             gen_format_constructor(format, fmt);
             if i + 1 != formats.len() {
diff --git a/cranelift/codegen/meta/src/shared/instructions.rs b/cranelift/codegen/meta/src/shared/instructions.rs
index 476a9375282e..4e3ba40bfa8f 100644
--- a/cranelift/codegen/meta/src/shared/instructions.rs
+++ b/cranelift/codegen/meta/src/shared/instructions.rs
@@ -788,194 +788,6 @@ pub(crate) fn define(
         .can_store(),
     );
 
-    let iExt8 = &TypeVar::new(
-        "iExt8",
-        "An integer type with more than 8 bits",
-        TypeSetBuilder::new().ints(16..64).build(),
-    );
-
-    ig.push(
-        Inst::new(
-            "uload8",
-            r#"
-        Load 8 bits from memory at ``p + Offset`` and zero-extend.
-
-        This is equivalent to ``load.i8`` followed by ``uextend``.
-        "#,
-            &formats.load,
-        )
-        .operands_in(&[
-            Operand::new("MemFlags", &imm.memflags),
-            Operand::new("p", iAddr),
-            Operand::new("Offset", &imm.offset32).with_doc("Byte offset from base address"),
-        ])
-        .operands_out(&[Operand::new("a", iExt8)])
-        .can_load(),
-    );
-
-    ig.push(
-        Inst::new(
-            "sload8",
-            r#"
-        Load 8 bits from memory at ``p + Offset`` and sign-extend.
-
-        This is equivalent to ``load.i8`` followed by ``sextend``.
-        "#,
-            &formats.load,
-        )
-        .operands_in(&[
-            Operand::new("MemFlags", &imm.memflags),
-            Operand::new("p", iAddr),
-            Operand::new("Offset", &imm.offset32).with_doc("Byte offset from base address"),
-        ])
-        .operands_out(&[Operand::new("a", iExt8)])
-        .can_load(),
-    );
-
-    ig.push(
-        Inst::new(
-            "istore8",
-            r#"
-        Store the low 8 bits of ``x`` to memory at ``p + Offset``.
-
-        This is equivalent to ``ireduce.i8`` followed by ``store.i8``.
-        "#,
-            &formats.store,
-        )
-        .operands_in(&[
-            Operand::new("MemFlags", &imm.memflags),
-            Operand::new("x", iExt8),
-            Operand::new("p", iAddr),
-            Operand::new("Offset", &imm.offset32).with_doc("Byte offset from base address"),
-        ])
-        .can_store(),
-    );
-
-    let iExt16 = &TypeVar::new(
-        "iExt16",
-        "An integer type with more than 16 bits",
-        TypeSetBuilder::new().ints(32..64).build(),
-    );
-
-    ig.push(
-        Inst::new(
-            "uload16",
-            r#"
-        Load 16 bits from memory at ``p + Offset`` and zero-extend.
-
-        This is equivalent to ``load.i16`` followed by ``uextend``.
-        "#,
-            &formats.load,
-        )
-        .operands_in(&[
-            Operand::new("MemFlags", &imm.memflags),
-            Operand::new("p", iAddr),
-            Operand::new("Offset", &imm.offset32).with_doc("Byte offset from base address"),
-        ])
-        .operands_out(&[Operand::new("a", iExt16)])
-        .can_load(),
-    );
-
-    ig.push(
-        Inst::new(
-            "sload16",
-            r#"
-        Load 16 bits from memory at ``p + Offset`` and sign-extend.
-
-        This is equivalent to ``load.i16`` followed by ``sextend``.
-        "#,
-            &formats.load,
-        )
-        .operands_in(&[
-            Operand::new("MemFlags", &imm.memflags),
-            Operand::new("p", iAddr),
-            Operand::new("Offset", &imm.offset32).with_doc("Byte offset from base address"),
-        ])
-        .operands_out(&[Operand::new("a", iExt16)])
-        .can_load(),
-    );
-
-    ig.push(
-        Inst::new(
-            "istore16",
-            r#"
-        Store the low 16 bits of ``x`` to memory at ``p + Offset``.
-
-        This is equivalent to ``ireduce.i16`` followed by ``store.i16``.
-        "#,
-            &formats.store,
-        )
-        .operands_in(&[
-            Operand::new("MemFlags", &imm.memflags),
-            Operand::new("x", iExt16),
-            Operand::new("p", iAddr),
-            Operand::new("Offset", &imm.offset32).with_doc("Byte offset from base address"),
-        ])
-        .can_store(),
-    );
-
-    let iExt32 = &TypeVar::new(
-        "iExt32",
-        "An integer type with more than 32 bits",
-        TypeSetBuilder::new().ints(64..64).build(),
-    );
-
-    ig.push(
-        Inst::new(
-            "uload32",
-            r#"
-        Load 32 bits from memory at ``p + Offset`` and zero-extend.
-
-        This is equivalent to ``load.i32`` followed by ``uextend``.
-        "#,
-            &formats.load,
-        )
-        .operands_in(&[
-            Operand::new("MemFlags", &imm.memflags),
-            Operand::new("p", iAddr),
-            Operand::new("Offset", &imm.offset32).with_doc("Byte offset from base address"),
-        ])
-        .operands_out(&[Operand::new("a", iExt32)])
-        .can_load(),
-    );
-
-    ig.push(
-        Inst::new(
-            "sload32",
-            r#"
-        Load 32 bits from memory at ``p + Offset`` and sign-extend.
-
-        This is equivalent to ``load.i32`` followed by ``sextend``.
-        "#,
-            &formats.load,
-        )
-        .operands_in(&[
-            Operand::new("MemFlags", &imm.memflags),
-            Operand::new("p", iAddr),
-            Operand::new("Offset", &imm.offset32).with_doc("Byte offset from base address"),
-        ])
-        .operands_out(&[Operand::new("a", iExt32)])
-        .can_load(),
-    );
-
-    ig.push(
-        Inst::new(
-            "istore32",
-            r#"
-        Store the low 32 bits of ``x`` to memory at ``p + Offset``.
-
-        This is equivalent to ``ireduce.i32`` followed by ``store.i32``.
-        "#,
-            &formats.store,
-        )
-        .operands_in(&[
-            Operand::new("MemFlags", &imm.memflags),
-            Operand::new("x", iExt32),
-            Operand::new("p", iAddr),
-            Operand::new("Offset", &imm.offset32).with_doc("Byte offset from base address"),
-        ])
-        .can_store(),
-    );
     ig.push(
         Inst::new(
             "stack_switch",
diff --git a/cranelift/codegen/src/alias_analysis.rs b/cranelift/codegen/src/alias_analysis.rs
index f2a0261c4e61..477ef80b669c 100644
--- a/cranelift/codegen/src/alias_analysis.rs
+++ b/cranelift/codegen/src/alias_analysis.rs
@@ -38,10 +38,10 @@
 //! To get this must-alias property, we compute a sparse table of
 //! "memory values": these are known equivalences between SSA `Value`s
 //! and particular locations in memory. The memory-values table is a
-//! mapping from (last store, address expression, type) to SSA
-//! value. At a store, we can insert into this table directly. At a
-//! load, we can also insert, if we don't already have a value (from
-//! the store that produced the load's value).
+//! mapping from a memory location (address, type, byte order, etc...)
+//! to a known value. At a store, we can insert into this table
+//! directly. At a load, we can also insert, if we don't already have a
+//! value (from the store that produced the load's value).
 //!
 //! Then we do a few optimizations at once given this table:
 //!
@@ -80,7 +80,9 @@ use crate::{
     dominator_tree::DominatorTree,
     flowgraph::ControlFlowGraph,
     inst_predicates::{inst_addr_offset_type, inst_store_data, visit_block_succs},
-    ir::{AliasRegion, Block, Function, Inst, Opcode, Type, Value, immediates::Offset32},
+    ir::{
+        AliasRegion, Block, Endianness, Function, Inst, Opcode, Type, Value, immediates::Offset32,
+    },
     post_dominator_tree::PostDominatorTree,
     trace,
 };
@@ -537,31 +539,41 @@ impl LastStores {
 /// A key identifying a unique memory location.
 ///
 /// For the result of a load to be equivalent to the result of another
-/// load, or the store data from a store, we need for (i) the
-/// "version" of memory (here ensured by having the same last store
-/// instruction to touch the disjoint category of abstract state we're
-/// accessing); (ii) the address must be the same (here ensured by
-/// having the same SSA value, which doesn't change after computed);
-/// (iii) the offset must be the same; and (iv) the accessed type and
-/// extension mode (e.g., 8-to-32, signed) must be the same.
+/// load, or the store data from a store, we need for (i) the "version"
+/// of memory (here ensured by having the same last store instruction
+/// to touch the disjoint category of abstract state we're accessing);
+/// (ii) the address must be the same (here ensured by having the same
+/// SSA value, which doesn't change after computed); (iii) the offset
+/// must be the same; (iv) the accessed type must be the same; and (v)
+/// the byte order of the two accesses must be the same.
 #[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 struct MemoryLoc {
     last_store: PackedOption<Inst>,
     address: Value,
     offset: Offset32,
     ty: Type,
-    /// We keep the *opcode* of the instruction that produced the
-    /// value we record at this key if the opcode is anything other
-    /// than an ordinary load or store. This is needed when we
-    /// consider loads that extend the value: e.g., an 8-to-32
-    /// sign-extending load will produce a 32-bit value from an 8-bit
-    /// value in memory, so we can only reuse that (as part of RLE)
-    /// for another load with the same extending opcode.
+    /// We keep the *opcode* of the instruction that produced the value we
+    /// record at this key if the opcode is anything other than an ordinary load
+    /// or store, like an atomic access. An atomic access is not interchangeable
+    /// with a plain one, so we only reuse the value at this key for an access
+    /// with the same opcode. Plain `load` and `store` opcodes both map to
+    /// `None` so that store-to-load forwarding works between them.
+    special_opcode: Option<Opcode>,
+    /// The byte order of this access, as explicitly specified in its memory
+    /// flags, or `None` when the access uses the target's native byte order.
+    ///
+    /// Without this, two accesses to the same address that disagree about byte
+    /// order would share a key, and we would happily forward a value from one
+    /// to the other, dropping the byte swap that the mismatch implies.
     ///
-    /// We could improve the transform to insert explicit extend ops
-    /// in place of extending loads when we know the memory value, but
-    /// we haven't yet done this.
-    extending_opcode: Option<Opcode>,
+    /// We only record the *explicit* byte order here, rather than resolving
+    /// `None` to the target's native byte order. This keeps the pass
+    /// independent of the target, but does mean we never share a key between an
+    /// access that spells out the native byte order and one that leaves it
+    /// implicit. That scenario leads to missed optimizations, never
+    /// miscompiles, and is exceedingly rare, so we deem the trade off worth it
+    /// for simplicity.
+    endianness: Option<Endianness>,
 }
 
 /// What is known to be in memory at an associated `MemoryLoc`.
@@ -636,8 +648,7 @@ pub struct AliasAnalysis<'a> {
     block_input: FxHashMap<Block, LastStores>,
 
     /// Known memory-value equivalences. This is the result of the
-    /// analysis. This is a mapping from (last store, address
-    /// expression, offset, type) to SSA `Value`.
+    /// analysis. This is a mapping from a memory location to its known value.
     mem_values: FxHashMap<MemoryLoc, KnownValue>,
 }
 
@@ -807,12 +818,19 @@ impl<'a> AliasAnalysis<'a> {
                         // layout, so drop its entry from `mem_values`. This
                         // maintains the invariant that `mem_values` only ever
                         // references instructions that are still in the layout.
+                        //
+                        // NB: the entry we are looking for was keyed on the
+                        // *dead* store's byte order, which `fully_overwrites`
+                        // does not require to match this store's byte order.
+                        // Everything else in the key does have to match, so we
+                        // can take it from this store.
                         let dead_loc = MemoryLoc {
                             last_store: last_store.into(),
                             address,
                             offset,
                             ty,
-                            extending_opcode: get_ext_opcode(opcode),
+                            special_opcode: special_opcode(opcode),
+                            endianness: get_endianness(func, last_store),
                         };
                         let dead_entry = self.mem_values.remove(&dead_loc);
 
@@ -857,7 +875,8 @@ impl<'a> AliasAnalysis<'a> {
                     address,
                     offset,
                     ty,
-                    extending_opcode: get_ext_opcode(opcode),
+                    special_opcode: special_opcode(opcode),
+                    endianness: get_endianness(func, inst),
                 };
                 if let Some(KnownValue {
                     def_inst,
@@ -898,7 +917,8 @@ impl<'a> AliasAnalysis<'a> {
                     address,
                     offset,
                     ty,
-                    extending_opcode: get_ext_opcode(opcode),
+                    special_opcode: special_opcode(opcode),
+                    endianness: get_endianness(func, inst),
                 };
                 trace!("  --> updating known values in memory: {mem_loc:?} = {store_data}");
                 self.mem_values.insert(
@@ -923,7 +943,8 @@ impl<'a> AliasAnalysis<'a> {
                     address,
                     offset,
                     ty,
-                    extending_opcode: get_ext_opcode(opcode),
+                    special_opcode: special_opcode(opcode),
+                    endianness: get_endianness(func, inst),
                 };
                 trace!("  load with last_store at loc {mem_loc:?}");
 
@@ -1040,7 +1061,15 @@ impl<'a> AliasAnalysis<'a> {
     }
 }
 
-fn get_ext_opcode(op: Opcode) -> Option<Opcode> {
+/// Get the explicitly-specified byte order of the given memory access,
+/// if any.
+fn get_endianness(func: &Function, inst: Inst) -> Option<Endianness> {
+    func.dfg.insts[inst]
+        .memflags_data(&func.dfg)
+        .and_then(|flags| flags.explicit_endianness())
+}
+
+fn special_opcode(op: Opcode) -> Option<Opcode> {
     debug_assert!(op.can_load() || op.can_store());
     match op {
         Opcode::Load | Opcode::Store => None,
@@ -1051,11 +1080,10 @@ fn get_ext_opcode(op: Opcode) -> Option<Opcode> {
 /// Can `overwriter` make `maybe_dead` a dead store?
 ///
 /// Only if `maybe_dead` is itself a store that writes exactly the
-/// bytes `overwriter` overwrites: the same alias region, address,
-/// offset, type, and store width (i.e. extending/truncating
-/// opcode). Otherwise some (or all) of `maybe_dead`'s bytes may
-/// remain observable after `overwriter` runs, and removing
-/// `maybe_dead` would change the program's behavior.
+/// bytes `overwriter` overwrites: the same opcode, alias region,
+/// address, offset, and type. Otherwise some (or all) of
+/// `maybe_dead`'s bytes may remain observable after `overwriter` runs,
+/// and removing `maybe_dead` would change the program's behavior.
 ///
 /// `overwriter_addr` must already have had its value-aliases resolved
 /// (as the caller does for the overwriter's address).
@@ -1077,10 +1105,10 @@ fn fully_overwrites(
         return false;
     }
 
-    // Both must write the same number of bytes: e.g. `istore8` and `store`
-    // write different widths even when their value types are equal.
+    // Both must be the same kind of store: e.g. a plain `store` does not
+    // subsume an `atomic_store`, whose fence is observable on its own.
     let overwriter_opcode = func.dfg.insts[overwriter].opcode();
-    if get_ext_opcode(maybe_dead_opcode) != get_ext_opcode(overwriter_opcode) {
+    if maybe_dead_opcode != overwriter_opcode {
         return false;
     }
 
@@ -1104,6 +1132,12 @@ fn fully_overwrites(
         return false;
     }
 
+    // NB: unlike store-to-load forwarding and redundant-load
+    // elimination, our two stores' byte orders do *not* have to match
+    // Both write the same range of bytes, just in a different order
+    // within that range, and the overwriting store's bytes are the
+    // ones that survive either way.
+
     // Both must write the same address, offset, and type.
     match inst_addr_offset_type(func, maybe_dead) {
         Some((addr, offset, ty)) => {
diff --git a/cranelift/codegen/src/isa/aarch64/lower.isle b/cranelift/codegen/src/isa/aarch64/lower.isle
index f3c37ff60348..c94ae3bdf7b7 100644
--- a/cranelift/codegen/src/isa/aarch64/lower.isle
+++ b/cranelift/codegen/src/isa/aarch64/lower.isle
@@ -2603,25 +2603,6 @@
       (load (ty_dyn_vec128 _) (little_or_native_endian flags) address offset))
       (aarch64_fpuload128 (amode $I8X16 address offset) flags))
 
-(rule (lower
-       (uload8 _ (little_or_native_endian flags) address offset))
-      (aarch64_uload8 (amode $I8 address offset) flags))
-(rule (lower
-       (sload8 _ (little_or_native_endian flags) address offset))
-      (aarch64_sload8 (amode $I8 address offset) flags))
-(rule (lower
-       (uload16 _ (little_or_native_endian flags) address offset))
-      (aarch64_uload16 (amode $I16 address offset) flags))
-(rule (lower
-       (sload16 _ (little_or_native_endian flags) address offset))
-      (aarch64_sload16 (amode $I16 address offset) flags))
-(rule (lower
-       (uload32 _ (little_or_native_endian flags) address offset))
-      (aarch64_uload32 (amode $I32 address offset) flags))
-(rule (lower
-       (sload32 _ (little_or_native_endian flags) address offset))
-      (aarch64_sload32 (amode $I32 address offset) flags))
-
 (rule (lower
        (sload8x8 _ (little_or_native_endian flags) address offset))
       (vec_extend (VecExtendOp.Sxtl)
@@ -2678,19 +2659,6 @@
       (side_effect
        (aarch64_store64 (amode $I64 address offset) flags value)))
 
-(rule (lower
-       (istore8 (little_or_native_endian flags) value address offset))
-      (side_effect
-       (aarch64_store8 (amode $I8 address offset) flags value)))
-(rule (lower
-       (istore16 (little_or_native_endian flags) value address offset))
-      (side_effect
-       (aarch64_store16 (amode $I16 address offset) flags value)))
-(rule (lower
-       (istore32 (little_or_native_endian flags) value address offset))
-      (side_effect
-       (aarch64_store32 (amode $I32 address offset) flags value)))
-
 (rule store_i128 (lower
        (store (little_or_native_endian flags) value @ (value_type $I128) address offset))
       (side_effect
diff --git a/cranelift/codegen/src/isa/pulley_shared/inst.isle b/cranelift/codegen/src/isa/pulley_shared/inst.isle
index e9a63e1703d7..914bda37994c 100644
--- a/cranelift/codegen/src/isa/pulley_shared/inst.isle
+++ b/cranelift/codegen/src/isa/pulley_shared/inst.isle
@@ -291,6 +291,33 @@
 
 (convert SinkableLoad SunkLoad sink_load)
 
+;; A narrow integer load whose result is about to be widened by a `uextend` or
+;; `sextend`. Pulley's `xload` instructions can perform that extension as part
+;; of the load itself, so the lowering of the extend sinks the load and
+;; re-emits it with the appropriate `ExtKind` via `gen_sunk_xload`.
+;;
+;; Unlike `sinkable_load` above there are no additional requirements on
+;; endianness, trapping, or the width of the static offset, because the load is
+;; emitted through `gen_xload`, which handles all of those cases itself.
+;;
+;; Like `SinkableLoad`, this deliberately hands back the load's *operands*
+;; rather than its result value. A rule matching on it therefore cannot come to
+;; depend on how that load would have been lowered on its own.
+(type SinkableNarrowLoad
+  (enum (Load (inst Inst) (ty Type) (flags MemFlagsData) (addr Value) (offset Offset32))))
+
+(decl pure partial sinkable_narrow_load (Value) SinkableNarrowLoad)
+
+(rule (sinkable_narrow_load value)
+  (if-let inst @ (load ty (mem_flags_data flags) addr offset) (is_sinkable_inst value))
+  (SinkableNarrowLoad.Load inst ty flags addr offset))
+
+;; Commit to sinking a `SinkableNarrowLoad` and emit it as an extending `xload`.
+(decl gen_sunk_xload (SinkableNarrowLoad ExtKind) XReg)
+(rule (gen_sunk_xload (SinkableNarrowLoad.Load inst ty flags addr offset) ext)
+      (let ((_ Unit (sink_inst inst)))
+        (gen_xload addr offset flags ty ext)))
+
 ;; Helper for determining what the pointer width of the host is.
 (type PointerWidth extern (enum PointerWidth32 PointerWidth64))
 (decl pure pointer_width () PointerWidth)
diff --git a/cranelift/codegen/src/isa/pulley_shared/lower.isle b/cranelift/codegen/src/isa/pulley_shared/lower.isle
index da423813ac33..392f8b74a9f2 100644
--- a/cranelift/codegen/src/isa/pulley_shared/lower.isle
+++ b/cranelift/codegen/src/isa/pulley_shared/lower.isle
@@ -976,41 +976,25 @@
         (hi XReg (pulley_xload (amode addr offsetp8) $I64 flags)))
     (value_regs lo hi)))
 
-(rule 0 (lower (uload8 (ty_int (fits_in_32 _)) (mem_flags_data flags) addr offset))
-  (gen_xload addr offset flags $I8 (ExtKind.Zero32)))
+;; Pulley's `xload` instructions can extend the loaded value as part of the
+;; load itself, so sink a narrow load into the extension that consumes it and
+;; re-emit it as a single extending load.
 
-(rule 0 (lower (uload16 (ty_int (fits_in_32 _)) (mem_flags_data flags) addr offset))
-  (gen_xload addr offset flags $I16 (ExtKind.Zero32)))
+(rule 2 (lower (uextend (fits_in_32 _) val))
+  (if-let ld (sinkable_narrow_load val))
+  (gen_sunk_xload ld (ExtKind.Zero32)))
 
-(rule 0 (lower (uload32 (ty_int (fits_in_32 _)) (mem_flags_data flags) addr offset))
-  (gen_xload addr offset flags $I32 (ExtKind.None)))
+(rule 3 (lower (uextend $I64 val))
+  (if-let ld (sinkable_narrow_load val))
+  (gen_sunk_xload ld (ExtKind.Zero64)))
 
-(rule 1 (lower (uload8 $I64 (mem_flags_data flags) addr offset))
-  (gen_xload addr offset flags $I8 (ExtKind.Zero64)))
+(rule 2 (lower (sextend (fits_in_32 _) val))
+  (if-let ld (sinkable_narrow_load val))
+  (gen_sunk_xload ld (ExtKind.Sign32)))
 
-(rule 1 (lower (uload16 $I64 (mem_flags_data flags) addr offset))
-  (gen_xload addr offset flags $I16 (ExtKind.Zero64)))
-
-(rule 1 (lower (uload32 $I64 (mem_flags_data flags) addr offset))
-  (gen_xload addr offset flags $I32 (ExtKind.Zero64)))
-
-(rule 0 (lower (sload8 (ty_int (fits_in_32 _)) (mem_flags_data flags) addr offset))
-  (gen_xload addr offset flags $I8 (ExtKind.Sign32)))
-
-(rule 0 (lower (sload16 (ty_int (fits_in_32 _)) (mem_flags_data flags) addr offset))
-  (gen_xload addr offset flags $I16 (ExtKind.Sign32)))
-
-(rule 0 (lower (sload32 (ty_int (fits_in_32 _)) (mem_flags_data flags) addr offset))
-  (gen_xload addr offset flags $I32 (ExtKind.None)))
-
-(rule 1 (lower (sload8 $I64 (mem_flags_data flags) addr offset))
-  (gen_xload addr offset flags $I8 (ExtKind.Sign64)))
-
-(rule 1 (lower (sload16 $I64 (mem_flags_data flags) addr offset))
-  (gen_xload addr offset flags $I16 (ExtKind.Sign64)))
-
-(rule 1 (lower (sload32 $I64 (mem_flags_data flags) addr offset))
-  (gen_xload addr offset flags $I32 (ExtKind.Sign64)))
+(rule 3 (lower (sextend $I64 val))
+  (if-let ld (sinkable_narrow_load val))
+  (gen_sunk_xload ld (ExtKind.Sign64)))
 
 (rule 2 (lower (load (ty_vec128 ty) (mem_flags_data flags) addr offset))
   (gen_vload addr offset flags ty (VExtKind.None)))
@@ -1265,15 +1249,6 @@
 (rule 1 (lower (store (mem_flags_data flags) src @ (value_type (ty_scalar_float ty)) addr offset))
   (side_effect (gen_store src addr offset flags ty)))
 
-(rule (lower (istore8 (mem_flags_data flags) src addr offset))
-  (side_effect (gen_store src addr offset flags $I8)))
-
-(rule (lower (istore16 (mem_flags_data flags) src addr offset))
-  (side_effect (gen_store src addr offset flags $I16)))
-
-(rule (lower (istore32 (mem_flags_data flags) src addr offset))
-  (side_effect (gen_store src addr offset flags $I32)))
-
 (rule 2 (lower (store (mem_flags_data flags) src @ (value_type (ty_vec128 ty)) addr offset))
   (side_effect (gen_store src addr offset flags ty)))
 
diff --git a/cranelift/codegen/src/isa/riscv64/lower.isle b/cranelift/codegen/src/isa/riscv64/lower.isle
index f3b91b0767f7..680e3646660a 100644
--- a/cranelift/codegen/src/isa/riscv64/lower.isle
+++ b/cranelift/codegen/src/isa/riscv64/lower.isle
@@ -2178,30 +2178,6 @@
 (rule (lower (trapnz value code))
   (gen_trapif (is_nonzero_cmp value) code))
 
-;;;;;  Rules for `uload8`;;;;;;;;;
-(rule (lower (uload8 _ (little_or_native_endian flags) addr offset))
-  (gen_load (amode addr offset) (LoadOP.Lbu) flags))
-
-;;;;;  Rules for `sload8`;;;;;;;;;
-(rule (lower (sload8 _ (little_or_native_endian flags) addr offset))
-  (gen_load (amode addr offset) (LoadOP.Lb) flags))
-
-;;;;;  Rules for `uload16`;;;;;;;;;
-(rule (lower (uload16 _ (little_or_native_endian flags) addr offset))
-  (gen_load (amode addr offset) (LoadOP.Lhu) flags))
-
-;;;;;  Rules for `iload16`;;;;;;;;;
-(rule (lower (sload16 _ (little_or_native_endian flags) addr offset))
-  (gen_load (amode addr offset) (LoadOP.Lh) flags))
-
-;;;;;  Rules for `uload32`;;;;;;;;;
-(rule (lower (uload32 _ (little_or_native_endian flags) addr offset))
-  (gen_load (amode addr offset) (LoadOP.Lwu) flags))
-
-;;;;;  Rules for `sload32`;;;;;;;;;
-(rule (lower (sload32 _ (little_or_native_endian flags) addr offset))
-  (gen_load (amode addr offset) (LoadOP.Lw) flags))
-
 ;;;;;  Rules for `load`;;;;;;;;;
 (rule (lower (load ty (little_or_native_endian flags) addr offset))
   (gen_load (amode addr offset) (load_op ty) flags))
@@ -2262,18 +2238,6 @@
 (rule (lower (sload32x2 (ty_supported_vec ty @ $I64X2) (little_or_native_endian flags) addr offset))
   (gen_load64_extend ty (ExtendOp.Signed) flags (amode addr offset)))
 
-;;;;;  Rules for `istore8`;;;;;;;;;
-(rule (lower (istore8 (little_or_native_endian flags) src addr offset))
-  (rv_store (amode addr offset) (StoreOP.Sb) flags src))
-
-;;;;;  Rules for `istore16`;;;;;;;;;
-(rule (lower (istore16 (little_or_native_endian flags) src addr offset))
-  (rv_store (amode addr offset) (StoreOP.Sh) flags src))
-
-;;;;;  Rules for `istore32`;;;;;;;;;
-(rule (lower (istore32 (little_or_native_endian flags) src addr offset))
-  (rv_store (amode addr offset) (StoreOP.Sw) flags src))
-
 ;;;;;  Rules for `store`;;;;;;;;;
 (rule (lower (store (little_or_native_endian flags) src @ (value_type ty) addr offset))
   (gen_store (amode addr offset) flags src))
diff --git a/cranelift/codegen/src/isa/s390x/inst.isle b/cranelift/codegen/src/isa/s390x/inst.isle
index 7f194c42df2d..2c5de37c0ecd 100644
--- a/cranelift/codegen/src/isa/s390x/inst.isle
+++ b/cranelift/codegen/src/isa/s390x/inst.isle
@@ -1992,14 +1992,6 @@
       (if (memarg_symbol_offset_sum sym_offset load_offset))
       inst)
 
-(decl pure partial uload16_sym (Inst) Inst)
-(rule (uload16_sym inst)
-      (if-let (uload16 _ _ (symbol_value _ (symbol_value_data _ (RelocDistance.Near) sym_offset))
-                       (i64_from_offset load_offset))
-          inst)
-      (if (memarg_symbol_offset_sum sym_offset load_offset))
-      inst)
-
 
 ;; Helpers for stack-slot addresses ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -2042,30 +2034,48 @@
 (extractor (sinkable_load_16 inst)
            (and (value_type $I16) (sinkable_load inst)))
 
+;; Sinkable big-endian load instruction (32-bit types only).
+(decl sinkable_load_32 (Inst) Value)
+(extractor (sinkable_load_32 inst)
+           (and (value_type $I32) (sinkable_load inst)))
+
+;; Sinkable 8-bit load instruction.
+;;
+;; A single byte has no byte order, so unlike `sinkable_load` this matches
+;; little-endian loads as well.
+(decl sinkable_load_8 (Inst) Value)
+(extractor (sinkable_load_8 inst)
+           (and (value_type $I8)
+                (sinkable_inst (and inst (load _ _flags _addr _offset)))))
+
 ;; Sinkable little-endian load instruction.
 (decl sinkable_load_little (Inst) Value)
 (extractor (sinkable_load_little inst)
            (sinkable_inst (and inst (load _ (mem_flags_data (littleendian)) _addr _offset))))
 
-;; Sinkable big-endian sload16 instruction.
+;; Sinkable big-endian 16-bit load feeding a `sextend`.
+;;
+;; Note that both the `sextend` and the load itself must be sinkable: the load
+;; is consumed by `sink_load`, so if the `sextend` had any other user it would
+;; end up reading a value that was never produced.
 (decl sinkable_sload16 (Inst) Value)
 (extractor (sinkable_sload16 inst)
-           (sinkable_inst (and inst (sload16 _ (mem_flags_data (bigendian)) _addr _offset))))
+           (sinkable_inst (sextend _ (sinkable_load_16 inst))))
 
-;; Sinkable big-endian sload32 instruction.
+;; Sinkable big-endian 32-bit load feeding a `sextend`.
 (decl sinkable_sload32 (Inst) Value)
 (extractor (sinkable_sload32 inst)
-           (sinkable_inst (and inst (sload32 _ (mem_flags_data (bigendian)) _addr _offset))))
+           (sinkable_inst (sextend _ (sinkable_load_32 inst))))
 
-;; Sinkable big-endian uload16 instruction.
+;; Sinkable big-endian 16-bit load feeding a `uextend`.
 (decl sinkable_uload16 (Inst) Value)
 (extractor (sinkable_uload16 inst)
-           (sinkable_inst (and inst (uload16 _ (mem_flags_data (bigendian)) _addr _offset))))
+           (sinkable_inst (uextend _ (sinkable_load_16 inst))))
 
-;; Sinkable big-endian uload32 instruction.
+;; Sinkable big-endian 32-bit load feeding a `uextend`.
 (decl sinkable_uload32 (Inst) Value)
 (extractor (sinkable_uload32 inst)
-           (sinkable_inst (and inst (uload32 _ (mem_flags_data (bigendian)) _addr _offset))))
+           (sinkable_inst (uextend _ (sinkable_load_32 inst))))
 
 ;; Sink a load instruction, returning its address as `MemArg`.
 ;; This is a side-effectful operation, see `sink_inst`.
@@ -2074,34 +2084,6 @@
       (let ((_ Unit (sink_inst inst)))
         (lower_address flags addr offset)))
 
-;; Sink a sload16 instruction, returning its address as `MemArg`.
-;; This is a side-effectful operation, see `sink_inst`.
-(decl sink_sload16 (Inst) MemArg)
-(rule (sink_sload16 inst @ (sload16 _ (mem_flags_data flags) addr offset))
-      (let ((_ Unit (sink_inst inst)))
-        (lower_address flags addr offset)))
-
-;; Sink a sload32 instruction, returning its address as `MemArg`.
-;; This is a side-effectful operation, see `sink_inst`.
-(decl sink_sload32 (Inst) MemArg)
-(rule (sink_sload32 inst @ (sload32 _ (mem_flags_data flags) addr offset))
-      (let ((_ Unit (sink_inst inst)))
-        (lower_address flags addr offset)))
-
-;; Sink a uload16 instruction, returning its address as `MemArg`.
-;; This is a side-effectful operation, see `sink_inst`.
-(decl sink_uload16 (Inst) MemArg)
-(rule (sink_uload16 inst @ (uload16 _ (mem_flags_data flags) addr offset))
-      (let ((_ Unit (sink_inst inst)))
-        (lower_address flags addr offset)))
-
-;; Sink a uload32 instruction, returning its address as `MemArg`.
-;; This is a side-effectful operation, see `sink_inst`.
-(decl sink_uload32 (Inst) MemArg)
-(rule (sink_uload32 inst @ (uload32 _ (mem_flags_data flags) addr offset))
-      (let ((_ Unit (sink_inst inst)))
-        (lower_address flags addr offset)))
-
 
 ;; Helpers for register pairs ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -3271,6 +3253,8 @@
 (decl put_in_reg_zext32 (Value) Reg)
 (rule 3 (put_in_reg_zext32 (and (value_type ty) (u64_from_value val)))
       (imm (ty_ext32 ty) val))
+(rule 4 (put_in_reg_zext32 (sinkable_load_8 load))
+      (zext32_mem $I8 (sink_load load)))
 (rule 1 (put_in_reg_zext32 (and (value_type (fits_in_16 ty)) (sinkable_load load)))
       (zext32_mem ty (sink_load load)))
 (rule 0 (put_in_reg_zext32 val @ (value_type (fits_in_16 ty)))
@@ -3282,6 +3266,8 @@
 (decl put_in_reg_sext32 (Value) Reg)
 (rule 3 (put_in_reg_sext32 (and (value_type ty) (u64_from_signed_value val)))
       (imm (ty_ext32 ty) val))
+(rule 4 (put_in_reg_sext32 (sinkable_load_8 load))
+      (sext32_mem $I8 (sink_load load)))
 (rule 1 (put_in_reg_sext32 (and (value_type (fits_in_16 ty)) (sinkable_load load)))
       (sext32_mem ty (sink_load load)))
 (rule 0 (put_in_reg_sext32 val @ (value_type (fits_in_16 ty)))
@@ -3293,6 +3279,8 @@
 (decl put_in_reg_zext64 (Value) Reg)
 (rule 3 (put_in_reg_zext64 (and (value_type ty) (u64_from_value val)))
       (imm (ty_ext64 ty) val))
+(rule 4 (put_in_reg_zext64 (sinkable_load_8 load))
+      (zext64_mem $I8 (sink_load load)))
 (rule 1 (put_in_reg_zext64 (and (value_type (gpr32_ty ty)) (sinkable_load load)))
       (zext64_mem ty (sink_load load)))
 (rule 0 (put_in_reg_zext64 val @ (value_type (gpr32_ty ty)))
@@ -3304,6 +3292,8 @@
 (decl put_in_reg_sext64 (Value) Reg)
 (rule 3 (put_in_reg_sext64 (and (value_type ty) (u64_from_signed_value val)))
       (imm (ty_ext64 ty) val))
+(rule 4 (put_in_reg_sext64 (sinkable_load_8 load))
+      (sext64_mem $I8 (sink_load load)))
 (rule 1 (put_in_reg_sext64 (and (value_type (gpr32_ty ty)) (sinkable_load load)))
       (sext64_mem ty (sink_load load)))
 (rule 0 (put_in_reg_sext64 val @ (value_type (gpr32_ty ty)))
diff --git a/cranelift/codegen/src/isa/s390x/lower.isle b/cranelift/codegen/src/isa/s390x/lower.isle
index 138f106ffd6a..d0915357e405 100644
--- a/cranelift/codegen/src/isa/s390x/lower.isle
+++ b/cranelift/codegen/src/isa/s390x/lower.isle
@@ -74,9 +74,9 @@
       (add_reg ty x y))
 
 ;; Add a register and a sign-extended register.
-(rule 8 (lower (iadd (fits_in_64 ty) x (sext32_value y)))
+(rule 2 (lower (iadd (fits_in_64 ty) x (sext32_value y)))
       (add_reg_sext32 ty x y))
-(rule 15 (lower (iadd (fits_in_64 ty) (sext32_value x) y))
+(rule 9 (lower (iadd (fits_in_64 ty) (sext32_value x) y))
       (add_reg_sext32 ty y x))
 
 ;; Add a register and an immediate.
@@ -103,13 +103,13 @@
 
 ;; Add a register and sign-extended memory.
 (rule 3 (lower (iadd (fits_in_64 ty) x (sinkable_sload16 y)))
-      (add_mem_sext16 ty x (sink_sload16 y)))
+      (add_mem_sext16 ty x (sink_load y)))
 (rule 10 (lower (iadd (fits_in_64 ty) (sinkable_sload16 x) y))
-      (add_mem_sext16 ty y (sink_sload16 x)))
-(rule 2 (lower (iadd (fits_in_64 ty) x (sinkable_sload32 y)))
-      (add_mem_sext32 ty x (sink_sload32 y)))
-(rule 9 (lower (iadd (fits_in_64 ty) (sinkable_sload32 x) y))
-      (add_mem_sext32 ty y (sink_sload32 x)))
+      (add_mem_sext16 ty y (sink_load x)))
+(rule 8 (lower (iadd (fits_in_64 ty) x (sinkable_sload32 y)))
+      (add_mem_sext32 ty x (sink_load y)))
+(rule 15 (lower (iadd (fits_in_64 ty) (sinkable_sload32 x) y))
+      (add_mem_sext32 ty y (sink_load x)))
 
 ;; Add two vector registers.
 (rule 1 (lower (iadd (vr128_ty ty) x y))
@@ -183,7 +183,7 @@
       (sub_reg ty x y))
 
 ;; Sub a register and a sign-extended register.
-(rule 8 (lower (isub (fits_in_64 ty) x (sext32_value y)))
+(rule 2 (lower (isub (fits_in_64 ty) x (sext32_value y)))
       (sub_reg_sext32 ty x y))
 
 ;; Sub a register and an immediate (using add of the negated value).
@@ -202,9 +202,9 @@
 
 ;; Sub a register and sign-extended memory.
 (rule 3 (lower (isub (fits_in_64 ty) x (sinkable_sload16 y)))
-      (sub_mem_sext16 ty x (sink_sload16 y)))
-(rule 2 (lower (isub (fits_in_64 ty) x (sinkable_sload32 y)))
-      (sub_mem_sext32 ty x (sink_sload32 y)))
+      (sub_mem_sext16 ty x (sink_load y)))
+(rule 8 (lower (isub (fits_in_64 ty) x (sinkable_sload32 y)))
+      (sub_mem_sext32 ty x (sink_load y)))
 
 ;; Sub two vector registers.
 (rule 1 (lower (isub (vr128_ty ty) x y))
@@ -411,9 +411,9 @@
       (mul_reg ty x y))
 
 ;; Multiply a register and a sign-extended register.
-(rule 8 (lower (imul (fits_in_64 ty) x (sext32_value y)))
+(rule 2 (lower (imul (fits_in_64 ty) x (sext32_value y)))
       (mul_reg_sext32 ty x y))
-(rule 15 (lower (imul (fits_in_64 ty) (sext32_value x) y))
+(rule 9 (lower (imul (fits_in_64 ty) (sext32_value x) y))
       (mul_reg_sext32 ty y x))
 
 ;; Multiply a register and an immediate.
@@ -440,13 +440,13 @@
 
 ;; Multiply a register and sign-extended memory.
 (rule 3 (lower (imul (fits_in_64 ty) x (sinkable_sload16 y)))
-      (mul_mem_sext16 ty x (sink_sload16 y)))
+      (mul_mem_sext16 ty x (sink_load y)))
 (rule 10 (lower (imul (fits_in_64 ty) (sinkable_sload16 x) y))
-      (mul_mem_sext16 ty y (sink_sload16 x)))
-(rule 2 (lower (imul (fits_in_64 ty) x (sinkable_sload32 y)))
-      (mul_mem_sext32 ty x (sink_sload32 y)))
-(rule 9 (lower (imul (fits_in_64 ty) (sinkable_sload32 x) y))
-      (mul_mem_sext32 ty y (sink_sload32 x)))
+      (mul_mem_sext16 ty y (sink_load x)))
+(rule 8 (lower (imul (fits_in_64 ty) x (sinkable_sload32 y)))
+      (mul_mem_sext32 ty x (sink_load y)))
+(rule 15 (lower (imul (fits_in_64 ty) (sinkable_sload32 x) y))
+      (mul_mem_sext32 ty y (sink_load x)))
 
 ;; Multiply two vector registers, using a helper.
 (decl vec_mul_impl (Type Reg Reg) Reg)
@@ -3015,94 +3015,6 @@
       (vec_elt_rev ty (vec_load ty (lower_address flags addr offset))))
 
 
-;;;; Rules for `uload8` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; 16- or 32-bit target types.
-(rule (lower (uload8 (gpr32_ty _ty) (mem_flags_data flags) addr offset))
-      (zext32_mem $I8 (lower_address flags addr offset)))
-
-;; 64-bit target types.
-(rule 1 (lower (uload8 (gpr64_ty _ty) (mem_flags_data flags) addr offset))
-      (zext64_mem $I8 (lower_address flags addr offset)))
-
-
-;;;; Rules for `sload8` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; 16- or 32-bit target types.
-(rule (lower (sload8 (gpr32_ty _ty) (mem_flags_data flags) addr offset))
-      (sext32_mem $I8 (lower_address flags addr offset)))
-
-;; 64-bit target types.
-(rule 1 (lower (sload8 (gpr64_ty _ty) (mem_flags_data flags) addr offset))
-      (sext64_mem $I8 (lower_address flags addr offset)))
-
-
-;;;; Rules for `uload16` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; 32-bit target type, big-endian source value.
-(rule 3 (lower (uload16 (gpr32_ty _ty) (mem_flags_data flags @ (bigendian)) addr offset))
-      (zext32_mem $I16 (lower_address flags addr offset)))
-
-;; 32-bit target type, little-endian source value (via explicit extension).
-(rule 1 (lower (uload16 (gpr32_ty _ty) (mem_flags_data flags @ (littleendian)) addr offset))
-      (let ((reg16 Reg (loadrev16 (lower_address flags addr offset))))
-        (zext32_reg $I16 reg16)))
-
-;; 64-bit target type, big-endian source value.
-(rule 4 (lower (uload16 (gpr64_ty _ty) (mem_flags_data flags @ (bigendian)) addr offset))
-      (zext64_mem $I16 (lower_address flags addr offset)))
-
-;; 64-bit target type, little-endian source value (via explicit extension).
-(rule 2 (lower (uload16 (gpr64_ty _ty) (mem_flags_data flags @ (littleendian)) addr offset))
-      (let ((reg16 Reg (loadrev16 (lower_address flags addr offset))))
-        (zext64_reg $I16 reg16)))
-
-
-;;;; Rules for `sload16` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; 32-bit target type, big-endian source value.
-(rule 2 (lower (sload16 (gpr32_ty _ty) (mem_flags_data flags @ (bigendian)) addr offset))
-      (sext32_mem $I16 (lower_address flags addr offset)))
-
-;; 32-bit target type, little-endian source value (via explicit extension).
-(rule 0 (lower (sload16 (gpr32_ty _ty) (mem_flags_data flags @ (littleendian)) addr offset))
-      (let ((reg16 Reg (loadrev16 (lower_address flags addr offset))))
-        (sext32_reg $I16 reg16)))
-
-;; 64-bit target type, big-endian source value.
-(rule 3 (lower (sload16 (gpr64_ty _ty) (mem_flags_data flags @ (bigendian)) addr offset))
-      (sext64_mem $I16 (lower_address flags addr offset)))
-
-;; 64-bit target type, little-endian source value (via explicit extension).
-(rule 1 (lower (sload16 (gpr64_ty _ty) (mem_flags_data flags @ (littleendian)) addr offset))
-      (let ((reg16 Reg (loadrev16 (lower_address flags addr offset))))
-        (sext64_reg $I16 reg16)))
-
-
-;;;; Rules for `uload32` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; 64-bit target type, big-endian source value.
-(rule 1 (lower (uload32 (gpr64_ty _ty) (mem_flags_data flags @ (bigendian)) addr offset))
-      (zext64_mem $I32 (lower_address flags addr offset)))
-
-;; 64-bit target type, little-endian source value (via explicit extension).
-(rule (lower (uload32 (gpr64_ty _ty) (mem_flags_data flags @ (littleendian)) addr offset))
-      (let ((reg32 Reg (loadrev32 (lower_address flags addr offset))))
-        (zext64_reg $I32 reg32)))
-
-
-;;;; Rules for `sload32` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; 64-bit target type, big-endian source value.
-(rule 1 (lower (sload32 (gpr64_ty _ty) (mem_flags_data flags @ (bigendian)) addr offset))
-      (sext64_mem $I32 (lower_address flags addr offset)))
-
-;; 64-bit target type, little-endian source value (via explicit extension).
-(rule (lower (sload32 (gpr64_ty _ty) (mem_flags_data flags @ (littleendian)) addr offset))
-      (let ((reg32 Reg (loadrev32 (lower_address flags addr offset))))
-        (sext64_reg $I32 reg32)))
-
-
 ;;;; Rules for `uloadNxM` and `sloadNxM` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ;; Unsigned 8->16 bit extension.
@@ -3357,10 +3269,6 @@
 
 ;;;; Rules for 8-bit integer stores ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-;; Main `istore8` lowering entry point, dispatching to the helper.
-(rule (lower (istore8 (mem_flags_data flags) val addr offset))
-      (side_effect (istore8_impl flags val addr offset)))
-
 ;; Helper to store 8-bit integer types.
 (decl istore8_impl (MemFlagsData Value Value Offset32) SideEffectNoResult)
 
@@ -3369,16 +3277,17 @@
       (store8 (put_in_reg val) (lower_address flags addr offset)))
 
 ;; Store 8-bit integer types, immediate input.
+;;
+;; The value may be narrowed by an `ireduce`, which is a no-op for an 8-bit
+;; store, so look through it to find the constant.
 (rule 1 (istore8_impl flags (u8_from_value imm) addr offset)
       (store8_imm imm (lower_address flags addr offset)))
+(rule 2 (istore8_impl flags (ireduce _ (u8_from_value imm)) addr offset)
+      (store8_imm imm (lower_address flags addr offset)))
 
 
 ;;;; Rules for 16-bit integer stores ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-;; Main `istore16` lowering entry point, dispatching to the helper.
-(rule (lower (istore16 (mem_flags_data flags) val addr offset))
-      (side_effect (istore16_impl flags val addr offset)))
-
 ;; Helper to store 16-bit integer types.
 (decl istore16_impl (MemFlagsData Value Value Offset32) SideEffectNoResult)
 
@@ -3391,20 +3300,23 @@
       (storerev16 (put_in_reg val) (lower_address flags addr offset)))
 
 ;; Store 16-bit big-endian integer types, immediate input.
+;;
+;; The value may be narrowed by an `ireduce`, which is a no-op for a 16-bit
+;; store, so look through it to find the constant.
 (rule 3 (istore16_impl flags @ (bigendian) (i16_from_value imm) addr offset)
       (store16_imm imm (lower_address flags addr offset)))
+(rule 5 (istore16_impl flags @ (bigendian) (ireduce _ (i16_from_value imm)) addr offset)
+      (store16_imm imm (lower_address flags addr offset)))
 
 ;; Store 16-bit little-endian integer types, immediate input.
 (rule 1 (istore16_impl flags @ (littleendian) (i16_from_swapped_value imm) addr offset)
       (store16_imm imm (lower_address flags addr offset)))
+(rule 4 (istore16_impl flags @ (littleendian) (ireduce _ (i16_from_swapped_value imm)) addr offset)
+      (store16_imm imm (lower_address flags addr offset)))
 
 
 ;;;; Rules for 32-bit integer stores ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-;; Main `istore32` lowering entry point, dispatching to the helper.
-(rule (lower (istore32 (mem_flags_data flags) val addr offset))
-      (side_effect (istore32_impl flags val addr offset)))
-
 ;; Helper to store 32-bit integer types.
 (decl istore32_impl (MemFlagsData Value Value Offset32) SideEffectNoResult)
 
@@ -3413,8 +3325,13 @@
       (store32 (put_in_reg val) (lower_address flags addr offset)))
 
 ;; Store 32-bit big-endian integer types, immediate input.
+;;
+;; The value may be narrowed by an `ireduce`, which is a no-op for a 32-bit
+;; store, so look through it to find the constant.
 (rule 2 (istore32_impl flags @ (bigendian) (i16_from_value imm) addr offset)
       (store32_simm16 imm (lower_address flags addr offset)))
+(rule 3 (istore32_impl flags @ (bigendian) (ireduce _ (i16_from_value imm)) addr offset)
+      (store32_simm16 imm (lower_address flags addr offset)))
 
 ;; Store 32-bit little-endian integer types.
 (rule 0 (istore32_impl flags @ (littleendian) val addr offset)
@@ -3898,9 +3815,9 @@
 
 ;; Compare (signed) a register and sign-extended memory.
 (rule 4 (icmps_val true x @ (value_type (fits_in_64 ty)) (sinkable_sload16 y))
-      (icmps_mem_sext16 ty x (sink_sload16 y)))
+      (icmps_mem_sext16 ty x (sink_load y)))
 (rule 4 (icmps_val true x @ (value_type (fits_in_64 ty)) (sinkable_sload32 y))
-      (icmps_mem_sext32 ty x (sink_sload32 y)))
+      (icmps_mem_sext32 ty x (sink_load y)))
 
 
 ;; Return a `ProducesBool` to implement unsigned integer comparisons.
@@ -3935,10 +3852,10 @@
 ;; address here, so we need to check whether the sinkable load matches this.
 (rule 3 (icmpu_val true x @ (value_type (fits_in_64 ty))
                  (sinkable_uload16 ld))
-      (if-let y (uload16_sym ld))
-      (icmpu_mem_zext16 ty x (sink_uload16 y)))
+      (if-let y (load_sym ld))
+      (icmpu_mem_zext16 ty x (sink_load y)))
 (rule 3 (icmpu_val true x @ (value_type (fits_in_64 ty)) (sinkable_uload32 y))
-      (icmpu_mem_zext32 ty x (sink_uload32 y)))
+      (icmpu_mem_zext32 ty x (sink_load y)))
 
 
 ;; Compare (signed) 128-bit integers on z17.
@@ -4400,11 +4317,11 @@
         (trap_if_impl (mask_as_cond 3) tc)))
 
 ;; Add a register an a zero-extended register.
-(rule 4 (lower (uadd_overflow_trap (fits_in_64 ty) x (zext32_value y) tc))
+(rule 1 (lower (uadd_overflow_trap (fits_in_64 ty) x (zext32_value y) tc))
       (with_flags
         (add_logical_reg_zext32_with_flags_paired ty x y)
         (trap_if_impl (mask_as_cond 3) tc)))
-(rule 8 (lower (uadd_overflow_trap (fits_in_64 ty) (zext32_value x) y tc))
+(rule 5 (lower (uadd_overflow_trap (fits_in_64 ty) (zext32_value x) y tc))
       (with_flags
         (add_logical_reg_zext32_with_flags_paired ty y x)
         (trap_if_impl (mask_as_cond 3) tc)))
@@ -4430,13 +4347,13 @@
         (trap_if_impl (mask_as_cond 3) tc)))
 
 ;; Add a register and zero-extended memory.
-(rule 1 (lower (uadd_overflow_trap (fits_in_64 ty) x (sinkable_uload32 y) tc))
+(rule 4 (lower (uadd_overflow_trap (fits_in_64 ty) x (sinkable_uload32 y) tc))
       (with_flags
-        (add_logical_mem_zext32_with_flags_paired ty x (sink_uload32 y))
+        (add_logical_mem_zext32_with_flags_paired ty x (sink_load y))
         (trap_if_impl (mask_as_cond 3) tc)))
-(rule 5 (lower (uadd_overflow_trap (fits_in_64 ty) (sinkable_uload32 x) y tc))
+(rule 8 (lower (uadd_overflow_trap (fits_in_64 ty) (sinkable_uload32 x) y tc))
       (with_flags
-        (add_logical_mem_zext32_with_flags_paired ty y (sink_uload32 x))
+        (add_logical_mem_zext32_with_flags_paired ty y (sink_load x))
         (trap_if_impl (mask_as_cond 3) tc)))
 
 ;;;; Rules for `uadd_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
diff --git a/cranelift/codegen/src/isa/x64/inst.isle b/cranelift/codegen/src/isa/x64/inst.isle
index 57639f6ff06f..89b8746e5d13 100644
--- a/cranelift/codegen/src/isa/x64/inst.isle
+++ b/cranelift/codegen/src/isa/x64/inst.isle
@@ -1636,7 +1636,6 @@
 (rule (value32_zeros_upper32 (bxor _ _ _)) true)
 (rule (value32_zeros_upper32 (ishl _ _ _)) true)
 (rule (value32_zeros_upper32 (ushr _ _ _)) true)
-(rule (value32_zeros_upper32 (uload32 _ _ _ _)) true)
 (rule -1 (value32_zeros_upper32 _) false)
 
 ;;;; Helpers for Working SSE tidbits ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
diff --git a/cranelift/codegen/src/isa/x64/lower.isle b/cranelift/codegen/src/isa/x64/lower.isle
index 8739c6fb6c27..9f7a5ab2fa21 100644
--- a/cranelift/codegen/src/isa/x64/lower.isle
+++ b/cranelift/codegen/src/isa/x64/lower.isle
@@ -3030,22 +3030,6 @@
 ;; no extension.
 (rule load_64_x64_movzx -1 (lower (load (ty_int_ref_64 ty) (little_or_native_endian flags) address offset))
       (x64_mov (to_amode flags address offset)))
-;; Also, certain scalar loads have a specific `from` width and extension kind
-;; (signed -> `sx`, zeroed -> `zx`). We overwrite the high bits of the 64-bit
-;; GPR even if the `to` type is smaller (e.g., 16-bits).
-(rule (lower (uload8 (is_gpr_type ty) (little_or_native_endian flags) address offset))
-      (x64_movzx (ExtMode.BQ) (to_amode flags address offset)))
-(rule (lower (sload8 (is_gpr_type ty) (little_or_native_endian flags) address offset))
-      (x64_movsx (ExtMode.BQ) (to_amode flags address offset)))
-(rule (lower (uload16 (is_gpr_type ty) (little_or_native_endian flags) address offset))
-      (x64_movzx (ExtMode.WQ) (to_amode flags address offset)))
-(rule (lower (sload16 (is_gpr_type ty) (little_or_native_endian flags) address offset))
-      (x64_movsx (ExtMode.WQ) (to_amode flags address offset)))
-(rule (lower (uload32 (is_gpr_type ty) (little_or_native_endian flags) address offset))
-      (x64_movzx (ExtMode.LQ) (to_amode flags address offset)))
-(rule (lower (sload32 (is_gpr_type ty) (little_or_native_endian flags) address offset))
-      (x64_movsx (ExtMode.LQ) (to_amode flags address offset)))
-
 ;; To load to XMM registers, we use the x64-specific instructions for each type.
 ;; For `$F32` and `$F64` this is important--we only want to load 32 or 64 bits.
 ;; But for the 128-bit types, this is not strictly necessary for performance but
@@ -3115,17 +3099,6 @@
       (side_effect
        (x64_movrm ty (to_amode flags address offset) value)))
 
-;; Explicit 8/16/32-bit opcodes.
-(rule (lower (istore8 (little_or_native_endian flags) value address offset))
-      (side_effect
-       (x64_movrm $I8 (to_amode flags address offset) value)))
-(rule (lower (istore16 (little_or_native_endian flags) value address offset))
-      (side_effect
-       (x64_movrm $I16 (to_amode flags address offset) value)))
-(rule (lower (istore32 (little_or_native_endian flags) value address offset))
-      (side_effect
-       (x64_movrm $I32 (to_amode flags address offset) value)))
-
 ;; IMM stores
 (rule 4 (lower (store (little_or_native_endian flags) value @ (value_type (fits_in_64 ty)) address offset))
       (if-let (i32_from_iconst imm) value)
diff --git a/cranelift/codegen/src/spec/inst_specs.isle b/cranelift/codegen/src/spec/inst_specs.isle
index 9730858fa683..f83c4f1abd10 100644
--- a/cranelift/codegen/src/spec/inst_specs.isle
+++ b/cranelift/codegen/src/spec/inst_specs.isle
@@ -522,92 +522,8 @@
     ((args (named Type) (named MemFlagsData) (named Value) (named Offset32)) (ret (bv 32)))
     ((args (named Type) (named MemFlagsData) (named Value) (named Offset32)) (ret (bv 64))))
 
-; Unsigned N-bit load
-(macro (uloadN clif_load size_bits p offset loaded_value result)
-    (and
-        ; Activate the CLIF load effect.
-        (clif_load_activate! clif_load size_bits p offset)
-
-        ; Loaded value is zero-extended.
-        (= result (zero_ext (widthof result) (conv_to size_bits loaded_value)))))
-
-; Unsigned 8-bit load
-(spec (uload8 ty flags p offset)
-    (modifies clif_load)
-    (modifies loaded_value)
-    (provide (uloadN! clif_load 8 p offset loaded_value result)
-             (= (:bits ty) (widthof result))))
-(instantiate uload8
-    ((args (named Type) (named MemFlagsData) (named Value) (named Offset32)) (ret (bv 16)))
-    ((args (named Type) (named MemFlagsData) (named Value) (named Offset32)) (ret (bv 32)))
-    ((args (named Type) (named MemFlagsData) (named Value) (named Offset32)) (ret (bv 64))))
-
-; Unsigned 16-bit load
-(spec (uload16 ty flags p offset)
-    (modifies clif_load)
-    (modifies loaded_value)
-    (provide (uloadN! clif_load 16 p offset loaded_value result)
-             (= (:bits ty) (widthof result))))
-(instantiate uload16
-    ((args (named Type) (named MemFlagsData) (named Value) (named Offset32)) (ret (bv 32)))
-    ((args (named Type) (named MemFlagsData) (named Value) (named Offset32)) (ret (bv 64))))
-
-; Unsigned 32-bit load
-(spec (uload32 ty flags p offset)
-    (modifies clif_load)
-    (modifies loaded_value)
-    (provide (uloadN! clif_load 32 p offset loaded_value result)
-             (= (:bits ty) (widthof result))))
-(instantiate uload32
-    ((args (named Type) (named MemFlagsData) (named Value) (named Offset32)) (ret (bv 64))))
-
-; Signed N-bit load
-(macro (sloadN clif_load size_bits p offset loaded_value result)
-    (and
-        ; Activate the CLIF load effect.
-        (clif_load_activate! clif_load size_bits p offset)
-
-        ; Loaded value is sign-extended.
-        (= result (sign_ext (widthof result) (conv_to size_bits loaded_value)))))
-
-; Signed 8-bit load
-(spec (sload8 ty flags p offset)
-    (modifies clif_load)
-    (modifies loaded_value)
-    (provide (sloadN! clif_load 8 p offset loaded_value result)
-             (= (:bits ty) (widthof result))))
-(instantiate sload8
-    ((args (named Type) (named MemFlagsData) (named Value) (named Offset32)) (ret (bv 16)))
-    ((args (named Type) (named MemFlagsData) (named Value) (named Offset32)) (ret (bv 32)))
-    ((args (named Type) (named MemFlagsData) (named Value) (named Offset32)) (ret (bv 64))))
-
-; Signed 16-bit load
-(spec (sload16 ty flags p offset)
-    (modifies clif_load)
-    (modifies loaded_value)
-    (provide (sloadN! clif_load 16 p offset loaded_value result)
-             (= (:bits ty) (widthof result))))
-(instantiate sload16
-    ((args (named Type) (named MemFlagsData) (named Value) (named Offset32)) (ret (bv 32)))
-    ((args (named Type) (named MemFlagsData) (named Value) (named Offset32)) (ret (bv 64))))
-
-; Signed 32-bit load
-(spec (sload32 ty flags p offset)
-    (modifies clif_load)
-    (modifies loaded_value)
-    (provide (sloadN! clif_load 32 p offset loaded_value result)
-             (= (:bits ty) (widthof result))))
-(instantiate sload32
-    ((args (named Type) (named MemFlagsData) (named Value) (named Offset32)) (ret (bv 64))))
-
 ; Loads have a large number of expansions and instantiations.
 (attr load (tag slow))
-(attr uload8 (tag slow))
-(attr uload16 (tag slow))
-(attr uload32 (tag slow))
-(attr sload8 (tag slow))
-(attr sload16 (tag slow))
-(attr sload32 (tag slow))
 
 ;; Store Instructions
 
@@ -645,35 +561,8 @@
     ((args (named MemFlagsData) (bv 32) (named Value) (named Offset32)) (ret (bv 1)))
     ((args (named MemFlagsData) (bv 64) (named Value) (named Offset32)) (ret (bv 1))))
 
-; 8-bit store
-(spec (istore8 flags value p offset)
-    (modifies clif_store)
-    (provide (store! clif_store flags (extract 7 0 value) p offset result)))
-(instantiate istore8
-    ((args (named MemFlagsData) (bv 16) (named Value) (named Offset32)) (ret (bv 1)))
-    ((args (named MemFlagsData) (bv 32) (named Value) (named Offset32)) (ret (bv 1)))
-    ((args (named MemFlagsData) (bv 64) (named Value) (named Offset32)) (ret (bv 1))))
-
-; 16-bit store
-(spec (istore16 flags value p offset)
-    (modifies clif_store)
-    (provide (store! clif_store flags (extract 15 0 value) p offset result)))
-(instantiate istore16
-    ((args (named MemFlagsData) (bv 32) (named Value) (named Offset32)) (ret (bv 1)))
-    ((args (named MemFlagsData) (bv 64) (named Value) (named Offset32)) (ret (bv 1))))
-
-; 32-bit store
-(spec (istore32 flags value p offset)
-    (modifies clif_store)
-    (provide (store! clif_store flags (extract 31 0 value) p offset result)))
-(instantiate istore32
-    ((args (named MemFlagsData) (bv 64) (named Value) (named Offset32)) (ret (bv 1))))
-
 ; Stores have a large number of expansions and instantiations.
 (attr store (tag slow))
-(attr istore8 (tag slow))
-(attr istore16 (tag slow))
-(attr istore32 (tag slow))
 
 ;; Floating Point Instructions
 
diff --git a/cranelift/codegen/src/spec/inst_tags.isle b/cranelift/codegen/src/spec/inst_tags.isle
index d7b7d4a9fc64..0dc2980f2aa5 100644
--- a/cranelift/codegen/src/spec/inst_tags.isle
+++ b/cranelift/codegen/src/spec/inst_tags.isle
@@ -27,30 +27,6 @@
     (tag wasm_category_stores)
     (tag wasm_proposal_mvp))
 
-(attr uload8
-    (tag wasm_category_loads)
-    (tag wasm_proposal_mvp))
-
-(attr uload16
-    (tag wasm_category_loads)
-    (tag wasm_proposal_mvp))
-
-(attr sload8
-    (tag wasm_category_loads)
-    (tag wasm_proposal_mvp))
-
-(attr sload16
-    (tag wasm_category_loads)
-    (tag wasm_proposal_mvp))
-
-(attr sload32
-    (tag wasm_category_loads)
-    (tag wasm_proposal_mvp))
-
-(attr uload32
-    (tag wasm_category_loads)
-    (tag wasm_proposal_mvp))
-
 (attr load
     (tag wasm_category_loads)
     (tag wasm_proposal_mvp))
@@ -59,18 +35,6 @@
     (tag wasm_category_stores)
     (tag wasm_proposal_mvp))
 
-(attr istore8
-    (tag wasm_category_stores)
-    (tag wasm_proposal_mvp))
-
-(attr istore16
-    (tag wasm_category_stores)
-    (tag wasm_proposal_mvp))
-
-(attr istore32
-    (tag wasm_category_stores)
-    (tag wasm_proposal_mvp))
-
 (attr f32const
     (tag wasm_category_const)
     (tag wasm_proposal_mvp))
diff --git a/cranelift/filetests/filetests/alias/endianness.clif b/cranelift/filetests/filetests/alias/endianness.clif
new file mode 100644
index 000000000000..7ff7f252e645
--- /dev/null
+++ b/cranelift/filetests/filetests/alias/endianness.clif
@@ -0,0 +1,197 @@
+test optimize precise-output
+set opt_level=speed
+target x86_64
+
+;; Byte order is part of a memory location's identity: two accesses to the same
+;; address with the same type but opposite byte order are *not* interchangeable,
+;; because forwarding a value from one to the other would drop a byte swap.
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Redundant-load elimination
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;; The big-endian load must not be replaced with the little-endian load's
+;; result.
+function %rle_mismatched_endianness(i64) -> i16, i16 {
+    region0 = 0 "heap"
+block0(v0: i64):
+    v1 = load.i16 region0 little v0
+    v2 = load.i16 region0 big v0
+    return v1, v2
+}
+
+; function %rle_mismatched_endianness(i64) -> i16, i16 fast {
+;     region0 = 0 "heap"
+;
+; block0(v0: i64):
+;     v1 = load.i16 little region0 v0
+;     v2 = load.i16 big region0 v0
+;     return v1, v2
+; }
+
+;; Same byte order: the second load is redundant and is removed.
+function %rle_matching_endianness(i64) -> i16, i16 {
+    region0 = 0 "heap"
+block0(v0: i64):
+    v1 = load.i16 region0 big v0
+    v2 = load.i16 region0 big v0
+    return v1, v2
+}
+
+; function %rle_matching_endianness(i64) -> i16, i16 fast {
+;     region0 = 0 "heap"
+;
+; block0(v0: i64):
+;     v1 = load.i16 big region0 v0
+;     return v1, v1
+; }
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Store-to-load forwarding
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;; The big-endian load must not be replaced with the little-endian store's data.
+function %stl_mismatched_endianness(i64, i16) -> i16 {
+    region0 = 0 "heap"
+block0(v0: i64, v1: i16):
+    store.i16 region0 little v1, v0
+    v2 = load.i16 region0 big v0
+    return v2
+}
+
+; function %stl_mismatched_endianness(i64, i16) -> i16 fast {
+;     region0 = 0 "heap"
+;
+; block0(v0: i64, v1: i16):
+;     store little region0 v1, v0
+;     v2 = load.i16 big region0 v0
+;     return v2
+; }
+
+;; Same byte order: the load is forwarded from the store.
+function %stl_matching_endianness(i64, i16) -> i16 {
+    region0 = 0 "heap"
+block0(v0: i64, v1: i16):
+    store.i16 region0 big v1, v0
+    v2 = load.i16 region0 big v0
+    return v2
+}
+
+; function %stl_matching_endianness(i64, i16) -> i16 fast {
+;     region0 = 0 "heap"
+;
+; block0(v0: i64, v1: i16):
+;     store big region0 v1, v0
+;     return v1
+; }
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Idempotent-store elimination
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;; Storing a big-endian load's result back with little-endian byte order writes
+;; the byte-swapped value to memory, so the store is not idempotent and must be
+;; kept.
+function %idempotent_store_mismatched_endianness(i64) {
+    region0 = 0 "heap"
+block0(v0: i64):
+    v1 = load.i16 region0 big v0
+    store.i16 region0 little v1, v0
+    return
+}
+
+; function %idempotent_store_mismatched_endianness(i64) fast {
+;     region0 = 0 "heap"
+;
+; block0(v0: i64):
+;     v1 = load.i16 big region0 v0
+;     store little region0 v1, v0
+;     return
+; }
+
+;; Same byte order: the store really is idempotent and is removed.
+function %idempotent_store_matching_endianness(i64) {
+    region0 = 0 "heap"
+block0(v0: i64):
+    v1 = load.i16 region0 big v0
+    store.i16 region0 big v1, v0
+    return
+}
+
+; function %idempotent_store_matching_endianness(i64) fast {
+;     region0 = 0 "heap"
+;
+; block0(v0: i64):
+;     v1 = load.i16 big region0 v0
+;     return
+; }
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Implicit (native) versus explicit byte order
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;; We do not resolve an unspecified byte order to the target's native byte
+;; order, so an access that leaves the byte order implicit never forwards into
+;; one that spells it out, even when they agree on this target. This is
+;; conservative: it costs an optimization, but is never wrong.
+function %rle_implicit_versus_explicit_endianness(i64) -> i16, i16 {
+    region0 = 0 "heap"
+block0(v0: i64):
+    v1 = load.i16 region0 v0
+    v2 = load.i16 region0 little v0
+    return v1, v2
+}
+
+; function %rle_implicit_versus_explicit_endianness(i64) -> i16, i16 fast {
+;     region0 = 0 "heap"
+;
+; block0(v0: i64):
+;     v1 = load.i16 region0 v0
+;     v2 = load.i16 little region0 v0
+;     return v1, v2
+; }
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Dead-store elimination
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;; Dead-store elimination does not care about byte order: both stores write
+;; exactly the same range of bytes, and the second one's bytes are the ones
+;; that survive regardless of the order within that range. So the first store
+;; is dead even though the two disagree about byte order.
+function %dead_store_mismatched_endianness(i64, i16, i16) {
+    region0 = 0 "heap"
+block0(v0: i64, v1: i16, v2: i16):
+    store.i16 region0 big v1, v0
+    store.i16 region0 little v2, v0
+    return
+}
+
+; function %dead_store_mismatched_endianness(i64, i16, i16) fast {
+;     region0 = 0 "heap"
+;
+; block0(v0: i64, v1: i16, v2: i16):
+;     store little region0 v2, v0
+;     return
+; }
+
+;; Removing a dead store whose byte order differs from its overwriter's must
+;; still roll the last-store state back to the version before the dead store,
+;; so that the overwriter is recognized as idempotent on reprocessing. Both
+;; stores should be gone here.
+function %dead_store_then_idempotent_store_mismatched_endianness(i64, i16) {
+    region0 = 0 "heap"
+block0(v0: i64, v1: i16):
+    v2 = load.i16 notrap region0 big v0
+    store.i16 region0 little v1, v0
+    store.i16 region0 big v2, v0
+    return
+}
+
+; function %dead_store_then_idempotent_store_mismatched_endianness(i64, i16) fast {
+;     region0 = 0 "heap"
+;
+; block0(v0: i64, v1: i16):
+;     v2 = load.i16 notrap big region0 v0
+;     return
+; }
diff --git a/cranelift/filetests/filetests/alias/extends.clif b/cranelift/filetests/filetests/alias/extends.clif
index 601d7392b39a..920acd0fb5a7 100644
--- a/cranelift/filetests/filetests/alias/extends.clif
+++ b/cranelift/filetests/filetests/alias/extends.clif
@@ -2,10 +2,10 @@ test alias-analysis
 set opt_level=speed
 target aarch64
 
-;; Test that extension modes are properly accounted for when deciding
-;; whether loads alias.
+;; Test that access widths are properly accounted for when deciding
+;; whether loads and stores alias.
 
-function %f0(i64 vmctx, i32) -> i32, i32, i32, i64, i64, i64 {
+function %f0(i64 vmctx, i32) -> i32, i8, i64, i64, i64 {
     gv0 = vmctx
     gv1 = load.i64 notrap readonly aligned gv0+8
 
@@ -16,28 +16,27 @@ block0(v0: i64, v1: i32):
     ;; though it does access the same address.
     v3 = load.i32 v2+8
 
-    ;; These loads must remain (must not be removed as redundant).
-    v4 = uload8.i32 v2+8
-    ; check: v4 = uload8.i32 v2+8
-    v5 = sload8.i32 v2+8
-    ; check: v5 = sload8.i32 v2+8
-    v6 = load.i64 v2+8
-    ; check: v6 = load.i64 v2+8
+    ;; These loads must remain (must not be removed as redundant), as
+    ;; they access different widths at the same address.
+    v4 = load.i8 v2+8
+    ; check: v4 = load.i8 v2+8
+    v5 = load.i64 v2+8
+    ; check: v5 = load.i64 v2+8
 
-    ;; 8-bit store only partially overwrites the address.
-    istore8 v6, v2+8
+    ;; An 8-bit store only partially overwrites the address.
+    v6 = ireduce.i8 v5
+    store v6, v2+8
 
     ;; This must not pick up the store data.
     v7 = load.i64 v2+8
     ; check: v7 = load.i64 v2+8
 
-    ;; Another store, this one non-truncating but actually using an
-    ;; `i8` value.
+    ;; Another 8-bit store, this one of an unrelated value.
     v8 = iconst.i8 123
     store.i8 v8, v2+8
 
     v9 = load.i64 v2+8
     ; check: v9 = load.i64 v2+8
 
-    return v3, v4, v5, v6, v7, v9
+    return v3, v4, v5, v7, v9
 }
diff --git a/cranelift/filetests/filetests/isa/aarch64/amodes.clif b/cranelift/filetests/filetests/isa/aarch64/amodes.clif
index 618f4d55a18f..863873497708 100644
--- a/cranelift/filetests/filetests/isa/aarch64/amodes.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/amodes.clif
@@ -279,7 +279,8 @@ function %f18(i64, i64, i64) -> i32 {
 block0(v0: i64, v1: i64, v2: i64):
   v3 = iconst.i32 -4098
   v6 = uextend.i64 v3
-  v5 = sload16.i32 v6+0
+  v7 = load.i16 v6+0
+  v5 = sextend.i32 v7
   return v5
 }
 
@@ -301,7 +302,8 @@ function %f19(i64, i64, i64) -> i32 {
 block0(v0: i64, v1: i64, v2: i64):
   v3 = iconst.i32 4098
   v6 = uextend.i64 v3
-  v5 = sload16.i32 v6+0
+  v7 = load.i16 v6+0
+  v5 = sextend.i32 v7
   return v5
 }
 
@@ -323,7 +325,8 @@ function %f20(i64, i64, i64) -> i32 {
 block0(v0: i64, v1: i64, v2: i64):
   v3 = iconst.i32 -4098
   v6 = sextend.i64 v3
-  v5 = sload16.i32 v6+0
+  v7 = load.i16 v6+0
+  v5 = sextend.i32 v7
   return v5
 }
 
@@ -345,7 +348,8 @@ function %f21(i64, i64, i64) -> i32 {
 block0(v0: i64, v1: i64, v2: i64):
   v3 = iconst.i32 4098
   v6 = sextend.i64 v3
-  v5 = sload16.i32 v6+0
+  v7 = load.i16 v6+0
+  v5 = sextend.i32 v7
   return v5
 }
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/big-endian.clif b/cranelift/filetests/filetests/isa/aarch64/big-endian.clif
index 9485ef753928..c2a945c19115 100644
--- a/cranelift/filetests/filetests/isa/aarch64/big-endian.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/big-endian.clif
@@ -73,37 +73,43 @@ function %f(i64) -> f64x2 {
 
 function %f(i64) -> i32 {
     block0(v0: i64):
-        v1 = uload8.i32 big v0+8
+        v2 = load.i8 big v0+8
+        v1 = uextend.i32 v2
         return v1
 }
 
 function %f(i64) -> i32 {
     block0(v0: i64):
-        v1 = sload8.i32 big v0+8
+        v2 = load.i8 big v0+8
+        v1 = sextend.i32 v2
         return v1
 }
 
 function %f(i64) -> i32 {
     block0(v0: i64):
-        v1 = uload16.i32 big v0+8
+        v2 = load.i16 big v0+8
+        v1 = uextend.i32 v2
         return v1
 }
 
 function %f(i64) -> i32 {
     block0(v0: i64):
-        v1 = sload16.i32 big v0+8
+        v2 = load.i16 big v0+8
+        v1 = sextend.i32 v2
         return v1
 }
 
 function %f(i64) -> i64 {
     block0(v0: i64):
-        v1 = uload32.i64 big v0+8
+        v2 = load.i32 big v0+8
+        v1 = uextend.i64 v2
         return v1
 }
 
 function %f(i64) -> i64 {
     block0(v0: i64):
-        v1 = sload32.i64 big v0+8
+        v2 = load.i32 big v0+8
+        v1 = sextend.i64 v2
         return v1
 }
 
@@ -139,19 +145,22 @@ function %f(i64, i128) {
 
 function %f(i64, i64) {
     block0(v0: i64, v1: i64):
-        istore8.i64 big v1, v0+8
+        v2 = ireduce.i8 v1
+        store big v2, v0+8
         return
 }
 
 function %f(i64, i64) {
     block0(v0: i64, v1: i64):
-        istore16.i64 big v1, v0+8
+        v2 = ireduce.i16 v1
+        store big v2, v0+8
         return
 }
 
 function %f(i64, i64) {
     block0(v0: i64, v1: i64):
-        istore32.i64 big v1, v0+8
+        v2 = ireduce.i32 v1
+        store big v2, v0+8
         return
 }
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/dead-notrap-load.clif b/cranelift/filetests/filetests/isa/aarch64/dead-notrap-load.clif
index bd17c43e9ce0..60c94e002ed8 100644
--- a/cranelift/filetests/filetests/isa/aarch64/dead-notrap-load.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/dead-notrap-load.clif
@@ -22,7 +22,8 @@ block0(v0: i64):
 
 function %dead_notrap_uload8(i64) {
 block0(v0: i64):
-    v1 = uload8.i32 notrap aligned v0
+    v2 = load.i8 notrap aligned v0
+    v1 = uextend.i32 v2
     return
 }
 
diff --git a/cranelift/filetests/filetests/isa/pulley64/load.clif b/cranelift/filetests/filetests/isa/pulley64/load.clif
index 248b77c5805c..331f25e5f9b2 100644
--- a/cranelift/filetests/filetests/isa/pulley64/load.clif
+++ b/cranelift/filetests/filetests/isa/pulley64/load.clif
@@ -18,7 +18,8 @@ block0(v0: i64):
 
 function %load_i8_s32(i64) -> i32 {
 block0(v0: i64):
-    v1 = sload8.i32 v0
+    v2 = load.i8 v0
+    v1 = sextend.i32 v2
     return v1
 }
 
@@ -33,7 +34,8 @@ block0(v0: i64):
 
 function %load_i8_u32(i64) -> i32 {
 block0(v0: i64):
-    v1 = uload8.i32 v0
+    v2 = load.i8 v0
+    v1 = uextend.i32 v2
     return v1
 }
 
@@ -63,7 +65,8 @@ block0(v0: i64):
 
 function %load_i16_s32(i64) -> i32 {
 block0(v0: i64):
-    v1 = sload16.i32 v0
+    v2 = load.i16 v0
+    v1 = sextend.i32 v2
     return v1
 }
 
@@ -78,7 +81,8 @@ block0(v0: i64):
 
 function %load_i16_u32(i64) -> i32 {
 block0(v0: i64):
-    v1 = uload16.i32 v0
+    v2 = load.i16 v0
+    v1 = uextend.i32 v2
     return v1
 }
 
@@ -108,7 +112,8 @@ block0(v0: i64):
 
 function %load_i32_s64(i64) -> i64 {
 block0(v0: i64):
-    v1 = sload32.i64 v0
+    v2 = load.i32 v0
+    v1 = sextend.i64 v2
     return v1
 }
 
@@ -125,7 +130,8 @@ block0(v0: i64):
 
 function %load_i32_u64(i64) -> i64 {
 block0(v0: i64):
-    v1 = uload32.i64 v0
+    v2 = load.i32 v0
+    v1 = uextend.i64 v2
     return v1
 }
 
@@ -172,7 +178,8 @@ block0(v0: i64):
 
 function %load_i8_s32_offset(i64) -> i32 {
 block0(v0: i64):
-    v1 = sload8.i32 v0+4
+    v2 = load.i8 v0+4
+    v1 = sextend.i32 v2
     return v1
 }
 
@@ -187,7 +194,8 @@ block0(v0: i64):
 
 function %load_i8_u32_offset(i64) -> i32 {
 block0(v0: i64):
-    v1 = uload8.i32 v0+4
+    v2 = load.i8 v0+4
+    v1 = uextend.i32 v2
     return v1
 }
 
@@ -217,7 +225,8 @@ block0(v0: i64):
 
 function %load_i16_s32_offset(i64) -> i32 {
 block0(v0: i64):
-    v1 = sload16.i32 v0+4
+    v2 = load.i16 v0+4
+    v1 = sextend.i32 v2
     return v1
 }
 
@@ -232,7 +241,8 @@ block0(v0: i64):
 
 function %load_i16_u32_offset(i64) -> i32 {
 block0(v0: i64):
-    v1 = uload16.i32 v0+4
+    v2 = load.i16 v0+4
+    v1 = uextend.i32 v2
     return v1
 }
 
@@ -262,7 +272,8 @@ block0(v0: i64):
 
 function %load_i32_s64_offset(i64) -> i64 {
 block0(v0: i64):
-    v1 = sload32.i64 v0+4
+    v2 = load.i32 v0+4
+    v1 = sextend.i64 v2
     return v1
 }
 
@@ -279,7 +290,8 @@ block0(v0: i64):
 
 function %load_i32_u64_offset(i64) -> i64 {
 block0(v0: i64):
-    v1 = uload32.i64 v0+4
+    v2 = load.i32 v0+4
+    v1 = uextend.i64 v2
     return v1
 }
 
@@ -326,7 +338,8 @@ block0(v0: i64):
 
 function %load_i8_s32_big_offset(i64) -> i32 {
 block0(v0: i64):
-    v1 = sload8.i32 v0+65536
+    v2 = load.i8 v0+65536
+    v1 = sextend.i32 v2
     return v1
 }
 
@@ -341,7 +354,8 @@ block0(v0: i64):
 
 function %load_i8_u32_big_offset(i64) -> i32 {
 block0(v0: i64):
-    v1 = uload8.i32 v0+65536
+    v2 = load.i8 v0+65536
+    v1 = uextend.i32 v2
     return v1
 }
 
@@ -371,7 +385,8 @@ block0(v0: i64):
 
 function %load_i16_s32_big_offset(i64) -> i32 {
 block0(v0: i64):
-    v1 = sload16.i32 v0+65536
+    v2 = load.i16 v0+65536
+    v1 = sextend.i32 v2
     return v1
 }
 
@@ -386,7 +401,8 @@ block0(v0: i64):
 
 function %load_i16_u32_big_offset(i64) -> i32 {
 block0(v0: i64):
-    v1 = uload16.i32 v0+65536
+    v2 = load.i16 v0+65536
+    v1 = uextend.i32 v2
     return v1
 }
 
@@ -416,7 +432,8 @@ block0(v0: i64):
 
 function %load_i32_s64_big_offset(i64) -> i64 {
 block0(v0: i64):
-    v1 = sload32.i64 v0+65536
+    v2 = load.i32 v0+65536
+    v1 = sextend.i64 v2
     return v1
 }
 
@@ -433,7 +450,8 @@ block0(v0: i64):
 
 function %load_i32_u64_big_offset(i64) -> i64 {
 block0(v0: i64):
-    v1 = uload32.i64 v0+65536
+    v2 = load.i32 v0+65536
+    v1 = uextend.i64 v2
     return v1
 }
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/amodes.clif b/cranelift/filetests/filetests/isa/riscv64/amodes.clif
index 5647bba2e01a..231223455670 100644
--- a/cranelift/filetests/filetests/isa/riscv64/amodes.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/amodes.clif
@@ -281,7 +281,8 @@ function %f18(i64, i64, i64) -> i32 {
 block0(v0: i64, v1: i64, v2: i64):
   v3 = iconst.i32 -4098
   v6 = uextend.i64 v3
-  v5 = sload16.i32 v6+0
+  v7 = load.i16 v6+0
+  v5 = sextend.i32 v7
   return v5
 }
 
@@ -307,7 +308,8 @@ function %f19(i64, i64, i64) -> i32 {
 block0(v0: i64, v1: i64, v2: i64):
   v3 = iconst.i32 4098
   v6 = uextend.i64 v3
-  v5 = sload16.i32 v6+0
+  v7 = load.i16 v6+0
+  v5 = sextend.i32 v7
   return v5
 }
 
@@ -333,7 +335,8 @@ function %f20(i64, i64, i64) -> i32 {
 block0(v0: i64, v1: i64, v2: i64):
   v3 = iconst.i32 -4098
   v6 = sextend.i64 v3
-  v5 = sload16.i32 v6+0
+  v7 = load.i16 v6+0
+  v5 = sextend.i32 v7
   return v5
 }
 
@@ -357,7 +360,8 @@ function %f21(i64, i64, i64) -> i32 {
 block0(v0: i64, v1: i64, v2: i64):
   v3 = iconst.i32 4098
   v6 = sextend.i64 v3
-  v5 = sload16.i32 v6+0
+  v7 = load.i16 v6+0
+  v5 = sextend.i32 v7
   return v5
 }
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/big-endian.clif b/cranelift/filetests/filetests/isa/riscv64/big-endian.clif
index e96839a329bf..9da978fb3154 100644
--- a/cranelift/filetests/filetests/isa/riscv64/big-endian.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/big-endian.clif
@@ -73,37 +73,43 @@ function %f(i64) -> f64x2 {
 
 function %f(i64) -> i32 {
     block0(v0: i64):
-        v1 = uload8.i32 big v0+8
+        v2 = load.i8 big v0+8
+        v1 = uextend.i32 v2
         return v1
 }
 
 function %f(i64) -> i32 {
     block0(v0: i64):
-        v1 = sload8.i32 big v0+8
+        v2 = load.i8 big v0+8
+        v1 = sextend.i32 v2
         return v1
 }
 
 function %f(i64) -> i32 {
     block0(v0: i64):
-        v1 = uload16.i32 big v0+8
+        v2 = load.i16 big v0+8
+        v1 = uextend.i32 v2
         return v1
 }
 
 function %f(i64) -> i32 {
     block0(v0: i64):
-        v1 = sload16.i32 big v0+8
+        v2 = load.i16 big v0+8
+        v1 = sextend.i32 v2
         return v1
 }
 
 function %f(i64) -> i64 {
     block0(v0: i64):
-        v1 = uload32.i64 big v0+8
+        v2 = load.i32 big v0+8
+        v1 = uextend.i64 v2
         return v1
 }
 
 function %f(i64) -> i64 {
     block0(v0: i64):
-        v1 = sload32.i64 big v0+8
+        v2 = load.i32 big v0+8
+        v1 = sextend.i64 v2
         return v1
 }
 
@@ -139,19 +145,22 @@ function %f(i64, i128) {
 
 function %f(i64, i64) {
     block0(v0: i64, v1: i64):
-        istore8.i64 big v1, v0+8
+        v2 = ireduce.i8 v1
+        store big v2, v0+8
         return
 }
 
 function %f(i64, i64) {
     block0(v0: i64, v1: i64):
-        istore16.i64 big v1, v0+8
+        v2 = ireduce.i16 v1
+        store big v2, v0+8
         return
 }
 
 function %f(i64, i64) {
     block0(v0: i64, v1: i64):
-        istore32.i64 big v1, v0+8
+        v2 = ireduce.i32 v1
+        store big v2, v0+8
         return
 }
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/dead-notrap-load.clif b/cranelift/filetests/filetests/isa/riscv64/dead-notrap-load.clif
index 76c2791a86c0..5aa5ab05e6ec 100644
--- a/cranelift/filetests/filetests/isa/riscv64/dead-notrap-load.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/dead-notrap-load.clif
@@ -22,7 +22,8 @@ block0(v0: i64):
 
 function %dead_notrap_uload8(i64) {
 block0(v0: i64):
-    v1 = uload8.i32 notrap aligned v0
+    v2 = load.i8 notrap aligned v0
+    v1 = uextend.i32 v2
     return
 }
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/issue-12811.clif b/cranelift/filetests/filetests/isa/riscv64/issue-12811.clif
index e691531521d2..1c2c4681b027 100644
--- a/cranelift/filetests/filetests/isa/riscv64/issue-12811.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/issue-12811.clif
@@ -1880,7 +1880,8 @@ block0(v0: i64):
     store little region0 v24511, v1786  
     v11743 = iconst.i64 0
     store little region0 v24490, v12137  
-    istore8 little region0 v24477, v12516  
+    v24644 = ireduce.i8 v24477
+    store little region0 v24644, v12516
     store little region0 v24488, v12540  
     store little region0 v24475, v13262  
     store little region0 v24502, v13268  
@@ -2983,7 +2984,8 @@ block82:
     store.i32 little region0 v24488, v17  
     store.i64 little region0 v24502, v12704  
     store.i64 little region0 v24502, v17  
-    istore8.i32 little region0 v24488, v12715  
+    v24645 = ireduce.i8 v24488
+    store little region0 v24645, v12715
     store.i32 little region0 v8, v12726  
     store.i32 little region0 v24488, v12732  
     store.i32 little region0 v24488, v12738  
@@ -3036,7 +3038,8 @@ block82:
     store.i64 little region0 v13070, v13075  
     store.i64 little region0 v24502, v13081  
     store.i64 little region0 v13090, v13095  
-    istore8.i32 little region0 v8, v13106  
+    v24646 = ireduce.i8 v8
+    store little region0 v24646, v13106
     store.i64 little region0 v24502, v13112  
     store.i32 little region0 v24488, v13130  
     store.i32 little region0 v8, v13135  
@@ -3107,7 +3110,8 @@ block82:
     store.i64 little region0 v13933, v13938  
     store.i64 little region0 v24502, v13944  
     store.i64 little region0 v24502, v13961  
-    istore8.i32 little region0 v8, v13966  
+    v24647 = ireduce.i8 v8
+    store little region0 v24647, v13966
     store.i32 little region0 v24488, v1786  
     store.i32 little region0 v13977, v13982  
     store.i64 little region0 v24502, v17  
@@ -3130,7 +3134,8 @@ block82:
     store.i64 little region0 v24502, v14155  
     store.i64 little region0 v24502, v14161  
     store.i64 little region0 v14173, v14178  
-    istore8.i32 little region0 v8, v14183  
+    v24648 = ireduce.i8 v8
+    store little region0 v24648, v14183
     store.i32 little region0 v24488, v17  
     store.i32 little region0 v24488, v14191  
     store.i64 little region0 v24502, v14207  
@@ -3152,7 +3157,8 @@ block82:
     store.i64 little region0 v24502, v14389  
     store.i64 little region0 v24502, v14395  
     store.i64 little region0 v24502, v1786  
-    istore8.i32 little region0 v24488, v14411  
+    v24649 = ireduce.i8 v24488
+    store little region0 v24649, v14411
     store.i32 little region0 v24488, v14429  
     store.i32 little region0 v24488, v14442  
     store.i64 little region0 v14449, v14454  
@@ -3172,7 +3178,8 @@ block82:
     store.i64 little region0 v24502, v14587  
     store.i64 little region0 v14597, v1786  
     store.i64 little region0 v14606, v14611  
-    istore8.i32 little region0 v8, v14616  
+    v24650 = ireduce.i8 v8
+    store little region0 v24650, v14616
     store.i32 little region0 v24488, v14630  
     store.i32 little region0 v24488, v14636  
     store.i32 little region0 v24488, v14642  
@@ -3204,7 +3211,8 @@ block82:
     store.i64 little region0 v24502, v14944  
     store.i32 little region0 v24488, v14950  
     store.i64 little region0 v24502, v15024  
-    istore8.i32 little region0 v8, v15030  
+    v24651 = ireduce.i8 v8
+    store little region0 v24651, v15030
     store.i32 little region0 v24488, v15036  
     store.i32 little region0 v24488, v15042  
     store.i64 little region0 v15056, v15061  
@@ -3219,7 +3227,8 @@ block82:
     store.i64 little region0 v24502, v15195  
     store.i64 little region0 v24502, v15202  
     store.i64 little region0 v24502, v15215  
-    istore8.i32 little region0 v24477, v15241  
+    v24652 = ireduce.i8 v24477
+    store little region0 v24652, v15241
     store.i32 little region0 v24488, v17  
     store.i64 little region0 v15285, v15290  
     store.i64 little region0 v15291, v15296  
@@ -3232,7 +3241,8 @@ block82:
     store.i32 little region0 v24488, v15374  
     store.i64 little region0 v24502, v15386  
     store.i64 little region0 v15454, v1786  
-    istore8.i32 little region0 v24488, v15463  
+    v24653 = ireduce.i8 v24488
+    store little region0 v24653, v15463
     store.i32 little region0 v24488, v15476  
     store.i32 little region0 v24488, v15482  
     store.i64 little region0 v24490, v24137  
@@ -3505,7 +3515,8 @@ block2:
 ;   li t0,3
 ;   sw t0,0(a1)
 ;   sd a2,0(a1)
-;   sb a3,0(a1)
+;   li t0,1
+;   sb t0,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
@@ -3618,9 +3629,9 @@ block2:
 ; block4:
 ;   j label5
 ; block5:
-;   li a1,1
-;   sext.w a1,a1
-;   trap_if user11##(a1 ne zero)
+;   li a2,1
+;   sext.w a2,a2
+;   trap_if user11##(a2 ne zero)
 ;   j label6
 ; block6:
 ;   j label7
@@ -3749,28 +3760,27 @@ block2:
 ;   sd zero,0(a3)
 ;   ld a3,[const(131)]
 ;   sd a3,0(a1)
-;   li a4,1
-;   ld a3,[const(130)]
-;   sw a4,0(a3)
-;   ld a3,[const(129)]
-;   sd a3,0(a1)
-;   ld a3,[const(128)]
-;   sd zero,0(a3)
+;   li a3,1
+;   ld a4,[const(130)]
+;   sw a3,0(a4)
+;   ld a4,[const(129)]
+;   sd a4,0(a1)
+;   ld a4,[const(128)]
+;   sd zero,0(a4)
 ;   sd zero,0(a1)
-;   li a3,0
 ;   sw zero,0(a1)
-;   ld a5,[const(127)]
-;   sd a5,0(a1)
+;   ld a4,[const(127)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(126)]
-;   sd a5,0(a1)
+;   ld a4,[const(126)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
-;   ld a5,[const(125)]
-;   ld a7,[const(124)]
-;   sd a5,0(a7)
+;   ld a4,[const(125)]
+;   ld a5,[const(124)]
+;   sd a4,0(a5)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
@@ -3778,30 +3788,30 @@ block2:
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(123)]
-;   sd a5,0(a1)
+;   ld a4,[const(123)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(122)]
-;   sd zero,0(a5)
+;   ld a4,[const(122)]
+;   sd zero,0(a4)
 ;   sw zero,0(a1)
-;   ld a5,[const(121)]
-;   sd a5,0(a1)
+;   ld a4,[const(121)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(120)]
-;   sd a5,0(a1)
+;   ld a4,[const(120)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(119)]
-;   sd zero,0(a5)
-;   ld a5,[const(118)]
-;   sd a5,0(a1)
+;   ld a4,[const(119)]
+;   sd zero,0(a4)
+;   ld a4,[const(118)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
@@ -3813,78 +3823,78 @@ block2:
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(117)]
-;   sd a5,0(a1)
+;   ld a4,[const(117)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(116)]
-;   sd a5,0(a1)
+;   ld a4,[const(116)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(115)]
-;   sd a5,0(a1)
+;   ld a4,[const(115)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(114)]
-;   sd a5,0(a1)
+;   ld a4,[const(114)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(113)]
-;   sd a5,0(a1)
-;   ld a5,[const(112)]
-;   ld a5,0(a5)
+;   ld a4,[const(113)]
+;   sd a4,0(a1)
+;   ld a4,[const(112)]
+;   ld a4,0(a4)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(111)]
-;   sd a5,0(a1)
+;   ld a4,[const(111)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(110)]
-;   sd a5,0(a1)
+;   ld a4,[const(110)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
-;   ld a5,[const(109)]
-;   sd zero,0(a5)
+;   ld a4,[const(109)]
+;   sd zero,0(a4)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(108)]
-;   sd a5,0(a1)
+;   ld a4,[const(108)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(107)]
-;   sd a5,0(a1)
+;   ld a4,[const(107)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(106)]
-;   sd a5,0(a1)
+;   ld a4,[const(106)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(105)]
-;   sd a5,0(a1)
+;   ld a4,[const(105)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(104)]
-;   sd a5,0(a1)
+;   ld a4,[const(104)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(103)]
-;   sd a5,0(a1)
+;   ld a4,[const(103)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
-;   ld a5,[const(102)]
-;   ld a5,0(a5)
+;   ld a4,[const(102)]
+;   ld a4,0(a4)
 ;   sw zero,0(a1)
-;   ld a5,[const(101)]
-;   sd a5,0(a1)
+;   ld a4,[const(101)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(100)]
-;   sd a5,0(a1)
+;   ld a4,[const(100)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
@@ -3892,99 +3902,99 @@ block2:
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(99)]
-;   sd a5,0(a1)
+;   ld a4,[const(99)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(98)]
-;   sd a5,0(a1)
+;   ld a4,[const(98)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(97)]
-;   sd a5,0(a1)
+;   ld a4,[const(97)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(96)]
-;   sd a5,0(a1)
+;   ld a4,[const(96)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(95)]
-;   sd a5,0(a1)
-;   ld a5,[const(94)]
-;   sd zero,0(a5)
+;   ld a4,[const(95)]
+;   sd a4,0(a1)
+;   ld a4,[const(94)]
+;   sd zero,0(a4)
 ;   sw zero,0(a1)
-;   ld a5,[const(93)]
-;   sd a5,0(a1)
+;   ld a4,[const(93)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(92)]
-;   sd a5,0(a1)
+;   ld a4,[const(92)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(91)]
-;   sd a5,0(a1)
+;   ld a4,[const(91)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(90)]
-;   sd a5,0(a1)
+;   ld a4,[const(90)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(89)]
-;   sd a5,0(a1)
+;   ld a4,[const(89)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(88)]
-;   sd a5,0(a1)
+;   ld a4,[const(88)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(87)]
-;   sd a5,0(a1)
+;   ld a4,[const(87)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(86)]
-;   sd a5,0(a1)
+;   ld a4,[const(86)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(85)]
-;   sd a5,0(a1)
+;   ld a4,[const(85)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(84)]
-;   sd a5,0(a1)
+;   ld a4,[const(84)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(83)]
-;   sd a5,0(a1)
+;   ld a4,[const(83)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(82)]
-;   sd a5,0(a1)
+;   ld a4,[const(82)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(81)]
-;   sd a5,0(a1)
+;   ld a4,[const(81)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(80)]
-;   sd a5,0(a1)
+;   ld a4,[const(80)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(79)]
-;   sd a5,0(a1)
+;   ld a4,[const(79)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(78)]
-;   sd a5,0(a1)
+;   ld a4,[const(78)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(77)]
-;   sd a5,0(a1)
+;   ld a4,[const(77)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
@@ -3992,22 +4002,22 @@ block2:
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(76)]
-;   sd a5,0(a1)
+;   ld a4,[const(76)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(75)]
-;   sd a5,0(a1)
+;   ld a4,[const(75)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(74)]
-;   sd a5,0(a1)
+;   ld a4,[const(74)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(73)]
-;   sd a5,0(a1)
+;   ld a4,[const(73)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(72)]
-;   sd a5,0(a1)
+;   ld a4,[const(72)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
@@ -4015,17 +4025,17 @@ block2:
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(71)]
-;   sd a5,0(a1)
+;   ld a4,[const(71)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(70)]
-;   sd a2,0(a5)
+;   ld a4,[const(70)]
+;   sd a2,0(a4)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(69)]
-;   sd zero,0(a5)
+;   ld a4,[const(69)]
+;   sd zero,0(a4)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
@@ -4039,35 +4049,35 @@ block2:
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
-;   ld a5,[const(68)]
-;   sd zero,0(a5)
+;   ld a4,[const(68)]
+;   sd zero,0(a4)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(67)]
-;   sd a2,0(a5)
-;   ld a5,[const(66)]
-;   sd a5,0(a1)
+;   ld a4,[const(67)]
+;   sd a2,0(a4)
+;   ld a4,[const(66)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(65)]
-;   sd a5,0(a1)
+;   ld a4,[const(65)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(64)]
-;   sd a5,0(a1)
+;   ld a4,[const(64)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(63)]
-;   sd a5,0(a1)
+;   ld a4,[const(63)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(62)]
-;   sd a2,0(a5)
+;   ld a4,[const(62)]
+;   sd a2,0(a4)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
@@ -4076,23 +4086,23 @@ block2:
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   lui a5,309522
-;   addi a5,a5,-111
-;   ld t2,[const(61)]
-;   sw a5,0(t2)
+;   lui a4,309522
+;   addi a4,a4,-111
+;   ld a5,[const(61)]
+;   sw a4,0(a5)
 ;   sw zero,0(a1)
-;   ld a5,[const(60)]
-;   sd a5,0(a1)
+;   ld a4,[const(60)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(59)]
-;   sd a5,0(a1)
+;   ld a4,[const(59)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(58)]
-;   sd a5,0(a1)
+;   ld a4,[const(58)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
@@ -4110,32 +4120,32 @@ block2:
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(57)]
-;   sd a5,0(a1)
+;   ld a4,[const(57)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(56)]
-;   sd a5,0(a1)
+;   ld a4,[const(56)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(55)]
-;   sd a5,0(a1)
+;   ld a4,[const(55)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(54)]
-;   sd a5,0(a1)
+;   ld a4,[const(54)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(53)]
-;   sd a5,0(a1)
+;   ld a4,[const(53)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(52)]
-;   sd a5,0(a1)
+;   ld a4,[const(52)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(51)]
-;   sd a5,0(a1)
+;   ld a4,[const(51)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
@@ -4147,60 +4157,60 @@ block2:
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(50)]
-;   sd a5,0(a1)
-;   ld a5,[const(49)]
-;   lw a5,0(a5)
+;   ld a4,[const(50)]
+;   sd a4,0(a1)
+;   ld a4,[const(49)]
+;   lw a4,0(a4)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(48)]
-;   sd a5,0(a1)
+;   ld a4,[const(48)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(47)]
-;   sd a5,0(a1)
+;   ld a4,[const(47)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(46)]
-;   sd a5,0(a1)
+;   ld a4,[const(46)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(45)]
-;   sd a5,0(a1)
+;   ld a4,[const(45)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(44)]
-;   sd a5,0(a1)
+;   ld a4,[const(44)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
-;   ld a5,[const(43)]
-;   sw zero,0(a5)
+;   ld a4,[const(43)]
+;   sw zero,0(a4)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(42)]
-;   sd a5,0(a1)
+;   ld a4,[const(42)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(41)]
-;   sd a5,0(a1)
-;   ld a5,[const(40)]
-;   sw a4,0(a5)
+;   ld a4,[const(41)]
+;   sd a4,0(a1)
+;   ld a4,[const(40)]
+;   sw a3,0(a4)
 ;   sw zero,0(a1)
-;   ld a5,[const(39)]
-;   sd a5,0(a1)
+;   ld a3,[const(39)]
+;   sd a3,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
-;   ld a5,[const(38)]
-;   sd a2,0(a5)
+;   ld a3,[const(38)]
+;   sd a2,0(a3)
 ;   sw zero,0(a1)
-;   ld a5,[const(37)]
-;   sd a5,0(a1)
+;   ld a3,[const(37)]
+;   sd a3,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
@@ -4209,15 +4219,15 @@ block2:
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
-;   sb a3,0(a1)
+;   sb zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(36)]
-;   sd a5,0(a1)
+;   ld a3,[const(36)]
+;   sd a3,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(35)]
-;   sd a5,0(a1)
+;   ld a3,[const(35)]
+;   sd a3,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
@@ -4225,71 +4235,71 @@ block2:
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(34)]
-;   sd a5,0(a1)
-;   ld a5,[const(33)]
-;   sd a2,0(a5)
+;   ld a3,[const(34)]
+;   sd a3,0(a1)
+;   ld a3,[const(33)]
+;   sd a2,0(a3)
 ;   sw zero,0(a1)
-;   ld a5,[const(32)]
-;   sd a5,0(a1)
+;   ld a3,[const(32)]
+;   sd a3,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(31)]
-;   sd a5,0(a1)
+;   ld a3,[const(31)]
+;   sd a3,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
-;   sb a3,0(a1)
+;   sb zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(30)]
-;   sd a5,0(a1)
+;   ld a3,[const(30)]
+;   sd a3,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(29)]
-;   sd a5,0(a1)
-;   ld a5,[const(28)]
-;   sd a2,0(a5)
+;   ld a3,[const(29)]
+;   sd a3,0(a1)
+;   ld a3,[const(28)]
+;   sd a2,0(a3)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
-;   lw a5,0(a1)
+;   lw a3,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(27)]
-;   sd a5,0(a1)
+;   ld a3,[const(27)]
+;   sd a3,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(26)]
-;   sd a5,0(a1)
+;   ld a3,[const(26)]
+;   sd a3,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(25)]
-;   sd a5,0(a1)
+;   ld a3,[const(25)]
+;   sd a3,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
-;   ld a5,[const(24)]
-;   sd a2,0(a5)
-;   ld a5,[const(23)]
-;   sd zero,0(a5)
+;   ld a3,[const(24)]
+;   sd a2,0(a3)
+;   ld a3,[const(23)]
+;   sd zero,0(a3)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
-;   sb a3,0(a1)
+;   sb zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(22)]
-;   sd a5,0(a1)
+;   ld a3,[const(22)]
+;   sd a3,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
-;   sb a3,0(a1)
+;   sb zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
@@ -4300,66 +4310,67 @@ block2:
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
-;   sb a3,0(a1)
+;   sb zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(21)]
-;   sd a5,0(a1)
+;   ld a3,[const(21)]
+;   sd a3,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(20)]
-;   sd a5,0(a1)
+;   ld a3,[const(20)]
+;   sd a3,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
-;   sb a3,0(a1)
+;   sb zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(19)]
-;   sd a5,0(a1)
+;   ld a3,[const(19)]
+;   sd a3,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(18)]
-;   sd a5,0(a1)
+;   ld a4,[const(18)]
+;   sd a4,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(17)]
-;   sd a5,0(a1)
+;   ld a3,[const(17)]
+;   sd a3,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(16)]
-;   sd a5,0(a1)
+;   ld a3,[const(16)]
+;   sd a3,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(15)]
-;   sd zero,0(a5)
-;   sb a3,0(a1)
+;   ld a3,[const(15)]
+;   sd zero,0(a3)
+;   sb zero,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(14)]
-;   sd a5,0(a1)
+;   ld a3,[const(14)]
+;   sd a3,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(13)]
-;   sd a5,0(a1)
+;   ld a3,[const(13)]
+;   sd a3,0(a1)
 ;   sw zero,0(a1)
-;   ld a5,[const(12)]
-;   sd a5,0(a1)
+;   ld a3,[const(12)]
+;   sd a3,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
-;   sb a4,0(a1)
+;   li a3,1
+;   sb a3,0(a1)
 ;   sw zero,0(a1)
-;   ld a4,[const(11)]
-;   sd a4,0(a1)
+;   ld a3,[const(11)]
+;   sd a3,0(a1)
 ;   sw zero,0(a1)
-;   ld a4,[const(10)]
-;   sd a4,0(a1)
+;   ld a3,[const(10)]
+;   sd a3,0(a1)
 ;   sw zero,0(a1)
-;   ld a4,[const(9)]
-;   sd a4,0(a1)
+;   ld a3,[const(9)]
+;   sd a3,0(a1)
 ;   sw zero,0(a1)
 ;   sd zero,0(a1)
-;   sb a3,0(a1)
+;   sb zero,0(a1)
 ;   sw zero,0(a1)
 ;   ld a3,[const(8)]
 ;   sd a2,0(a3)
@@ -4516,7 +4527,8 @@ block2:
 ;   c.li t0, 3
 ;   sw t0, 0(a1) ; trap: heap_oob
 ;   c.sd a2, 0(a1) ; trap: heap_oob
-;   sb a3, 0(a1) ; trap: heap_oob
+;   c.li t0, 1
+;   sb t0, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
@@ -4611,139 +4623,138 @@ block2:
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   c.sd a2, 0(a1) ; trap: heap_oob
-; block2: ; offset 0x2a6
+; block2: ; offset 0x2a8
 ;   lui a1, 0x6a64d
 ;   c.addi a1, 3
 ;   c.addiw a1, 0
 ;   beqz a1, 6
 ;   c.unimp ; trap: user11
-; block3: ; offset 0x2b4
+; block3: ; offset 0x2b6
 ;   lui a1, 0x259ad
 ;   addi a1, a1, -0x626
 ;   c.addiw a1, 0
 ;   beqz a1, 6
 ;   c.unimp ; trap: user11
-; block4: ; offset 0x2c4
-;   c.li a1, 1
-;   c.addiw a1, 0
-;   beqz a1, 6
+; block4: ; offset 0x2c6
+;   c.li a2, 1
+;   c.addiw a2, 0
+;   beqz a2, 6
 ;   c.unimp ; trap: user11
-; block5: ; offset 0x2ce
+; block5: ; offset 0x2d0
 ;   lui a1, 0x7c7d9
 ;   addi a1, a1, -0xc1
 ;   c.addiw a1, 0
 ;   beqz a1, 6
 ;   c.unimp ; trap: user11
-; block6: ; offset 0x2de
+; block6: ; offset 0x2e0
 ;   lui a1, 0x5b1f2
 ;   addi a1, a1, 0x6e3
 ;   c.addiw a1, 0
 ;   beqz a1, 6
 ;   c.unimp ; trap: user11
-; block7: ; offset 0x2ee
+; block7: ; offset 0x2f0
 ;   lui a1, 0x6f8d1
 ;   addi a1, a1, -0x144
 ;   c.addiw a1, 0
 ;   beqz a1, 6
 ;   c.unimp ; trap: user11
-; block8: ; offset 0x2fe
+; block8: ; offset 0x300
 ;   lui a1, 0x484e2
 ;   addi a1, a1, -0x478
 ;   c.addiw a1, 0
 ;   beqz a1, 6
 ;   c.unimp ; trap: user11
-; block9: ; offset 0x30e
+; block9: ; offset 0x310
 ;   lui a1, 0x110e5
 ;   addi a1, a1, -0x662
 ;   c.addiw a1, 0
 ;   beqz a1, 6
 ;   c.unimp ; trap: user11
-; block10: ; offset 0x31e
+; block10: ; offset 0x320
 ;   lui a1, 0x71fd2
 ;   addi a1, a1, 0x446
 ;   c.addiw a1, 0
 ;   beqz a1, 6
 ;   c.unimp ; trap: user11
-; block11: ; offset 0x32e
+; block11: ; offset 0x330
 ;   lui a1, 0x8237d
 ;   addi a1, a1, 0x5b7
 ;   c.addiw a1, 0
 ;   beqz a1, 6
 ;   c.unimp ; trap: user11
-; block12: ; offset 0x33e
+; block12: ; offset 0x340
 ;   auipc a2, 0
-;   ld a2, 0x292(a2)
+;   ld a2, 0x298(a2)
 ;   c.li a1, 0
 ;   c.sd a2, 0(a1) ; trap: heap_oob
 ;   auipc a2, 0
-;   ld a2, 0x28e(a2)
+;   ld a2, 0x294(a2)
 ;   sd zero, 0(a2) ; trap: heap_oob
 ;   auipc a2, 0
-;   ld a2, 0x28a(a2)
+;   ld a2, 0x290(a2)
 ;   c.sd a2, 0(a1) ; trap: heap_oob
 ;   c.li a2, 1
 ;   auipc a3, 0
-;   ld a3, 0x286(a3)
+;   ld a3, 0x28c(a3)
 ;   c.sd a2, 0(a3) ; trap: heap_oob
 ;   auipc a3, 0
-;   ld a3, 0x284(a3)
+;   ld a3, 0x28a(a3)
 ;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   auipc a3, 0
-;   ld a3, 0x282(a3)
+;   ld a3, 0x288(a3)
 ;   sd zero, 0(a3) ; trap: heap_oob
 ;   auipc a3, 0
-;   ld a3, 0x27e(a3)
+;   ld a3, 0x284(a3)
 ;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   auipc a3, 0
-;   ld a3, 0x27c(a3)
+;   ld a3, 0x282(a3)
 ;   sd zero, 0(a3) ; trap: heap_oob
 ;   auipc a3, 0
-;   ld a3, 0x278(a3)
+;   ld a3, 0x27e(a3)
 ;   sd zero, 0(a3) ; trap: heap_oob
 ;   auipc a3, 0
-;   ld a3, 0x274(a3)
+;   ld a3, 0x27a(a3)
 ;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   auipc a3, 0
-;   ld a3, 0x272(a3)
+;   ld a3, 0x278(a3)
 ;   c.sd a2, 0(a3) ; trap: heap_oob
 ;   auipc a3, 0
-;   ld a3, 0x270(a3)
+;   ld a3, 0x276(a3)
 ;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   auipc a3, 0
-;   ld a3, 0x26e(a3)
+;   ld a3, 0x274(a3)
 ;   sd zero, 0(a3) ; trap: heap_oob
 ;   auipc a3, 0
-;   ld a3, 0x26a(a3)
-;   c.sd a3, 0(a1) ; trap: heap_oob
-;   c.li a4, 1
-;   auipc a3, 0
-;   ld a3, 0x266(a3)
-;   c.sw a4, 0(a3) ; trap: heap_oob
-;   auipc a3, 0
-;   ld a3, 0x264(a3)
+;   ld a3, 0x270(a3)
 ;   c.sd a3, 0(a1) ; trap: heap_oob
-;   auipc a3, 0
-;   ld a3, 0x262(a3)
-;   sd zero, 0(a3) ; trap: heap_oob
+;   c.li a3, 1
+;   auipc a4, 0
+;   ld a4, 0x26c(a4)
+;   c.sw a3, 0(a4) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x26a(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x268(a4)
+;   sd zero, 0(a4) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
-;   c.li a3, 0
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x254(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x25c(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x24e(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x256(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x244(a4)
 ;   auipc a5, 0
-;   ld a5, 0x23c(a5)
-;   auipc a7, 0
-;   ld a7, 0x23c(a7)
-;   sd a5, 0(a7) ; trap: heap_oob
+;   ld a5, 0x244(a5)
+;   c.sd a4, 0(a5) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
@@ -4751,36 +4762,36 @@ block2:
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x21c(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x226(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x206(a5)
-;   sd zero, 0(a5) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x210(a4)
+;   sd zero, 0(a4) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x1fe(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x208(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x1e8(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x1f2(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x1e2(a5)
-;   sd zero, 0(a5) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x1de(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x1ec(a4)
+;   sd zero, 0(a4) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x1e8(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
@@ -4792,66 +4803,70 @@ block2:
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x1b0(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x1ba(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x1aa(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x1b4(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x19c(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x1a6(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x196(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x1a0(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x190(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x18e(a5)
-;   c.ld a5, 0(a5) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x19a(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x198(a4)
+;   c.ld a4, 0(a4) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x184(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x18e(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x17e(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x188(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x164(a5)
-;   sd zero, 0(a5) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x16e(a4)
+;   sd zero, 0(a4) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x150(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x15a(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x14a(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x154(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x13c(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
-;   c.j 0x13a
+;   auipc a4, 0
+;   ld a4, 0x146(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
+;   sw zero, 0(a1) ; trap: heap_oob
+;   c.j 0x140
+;   c.unimp
+;   c.unimp
+;   c.unimp
 ;   c.lw a2, 0xc(a4)
 ;   c.sd s0, 0x70(s0)
 ;   c.slli a7, 1
@@ -4998,37 +5013,36 @@ block2:
 ;   .byte 0xbf, 0x7f
 ;   c.fsdsp ft7, 0x180(sp)
 ;   c.bnez a1, 0x3c
-;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x10c(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x108(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0xfe(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0xfa(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0xf8(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0xf4(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0xe6(a5)
-;   c.ld a5, 0(a5) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0xe2(a4)
+;   c.ld a4, 0(a4) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0xe0(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0xdc(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0xd2(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0xce(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
@@ -5036,41 +5050,40 @@ block2:
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0xb4(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0xb0(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0xae(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0xaa(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x98(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x94(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x92(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x8e(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x8c(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x8a(a5)
-;   sd zero, 0(a5) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x88(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x86(a4)
+;   sd zero, 0(a4) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x82(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x7e(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
-;   sw zero, 0(a1) ; trap: heap_oob
 ;   c.j 0x6c
 ;   c.unimp
 ;   c.slli s10, 0x39
@@ -5122,65 +5135,68 @@ block2:
 ;   c.add t4, s9
 ;   c.sw a5, 0(s1)
 ;   c.fld fa4, 0x60(a2)
-;   auipc a5, 0
-;   ld a5, 0xd8(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0xd2(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0xdc(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
+;   sw zero, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0xd6(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0xbc(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0xc0(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0xae(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0xb2(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0xa0(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0xa4(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x9a(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x9e(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x94(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x98(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x7e(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x82(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x68(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x6c(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x62(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x66(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x5c(a5)
-;   c.j 0x5c
+;   auipc a4, 0
+;   ld a4, 0x60(a4)
+;   c.j 0x60
+;   c.unimp
+;   c.unimp
 ;   c.unimp
 ;   .byte 0xac, 0x88
 ;   c.mv a7, a0
@@ -5224,38 +5240,35 @@ block2:
 ;   .byte 0xd7, 0x0b
 ;   c.fldsp fs5, 0x120(sp)
 ;   c.li s8, 0x1d
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x6a(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x62(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x64(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x5c(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x56(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x4e(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x50(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x48(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x4a(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x42(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   sd zero, 0(a1) ; trap: heap_oob
-;   c.j 0x30
-;   c.unimp
-;   c.unimp
+;   c.j 0x2c
 ;   c.unimp
 ;   c.fsd fa1, 0xb0(a4)
 ;   c.mv s9, s0
@@ -5275,24 +5288,27 @@ block2:
 ;   c.lwsp t4, 0xd0(sp)
 ;   .byte 0x4b, 0x75
 ;   c.beqz s0, 0xce
+;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x3c(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x40(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x36(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x3a(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x30(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x34(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x22(a5)
-;   c.j 0x22
+;   auipc a4, 0
+;   ld a4, 0x26(a4)
+;   c.j 0x26
+;   c.unimp
+;   c.unimp
 ;   c.sdsp t2, 0xe8(sp)
 ;   c.lui t0, 0xfffea
 ;   c.xor a3, s0
@@ -5307,30 +5323,34 @@ block2:
 ;   c.sw a4, 0x34(s0)
 ;   c.or a5, s0
 ;   c.sd a4, 0xc8(a1)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x2a(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x2a(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
-;   sw zero, 0(a1) ; trap: heap_oob
-;   c.j 0xc
+;   c.j 0x10
+;   c.unimp
+;   c.unimp
 ;   c.unimp
 ;   c.beqz a2, -0xe0
 ;   fnmadd.d fa1, fs5, fs3, ft2
 ;   .byte 0x23, 0xf3
-;   auipc a5, 0
-;   ld a5, 0x18(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x12(a5)
-;   c.j 0x12
+;   auipc a4, 0
+;   ld a4, 0x1c(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
+;   sw zero, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x16(a4)
+;   c.j 0x16
+;   c.unimp
+;   c.unimp
 ;   c.sw s0, 8(a0)
 ;   c.lwsp tp, 0xe8(sp)
 ;   c.j -0x662
@@ -5339,21 +5359,21 @@ block2:
 ;   c.beqz a5, 4
 ;   c.unimp
 ;   c.unimp
-;   c.sd a2, 0(a5) ; trap: heap_oob
+;   c.sd a2, 0(a4) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
-;   sw zero, 0(a1) ; trap: heap_oob
 ;   c.j 2
+;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0xc(a5)
+;   auipc a4, 0
+;   ld a4, 0xc(a4)
 ;   c.j 0xc
 ;   c.unimp
 ;   c.addiw a0, -0x14
 ;   c.fsdsp fa6, 0x150(sp)
 ;   c.unimp
 ;   c.unimp
-;   sd zero, 0(a5) ; trap: heap_oob
+;   sd zero, 0(a4) ; trap: heap_oob
 ;   c.j 2
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   c.j 2
@@ -5381,15 +5401,15 @@ block2:
 ;   c.j 2
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   c.j 2
-;   auipc a5, 0
-;   ld a5, 0xc(a5)
+;   auipc a4, 0
+;   ld a4, 0xc(a4)
 ;   c.j 0xc
 ;   c.unimp
 ;   c.beqz s0, 0x5e
 ;   c.sd a3, 0xb8(a2)
 ;   c.unimp
 ;   c.unimp
-;   sd zero, 0(a5) ; trap: heap_oob
+;   sd zero, 0(a4) ; trap: heap_oob
 ;   c.j 2
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   c.j 2
@@ -5401,28 +5421,28 @@ block2:
 ;   c.j 2
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   c.j 2
-;   auipc a5, 0
-;   ld a5, 0xc(a5)
+;   auipc a4, 0
+;   ld a4, 0xc(a4)
 ;   c.j 0xc
 ;   c.unimp
 ;   .byte 0x0b, 0xc8
 ;   fnmadd.s ft2, ft1, ft0, ft0, rtz
 ;   c.unimp
-;   c.sd a2, 0(a5) ; trap: heap_oob
+;   c.sd a2, 0(a4) ; trap: heap_oob
 ;   c.j 2
-;   auipc a5, 0
-;   ld a5, 0xc(a5)
+;   auipc a4, 0
+;   ld a4, 0xc(a4)
 ;   c.j 0xc
 ;   c.unimp
 ;   .byte 0x3b, 0x78
 ;   fnmadd.d ft10, fs2, ft11, fa7, rup
 ;   c.sd a0, 0x90(a2)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   c.j 2
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   c.j 2
-;   auipc a5, 0
-;   ld a5, 0xe(a5)
+;   auipc a4, 0
+;   ld a4, 0xe(a4)
 ;   c.j 0xe
 ;   c.unimp
 ;   c.unimp
@@ -5430,12 +5450,12 @@ block2:
 ;   c.lw a5, 0x68(s0)
 ;   .byte 0x23, 0x40
 ;   c.lw a4, 0x48(s0)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   c.j 2
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   c.j 2
-;   auipc a5, 0
-;   ld a5, 0xe(a5)
+;   auipc a4, 0
+;   ld a4, 0xe(a4)
 ;   c.j 0xe
 ;   c.unimp
 ;   c.unimp
@@ -5443,7 +5463,7 @@ block2:
 ;   c.beqz a1, 0x58
 ;   c.j -0x608
 ;   c.fsd fa5, 0x80(a3)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   c.j 2
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   c.j 2
@@ -5455,15 +5475,15 @@ block2:
 ;   c.j 2
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   c.j 2
-;   auipc a5, 0
-;   ld a5, 0xe(a5)
+;   auipc a4, 0
+;   ld a4, 0xe(a4)
 ;   c.j 0xe
 ;   c.unimp
 ;   c.unimp
 ;   .byte 0xab, 0x89
 ;   .byte 0x9b, 0x53
 ;   sw zero, 0x42(s6)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   c.j 2
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   c.j 2
@@ -5471,13 +5491,13 @@ block2:
 ;   c.j 2
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   c.j 2
-;   auipc a5, 0
-;   ld a5, 0xa(a5)
+;   auipc a4, 0
+;   ld a4, 0xa(a4)
 ;   c.j 0xa
 ;   fmadd.d ft10, fs11, ft10, fs8
 ;   c.unimp
 ;   c.unimp
-;   c.sd a2, 0(a5) ; trap: heap_oob
+;   c.sd a2, 0(a4) ; trap: heap_oob
 ;   c.j 2
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   c.j 2
@@ -5495,12 +5515,12 @@ block2:
 ;   c.j 2
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   c.j 2
-;   lui a5, 0x4b912
+;   lui a4, 0x4b912
 ;   c.j 2
-;   addi a5, a5, -0x6f
+;   addi a4, a4, -0x6f
 ;   c.j 2
-;   auipc t2, 0
-;   ld t2, 0x10(t2)
+;   auipc a5, 0
+;   ld a5, 0x10(a5)
 ;   c.j 0x10
 ;   c.unimp
 ;   c.unimp
@@ -5509,33 +5529,34 @@ block2:
 ;   c.beqz s1, -0x54
 ;   c.unimp
 ;   c.unimp
-;   sw a5, 0(t2) ; trap: heap_oob
+;   c.sw a4, 0(a5) ; trap: heap_oob
 ;   c.j 2
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   c.j 2
-;   auipc a5, 0
-;   ld a5, 0x14(a5)
-;   c.j 4
-;   c.unimp
+;   auipc a4, 0
+;   ld a4, 0x16(a4)
+;   c.j 2
 ;   auipc t6, 0
-;   jalr zero, t6, 0x10
+;   jalr zero, t6, 0x14
+;   c.unimp
+;   c.unimp
 ;   c.bnez s1, 0x40
 ;   c.add t6, s10
 ;   .byte 0x77, 0x2f
 ;   c.lwsp t1, 0xe8(sp)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x59a(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x59a(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x584(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x584(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
@@ -5553,39 +5574,39 @@ block2:
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x53e(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x53e(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x530(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x530(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x522(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x522(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x51c(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x51c(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x50e(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x50e(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x508(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x508(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x502(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x502(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
@@ -5597,74 +5618,74 @@ block2:
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x4d4(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x4d2(a5)
-;   c.lw a5, 0(a5) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x4d4(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x4d2(a4)
+;   c.lw a4, 0(a4) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x4c8(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x4c8(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x4c2(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x4c2(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x4bc(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x4bc(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x4a6(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x4a6(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x4a0(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x4a0(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x496(a5)
-;   sw zero, 0(a5) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x496(a4)
+;   sw zero, 0(a4) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x47e(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x47e(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x478(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x476(a5)
-;   c.sw a4, 0(a5) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x478(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x476(a4)
+;   c.sw a3, 0(a4) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x470(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x470(a3)
+;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x456(a5)
-;   c.sd a2, 0(a5) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x456(a3)
+;   c.sd a2, 0(a3) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x450(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x450(a3)
+;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
@@ -5673,17 +5694,17 @@ block2:
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
-;   sb a3, 0(a1) ; trap: heap_oob
+;   sb zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x41e(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x41e(a3)
+;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x418(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x418(a3)
+;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
@@ -5691,84 +5712,84 @@ block2:
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x3fa(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x3f8(a5)
-;   c.sd a2, 0(a5) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x3fa(a3)
+;   c.sd a3, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x3f8(a3)
+;   c.sd a2, 0(a3) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x3f2(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x3f2(a3)
+;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x3ec(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x3ec(a3)
+;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
-;   sb a3, 0(a1) ; trap: heap_oob
+;   sb zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x3d6(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x3d6(a3)
+;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x3c8(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x3c6(a5)
-;   c.sd a2, 0(a5) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x3c8(a3)
+;   c.sd a3, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x3c6(a3)
+;   c.sd a2, 0(a3) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
-;   c.lw a5, 0(a1) ; trap: heap_oob
+;   c.lw a3, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x3ae(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x3ae(a3)
+;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x3a0(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x3a0(a3)
+;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x39a(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x39a(a3)
+;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x380(a5)
-;   c.sd a2, 0(a5) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x37e(a5)
-;   sd zero, 0(a5) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x380(a3)
+;   c.sd a2, 0(a3) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x37e(a3)
+;   sd zero, 0(a3) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
-;   sb a3, 0(a1) ; trap: heap_oob
+;   sb zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x362(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x362(a3)
+;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
-;   sb a3, 0(a1) ; trap: heap_oob
+;   sb zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
@@ -5779,92 +5800,93 @@ block2:
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
-;   sb a3, 0(a1) ; trap: heap_oob
+;   sb zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x314(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x314(a3)
+;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x306(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x306(a3)
+;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
-;   sb a3, 0(a1) ; trap: heap_oob
+;   sb zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x2ec(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x2ec(a3)
+;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x2e6(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a4, 0
+;   ld a4, 0x2e6(a4)
+;   c.sd a4, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x2d0(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x2d0(a3)
+;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x2ca(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x2ca(a3)
+;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x2bc(a5)
-;   sd zero, 0(a5) ; trap: heap_oob
-;   sb a3, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x2bc(a3)
+;   sd zero, 0(a3) ; trap: heap_oob
+;   sb zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x2b0(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x2b0(a3)
+;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x2aa(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x2aa(a3)
+;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a5, 0
-;   ld a5, 0x2a4(a5)
-;   c.sd a5, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x2a4(a3)
+;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
-;   sb a4, 0(a1) ; trap: heap_oob
+;   c.li a3, 1
+;   sb a3, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a4, 0
-;   ld a4, 0x292(a4)
-;   c.sd a4, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x290(a3)
+;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a4, 0
-;   ld a4, 0x28c(a4)
-;   c.sd a4, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x28a(a3)
+;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   auipc a4, 0
-;   ld a4, 0x286(a4)
-;   c.sd a4, 0(a1) ; trap: heap_oob
+;   auipc a3, 0
+;   ld a3, 0x284(a3)
+;   c.sd a3, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
-;   sb a3, 0(a1) ; trap: heap_oob
+;   sb zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   auipc a3, 0
-;   ld a3, 0x274(a3)
+;   ld a3, 0x272(a3)
 ;   c.sd a2, 0(a3) ; trap: heap_oob
 ;   auipc a2, 0
-;   ld a2, 0x272(a2)
+;   ld a2, 0x270(a2)
 ;   c.sd a2, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   auipc a2, 0
-;   ld a2, 0x26c(a2)
+;   ld a2, 0x26a(a2)
 ;   c.sd a2, 0(a1) ; trap: heap_oob
 ;   auipc a2, 0
-;   ld a2, 0x26a(a2)
+;   ld a2, 0x268(a2)
 ;   c.lui a3, 4
 ;   addi a3, a3, -0x720
 ;   c.sd a2, 0(a3) ; trap: heap_oob
@@ -5873,7 +5895,7 @@ block2:
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   auipc a2, 0
-;   ld a2, 0x252(a2)
+;   ld a2, 0x250(a2)
 ;   c.lui a3, 4
 ;   addi a3, a3, -0x6a4
 ;   c.sd a2, 0(a3) ; trap: heap_oob
@@ -5882,7 +5904,7 @@ block2:
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   auipc a2, 0
-;   ld a2, 0x23a(a2)
+;   ld a2, 0x238(a2)
 ;   c.lui a3, 4
 ;   addi a3, a3, -0x5f0
 ;   c.sd a2, 0(a3) ; trap: heap_oob
@@ -5890,28 +5912,27 @@ block2:
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   auipc a2, 0
-;   ld a2, 0x226(a2)
+;   ld a2, 0x224(a2)
 ;   c.lui a3, 4
 ;   addi a3, a3, -0x638
 ;   c.sd a2, 0(a3) ; trap: heap_oob
 ;   auipc a2, 0
-;   ld a2, 0x21e(a2)
+;   ld a2, 0x21c(a2)
 ;   c.lui a3, 4
 ;   addi a3, a3, -0x640
 ;   c.sd a2, 0(a3) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   auipc a2, 0
-;   ld a2, 0x20e(a2)
+;   ld a2, 0x20c(a2)
 ;   c.lui a3, 4
 ;   addi a3, a3, -0x59c
 ;   c.sd a2, 0(a3) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
 ;   sd zero, 0(a1) ; trap: heap_oob
 ;   sw zero, 0(a1) ; trap: heap_oob
-;   c.j 6
-;   c.j 0xc
-;   c.unimp
+;   c.j 4
+;   c.j 0xa
 ;   auipc t6, 0
 ;   jalr zero, t6, 0x1f4
 ;   auipc t6, 0
@@ -6142,7 +6163,7 @@ block2:
 ;   c.addi4spn s0, sp, 0x84
 ;   andi a7, s11, -0x6ab
 ;   c.swsp t5, 0xb4(sp)
-; block13: ; offset 0x1488
+; block13: ; offset 0x1498
 ;   c.li a2, 1
 ;   c.li a3, 2
 ;   c.mv a1, a0
diff --git a/cranelift/filetests/filetests/isa/riscv64/zcb.clif b/cranelift/filetests/filetests/isa/riscv64/zcb.clif
index 411e80be7e72..a16f24c30ee3 100644
--- a/cranelift/filetests/filetests/isa/riscv64/zcb.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/zcb.clif
@@ -119,8 +119,10 @@ block0(v0: i16):
 
 function %c_lbu(i64) -> i16, i64 {
 block0(v0: i64):
-  v1 = uload8.i16 v0+0
-  v2 = uload8.i64 v0+3
+  v3 = load.i8 v0+0
+  v1 = uextend.i16 v3
+  v4 = load.i8 v0+3
+  v2 = uextend.i64 v4
   return v1, v2
 }
 
@@ -140,8 +142,10 @@ block0(v0: i64):
 
 function %c_lhu(i64) -> i32, i64 {
 block0(v0: i64):
-  v1 = uload16.i32 v0+0
-  v2 = uload16.i64 v0+2
+  v3 = load.i16 v0+0
+  v1 = uextend.i32 v3
+  v4 = load.i16 v0+2
+  v2 = uextend.i64 v4
   return v1, v2
 }
 
diff --git a/cranelift/filetests/filetests/isa/s390x/arithmetic.clif b/cranelift/filetests/filetests/isa/s390x/arithmetic.clif
index ae819219032d..45a9fd14a0e0 100644
--- a/cranelift/filetests/filetests/isa/s390x/arithmetic.clif
+++ b/cranelift/filetests/filetests/isa/s390x/arithmetic.clif
@@ -110,7 +110,8 @@ block0(v0: i64, v1: i64):
 
 function %iadd_i64_mem_ext16(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
-  v2 = sload16.i64 v1
+  v4 = load.i16 v1
+  v2 = sextend.i64 v4
   v3 = iadd.i64 v0, v2
   return v3
 }
@@ -127,7 +128,8 @@ block0(v0: i64, v1: i64):
 
 function %iadd_i64_mem_ext32(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
-  v2 = sload32.i64 v1
+  v4 = load.i32 v1
+  v2 = sextend.i64 v4
   v3 = iadd.i64 v0, v2
   return v3
 }
@@ -228,7 +230,8 @@ block0(v0: i32, v1: i64):
 
 function %iadd_i32_mem_ext16(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
-  v2 = sload16.i32 v1
+  v4 = load.i16 v1
+  v2 = sextend.i32 v4
   v3 = iadd.i32 v0, v2
   return v3
 }
@@ -245,7 +248,8 @@ block0(v0: i32, v1: i64):
 
 function %iadd_i32_memoff_ext16(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
-  v2 = sload16.i32 v1+4096
+  v4 = load.i16 v1+4096
+  v2 = sextend.i32 v4
   v3 = iadd.i32 v0, v2
   return v3
 }
@@ -470,7 +474,8 @@ block0(v0: i64, v1: i64):
 
 function %isub_i64_mem_ext16(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
-  v2 = sload16.i64 v1
+  v4 = load.i16 v1
+  v2 = sextend.i64 v4
   v3 = isub.i64 v0, v2
   return v3
 }
@@ -487,7 +492,8 @@ block0(v0: i64, v1: i64):
 
 function %isub_i64_mem_ext32(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
-  v2 = sload32.i64 v1
+  v4 = load.i32 v1
+  v2 = sextend.i64 v4
   v3 = isub.i64 v0, v2
   return v3
 }
@@ -588,7 +594,8 @@ block0(v0: i32, v1: i64):
 
 function %isub_i32_mem_ext16(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
-  v2 = sload16.i32 v1
+  v4 = load.i16 v1
+  v2 = sextend.i32 v4
   v3 = isub.i32 v0, v2
   return v3
 }
@@ -605,7 +612,8 @@ block0(v0: i32, v1: i64):
 
 function %isub_i32_memoff_ext16(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
-  v2 = sload16.i32 v1+4096
+  v4 = load.i16 v1+4096
+  v2 = sextend.i32 v4
   v3 = isub.i32 v0, v2
   return v3
 }
@@ -1058,7 +1066,8 @@ block0(v0: i64, v1: i64):
 
 function %imul_i64_mem_ext16(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
-  v2 = sload16.i64 v1
+  v4 = load.i16 v1
+  v2 = sextend.i64 v4
   v3 = imul.i64 v0, v2
   return v3
 }
@@ -1075,7 +1084,8 @@ block0(v0: i64, v1: i64):
 
 function %imul_i64_mem_ext32(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
-  v2 = sload32.i64 v1
+  v4 = load.i32 v1
+  v2 = sextend.i64 v4
   v3 = imul.i64 v0, v2
   return v3
 }
@@ -1176,7 +1186,8 @@ block0(v0: i32, v1: i64):
 
 function %imul_i32_mem_ext16(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
-  v2 = sload16.i32 v1
+  v4 = load.i16 v1
+  v2 = sextend.i32 v4
   v3 = imul.i32 v0, v2
   return v3
 }
@@ -1193,7 +1204,8 @@ block0(v0: i32, v1: i64):
 
 function %imul_i32_memoff_ext16(i32, i64) -> i32 {
 block0(v0: i32, v1: i64):
-  v2 = sload16.i32 v1+4096
+  v4 = load.i16 v1+4096
+  v2 = sextend.i32 v4
   v3 = imul.i32 v0, v2
   return v3
 }
diff --git a/cranelift/filetests/filetests/isa/s390x/dead-notrap-load.clif b/cranelift/filetests/filetests/isa/s390x/dead-notrap-load.clif
index 941492749165..f60e889e9956 100644
--- a/cranelift/filetests/filetests/isa/s390x/dead-notrap-load.clif
+++ b/cranelift/filetests/filetests/isa/s390x/dead-notrap-load.clif
@@ -22,7 +22,8 @@ block0(v0: i64):
 
 function %dead_notrap_uload8(i64) {
 block0(v0: i64):
-    v1 = uload8.i32 notrap aligned v0
+    v2 = load.i8 notrap aligned v0
+    v1 = uextend.i32 v2
     return
 }
 
diff --git a/cranelift/filetests/filetests/isa/s390x/icmp.clif b/cranelift/filetests/filetests/isa/s390x/icmp.clif
index bee448a674d0..bed13989df1f 100644
--- a/cranelift/filetests/filetests/isa/s390x/icmp.clif
+++ b/cranelift/filetests/filetests/isa/s390x/icmp.clif
@@ -130,7 +130,8 @@ block0(v0: i64):
 
 function %icmp_slt_i64_mem_ext16(i64, i64) -> i8 {
 block0(v0: i64, v1: i64):
-  v2 = sload16.i64 v1
+  v4 = load.i16 v1
+  v2 = sextend.i64 v4
   v3 = icmp.i64 slt v0, v2
   return v3
 }
@@ -153,7 +154,8 @@ function %icmp_slt_i64_sym_ext16(i64) -> i8 {
   gv0 = symbol colocated %sym
 block0(v0: i64):
   v1 = symbol_value.i64 gv0
-  v2 = sload16.i64 aligned v1
+  v4 = load.i16 aligned v1
+  v2 = sextend.i64 v4
   v3 = icmp.i64 slt v0, v2
   return v3
 }
@@ -174,7 +176,8 @@ block0(v0: i64):
 
 function %icmp_slt_i64_mem_ext32(i64, i64) -> i8 {
 block0(v0: i64, v1: i64):
-  v2 = sload32.i64 v1
+  v4 = load.i32 v1
+  v2 = sextend.i64 v4
   v3 = icmp.i64 slt v0, v2
   return v3
 }
@@ -197,7 +200,8 @@ function %icmp_slt_i64_sym_ext32(i64) -> i8 {
   gv0 = symbol colocated %sym
 block0(v0: i64):
   v1 = symbol_value.i64 gv0
-  v2 = sload32.i64 aligned v1
+  v4 = load.i32 aligned v1
+  v2 = sextend.i64 v4
   v3 = icmp.i64 slt v0, v2
   return v3
 }
@@ -345,7 +349,8 @@ block0(v0: i32):
 
 function %icmp_slt_i32_mem_ext16(i32, i64) -> i8 {
 block0(v0: i32, v1: i64):
-  v2 = sload16.i32 v1
+  v4 = load.i16 v1
+  v2 = sextend.i32 v4
   v3 = icmp.i32 slt v0, v2
   return v3
 }
@@ -366,7 +371,8 @@ block0(v0: i32, v1: i64):
 
 function %icmp_slt_i32_memoff_ext16(i32, i64) -> i8 {
 block0(v0: i32, v1: i64):
-  v2 = sload16.i32 v1+4096
+  v4 = load.i16 v1+4096
+  v2 = sextend.i32 v4
   v3 = icmp.i32 slt v0, v2
   return v3
 }
@@ -389,7 +395,8 @@ function %icmp_slt_i32_sym_ext16(i32) -> i8 {
   gv0 = symbol colocated %sym
 block0(v0: i32):
   v1 = symbol_value.i64 gv0
-  v2 = sload16.i32 aligned v1
+  v4 = load.i16 aligned v1
+  v2 = sextend.i32 v4
   v3 = icmp.i32 slt v0, v2
   return v3
 }
@@ -695,7 +702,8 @@ block0(v0: i64):
 
 function %icmp_ult_i64_mem_ext32(i64, i64) -> i8 {
 block0(v0: i64, v1: i64):
-  v2 = uload32.i64 v1
+  v4 = load.i32 v1
+  v2 = uextend.i64 v4
   v3 = icmp.i64 ult v0, v2
   return v3
 }
@@ -718,7 +726,8 @@ function %icmp_ult_i64_sym_ext32(i64) -> i8 {
   gv0 = symbol colocated %sym
 block0(v0: i64):
   v1 = symbol_value.i64 gv0
-  v2 = uload32.i64 aligned v1
+  v4 = load.i32 aligned v1
+  v2 = uextend.i64 v4
   v3 = icmp.i64 ult v0, v2
   return v3
 }
@@ -739,7 +748,8 @@ block0(v0: i64):
 
 function %icmp_ult_i64_mem_ext16(i64, i64) -> i8 {
 block0(v0: i64, v1: i64):
-  v2 = uload16.i64 v1
+  v4 = load.i16 v1
+  v2 = uextend.i64 v4
   v3 = icmp.i64 ult v0, v2
   return v3
 }
@@ -764,7 +774,8 @@ function %icmp_ult_i64_sym_ext16(i64) -> i8 {
   gv0 = symbol colocated %sym
 block0(v0: i64):
   v1 = symbol_value.i64 gv0
-  v2 = uload16.i64 aligned v1
+  v4 = load.i16 aligned v1
+  v2 = uextend.i64 v4
   v3 = icmp.i64 ult v0, v2
   return v3
 }
@@ -891,7 +902,8 @@ block0(v0: i32):
 
 function %icmp_ult_i32_mem_ext16(i32, i64) -> i8 {
 block0(v0: i32, v1: i64):
-  v2 = uload16.i32 v1
+  v4 = load.i16 v1
+  v2 = uextend.i32 v4
   v3 = icmp.i32 ult v0, v2
   return v3
 }
@@ -916,7 +928,8 @@ function %icmp_ult_i32_sym_ext16(i32) -> i8 {
   gv0 = symbol colocated %sym
 block0(v0: i32):
   v1 = symbol_value.i64 gv0
-  v2 = uload16.i32 aligned v1
+  v4 = load.i16 aligned v1
+  v2 = uextend.i32 v4
   v3 = icmp.i32 ult v0, v2
   return v3
 }
diff --git a/cranelift/filetests/filetests/isa/s390x/load-arch15.clif b/cranelift/filetests/filetests/isa/s390x/load-arch15.clif
index 54757e867774..e0313463df83 100644
--- a/cranelift/filetests/filetests/isa/s390x/load-arch15.clif
+++ b/cranelift/filetests/filetests/isa/s390x/load-arch15.clif
@@ -10,7 +10,8 @@ block0(v0: i64, v1: i32):
   v5 = uextend.i64 v4
   v6 = ishl v5, v2
   v7 = iadd v0, v6
-  v8 = uload8.i64 v7
+  v9 = load.i8 v7
+  v8 = uextend.i64 v9
   return v8
 }
 
@@ -36,7 +37,8 @@ block0(v0: i64, v1: i32):
   v5 = sextend.i64 v4
   v6 = ishl v5, v2
   v7 = iadd v0, v6
-  v8 = uload8.i64 v7
+  v9 = load.i8 v7
+  v8 = uextend.i64 v9
   return v8
 }
 
@@ -60,7 +62,8 @@ block0(v0: i64, v1: i32):
   v3 = uextend.i64 v1
   v4 = ishl v3, v2
   v5 = iadd v0, v4
-  v6 = uload8.i64 v5+1000
+  v7 = load.i8 v5+1000
+  v6 = uextend.i64 v7
   return v6
 }
 
diff --git a/cranelift/filetests/filetests/isa/s390x/load-little.clif b/cranelift/filetests/filetests/isa/s390x/load-little.clif
index 4f10a4e941a3..e064a81d3074 100644
--- a/cranelift/filetests/filetests/isa/s390x/load-little.clif
+++ b/cranelift/filetests/filetests/isa/s390x/load-little.clif
@@ -39,7 +39,8 @@ block0:
 
 function %uload8_i64(i64) -> i64 {
 block0(v0: i64):
-  v1 = uload8.i64 little v0
+  v2 = load.i8 little v0
+  v1 = uextend.i64 v2
   return v1
 }
 
@@ -55,7 +56,8 @@ block0(v0: i64):
 
 function %sload8_i64(i64) -> i64 {
 block0(v0: i64):
-  v1 = sload8.i64 little v0
+  v2 = load.i8 little v0
+  v1 = sextend.i64 v2
   return v1
 }
 
@@ -71,27 +73,29 @@ block0(v0: i64):
 
 function %uload16_i64(i64) -> i64 {
 block0(v0: i64):
-  v1 = uload16.i64 little v0
+  v2 = load.i16 little v0
+  v1 = uextend.i64 v2
   return v1
 }
 
 ; VCode:
 ; block0:
-;   lrvh %r2, 0(%r2)
-;   llghr %r2, %r2
+;   lrvh %r3, 0(%r2)
+;   llghr %r2, %r3
 ;   br %r14
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   lrvh %r2, 0(%r2) ; trap: heap_oob
-;   llghr %r2, %r2
+;   lrvh %r3, 0(%r2) ; trap: heap_oob
+;   llghr %r2, %r3
 ;   br %r14
 
 function %uload16_i64_sym() -> i64 {
   gv0 = symbol colocated %sym
 block0:
   v0 = symbol_value.i64 gv0
-  v1 = uload16.i64 aligned little v0
+  v2 = load.i16 aligned little v0
+  v1 = uextend.i64 v2
   return v1
 }
 
@@ -110,27 +114,29 @@ block0:
 
 function %sload16_i64(i64) -> i64 {
 block0(v0: i64):
-  v1 = sload16.i64 little v0
+  v2 = load.i16 little v0
+  v1 = sextend.i64 v2
   return v1
 }
 
 ; VCode:
 ; block0:
-;   lrvh %r2, 0(%r2)
-;   lghr %r2, %r2
+;   lrvh %r3, 0(%r2)
+;   lghr %r2, %r3
 ;   br %r14
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   lrvh %r2, 0(%r2) ; trap: heap_oob
-;   lghr %r2, %r2
+;   lrvh %r3, 0(%r2) ; trap: heap_oob
+;   lghr %r2, %r3
 ;   br %r14
 
 function %sload16_i64_sym() -> i64 {
   gv0 = symbol colocated %sym
 block0:
   v0 = symbol_value.i64 gv0
-  v1 = sload16.i64 aligned little v0
+  v2 = load.i16 aligned little v0
+  v1 = sextend.i64 v2
   return v1
 }
 
@@ -149,27 +155,29 @@ block0:
 
 function %uload32_i64(i64) -> i64 {
 block0(v0: i64):
-  v1 = uload32.i64 little v0
+  v2 = load.i32 little v0
+  v1 = uextend.i64 v2
   return v1
 }
 
 ; VCode:
 ; block0:
-;   lrv %r2, 0(%r2)
-;   llgfr %r2, %r2
+;   lrv %r3, 0(%r2)
+;   llgfr %r2, %r3
 ;   br %r14
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   lrv %r2, 0(%r2) ; trap: heap_oob
-;   llgfr %r2, %r2
+;   lrv %r3, 0(%r2) ; trap: heap_oob
+;   llgfr %r2, %r3
 ;   br %r14
 
 function %uload32_i64_sym() -> i64 {
   gv0 = symbol colocated %sym
 block0:
   v0 = symbol_value.i64 gv0
-  v1 = uload32.i64 aligned little v0
+  v2 = load.i32 aligned little v0
+  v1 = uextend.i64 v2
   return v1
 }
 
@@ -188,27 +196,29 @@ block0:
 
 function %sload32_i64(i64) -> i64 {
 block0(v0: i64):
-  v1 = sload32.i64 little v0
+  v2 = load.i32 little v0
+  v1 = sextend.i64 v2
   return v1
 }
 
 ; VCode:
 ; block0:
-;   lrv %r2, 0(%r2)
-;   lgfr %r2, %r2
+;   lrv %r3, 0(%r2)
+;   lgfr %r2, %r3
 ;   br %r14
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   lrv %r2, 0(%r2) ; trap: heap_oob
-;   lgfr %r2, %r2
+;   lrv %r3, 0(%r2) ; trap: heap_oob
+;   lgfr %r2, %r3
 ;   br %r14
 
 function %sload32_i64_sym() -> i64 {
   gv0 = symbol colocated %sym
 block0:
   v0 = symbol_value.i64 gv0
-  v1 = sload32.i64 aligned little v0
+  v2 = load.i32 aligned little v0
+  v1 = sextend.i64 v2
   return v1
 }
 
@@ -262,7 +272,8 @@ block0:
 
 function %uload8_i32(i64) -> i32 {
 block0(v0: i64):
-  v1 = uload8.i32 little v0
+  v2 = load.i8 little v0
+  v1 = uextend.i32 v2
   return v1
 }
 
@@ -278,7 +289,8 @@ block0(v0: i64):
 
 function %sload8_i32(i64) -> i32 {
 block0(v0: i64):
-  v1 = sload8.i32 little v0
+  v2 = load.i8 little v0
+  v1 = sextend.i32 v2
   return v1
 }
 
@@ -294,27 +306,29 @@ block0(v0: i64):
 
 function %uload16_i32(i64) -> i32 {
 block0(v0: i64):
-  v1 = uload16.i32 little v0
+  v2 = load.i16 little v0
+  v1 = uextend.i32 v2
   return v1
 }
 
 ; VCode:
 ; block0:
-;   lrvh %r2, 0(%r2)
-;   llhr %r2, %r2
+;   lrvh %r3, 0(%r2)
+;   llhr %r2, %r3
 ;   br %r14
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   lrvh %r2, 0(%r2) ; trap: heap_oob
-;   llhr %r2, %r2
+;   lrvh %r3, 0(%r2) ; trap: heap_oob
+;   llhr %r2, %r3
 ;   br %r14
 
 function %uload16_i32_sym() -> i32 {
   gv0 = symbol colocated %sym
 block0:
   v0 = symbol_value.i64 gv0
-  v1 = uload16.i32 aligned little v0
+  v2 = load.i16 aligned little v0
+  v1 = uextend.i32 v2
   return v1
 }
 
@@ -333,27 +347,29 @@ block0:
 
 function %sload16_i32(i64) -> i32 {
 block0(v0: i64):
-  v1 = sload16.i32 little v0
+  v2 = load.i16 little v0
+  v1 = sextend.i32 v2
   return v1
 }
 
 ; VCode:
 ; block0:
-;   lrvh %r2, 0(%r2)
-;   lhr %r2, %r2
+;   lrvh %r3, 0(%r2)
+;   lhr %r2, %r3
 ;   br %r14
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   lrvh %r2, 0(%r2) ; trap: heap_oob
-;   lhr %r2, %r2
+;   lrvh %r3, 0(%r2) ; trap: heap_oob
+;   lhr %r2, %r3
 ;   br %r14
 
 function %sload16_i32_sym() -> i32 {
   gv0 = symbol colocated %sym
 block0:
   v0 = symbol_value.i64 gv0
-  v1 = sload16.i32 aligned little v0
+  v2 = load.i16 aligned little v0
+  v1 = sextend.i32 v2
   return v1
 }
 
@@ -407,7 +423,8 @@ block0:
 
 function %uload8_i16(i64) -> i16 {
 block0(v0: i64):
-  v1 = uload8.i16 little v0
+  v2 = load.i8 little v0
+  v1 = uextend.i16 v2
   return v1
 }
 
@@ -423,7 +440,8 @@ block0(v0: i64):
 
 function %sload8_i16(i64) -> i16 {
 block0(v0: i64):
-  v1 = sload8.i16 little v0
+  v2 = load.i8 little v0
+  v1 = sextend.i16 v2
   return v1
 }
 
diff --git a/cranelift/filetests/filetests/isa/s390x/load.clif b/cranelift/filetests/filetests/isa/s390x/load.clif
index 0916b312a3b1..99a94b1a6bf8 100644
--- a/cranelift/filetests/filetests/isa/s390x/load.clif
+++ b/cranelift/filetests/filetests/isa/s390x/load.clif
@@ -38,7 +38,8 @@ block0:
 
 function %uload8_i64(i64) -> i64 {
 block0(v0: i64):
-  v1 = uload8.i64 v0
+  v2 = load.i8 v0
+  v1 = uextend.i64 v2
   return v1
 }
 
@@ -55,7 +56,8 @@ block0(v0: i64):
 function %uload8_i64_i64_offset(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
   v2 = iadd v0, v1
-  v3 = uload8.i64 v2+100000
+  v4 = load.i8 v2+100000
+  v3 = uextend.i64 v4
   return v3
 }
 
@@ -72,7 +74,8 @@ block0(v0: i64, v1: i64):
 function %uload8_i64_i64_offset_too_big(i64, i64) -> i64 {
 block0(v0: i64, v1: i64):
   v2 = iadd v0, v1
-  v3 = uload8.i64 v2+10000000
+  v4 = load.i8 v2+10000000
+  v3 = uextend.i64 v4
   return v3
 }
 
@@ -91,7 +94,8 @@ block0(v0: i64, v1: i64):
 
 function %sload8_i64(i64) -> i64 {
 block0(v0: i64):
-  v1 = sload8.i64 v0
+  v2 = load.i8 v0
+  v1 = sextend.i64 v2
   return v1
 }
 
@@ -107,7 +111,8 @@ block0(v0: i64):
 
 function %uload16_i64(i64) -> i64 {
 block0(v0: i64):
-  v1 = uload16.i64 v0
+  v2 = load.i16 v0
+  v1 = uextend.i64 v2
   return v1
 }
 
@@ -125,7 +130,8 @@ function %uload16_i64_sym() -> i64 {
   gv0 = symbol colocated %sym
 block0:
   v0 = symbol_value.i64 gv0
-  v1 = uload16.i64 aligned v0
+  v2 = load.i16 aligned v0
+  v1 = uextend.i64 v2
   return v1
 }
 
@@ -141,7 +147,8 @@ block0:
 
 function %sload16_i64(i64) -> i64 {
 block0(v0: i64):
-  v1 = sload16.i64 v0
+  v2 = load.i16 v0
+  v1 = sextend.i64 v2
   return v1
 }
 
@@ -159,7 +166,8 @@ function %sload16_i64_sym() -> i64 {
   gv0 = symbol colocated %sym
 block0:
   v0 = symbol_value.i64 gv0
-  v1 = sload16.i64 aligned v0
+  v2 = load.i16 aligned v0
+  v1 = sextend.i64 v2
   return v1
 }
 
@@ -175,7 +183,8 @@ block0:
 
 function %uload32_i64(i64) -> i64 {
 block0(v0: i64):
-  v1 = uload32.i64 v0
+  v2 = load.i32 v0
+  v1 = uextend.i64 v2
   return v1
 }
 
@@ -193,7 +202,8 @@ function %uload32_i64_sym() -> i64 {
   gv0 = symbol colocated %sym
 block0:
   v0 = symbol_value.i64 gv0
-  v1 = uload32.i64 aligned v0
+  v2 = load.i32 aligned v0
+  v1 = uextend.i64 v2
   return v1
 }
 
@@ -209,7 +219,8 @@ block0:
 
 function %sload32_i64(i64) -> i64 {
 block0(v0: i64):
-  v1 = sload32.i64 v0
+  v2 = load.i32 v0
+  v1 = sextend.i64 v2
   return v1
 }
 
@@ -227,7 +238,8 @@ function %sload32_i64_sym() -> i64 {
   gv0 = symbol colocated %sym
 block0:
   v0 = symbol_value.i64 gv0
-  v1 = sload32.i64 aligned v0
+  v2 = load.i32 aligned v0
+  v1 = sextend.i64 v2
   return v1
 }
 
@@ -293,7 +305,8 @@ block0(v0: i64):
 
 function %uload8_i32(i64) -> i32 {
 block0(v0: i64):
-  v1 = uload8.i32 v0
+  v2 = load.i8 v0
+  v1 = uextend.i32 v2
   return v1
 }
 
@@ -309,7 +322,8 @@ block0(v0: i64):
 
 function %sload8_i32(i64) -> i32 {
 block0(v0: i64):
-  v1 = sload8.i32 v0
+  v2 = load.i8 v0
+  v1 = sextend.i32 v2
   return v1
 }
 
@@ -325,7 +339,8 @@ block0(v0: i64):
 
 function %uload16_i32(i64) -> i32 {
 block0(v0: i64):
-  v1 = uload16.i32 v0
+  v2 = load.i16 v0
+  v1 = uextend.i32 v2
   return v1
 }
 
@@ -343,7 +358,8 @@ function %uload16_i32_sym() -> i32 {
   gv0 = symbol colocated %sym
 block0:
   v0 = symbol_value.i64 gv0
-  v1 = uload16.i32 aligned v0
+  v2 = load.i16 aligned v0
+  v1 = uextend.i32 v2
   return v1
 }
 
@@ -359,7 +375,8 @@ block0:
 
 function %sload16_i32(i64) -> i32 {
 block0(v0: i64):
-  v1 = sload16.i32 v0
+  v2 = load.i16 v0
+  v1 = sextend.i32 v2
   return v1
 }
 
@@ -375,7 +392,8 @@ block0(v0: i64):
 
 function %sload16_i32_off(i64) -> i32 {
 block0(v0: i64):
-  v1 = sload16.i32 v0+4096
+  v2 = load.i16 v0+4096
+  v1 = sextend.i32 v2
   return v1
 }
 
@@ -393,7 +411,8 @@ function %sload16_i32_sym() -> i32 {
   gv0 = symbol colocated %sym
 block0:
   v0 = symbol_value.i64 gv0
-  v1 = sload16.i32 aligned v0
+  v2 = load.i16 aligned v0
+  v1 = sextend.i32 v2
   return v1
 }
 
@@ -443,7 +462,8 @@ block0:
 
 function %uload8_i16(i64) -> i16 {
 block0(v0: i64):
-  v1 = uload8.i16 v0
+  v2 = load.i8 v0
+  v1 = uextend.i16 v2
   return v1
 }
 
@@ -459,7 +479,8 @@ block0(v0: i64):
 
 function %sload8_i16(i64) -> i16 {
 block0(v0: i64):
-  v1 = sload8.i16 v0
+  v2 = load.i8 v0
+  v1 = sextend.i16 v2
   return v1
 }
 
diff --git a/cranelift/filetests/filetests/isa/s390x/store-little.clif b/cranelift/filetests/filetests/isa/s390x/store-little.clif
index 5b781f09ed2c..0351ce0f8599 100644
--- a/cranelift/filetests/filetests/isa/s390x/store-little.clif
+++ b/cranelift/filetests/filetests/isa/s390x/store-little.clif
@@ -57,7 +57,8 @@ block0(v0: i64):
 
 function %istore8_i64(i64, i64) {
 block0(v0: i64, v1: i64):
-  istore8.i64 little v0, v1
+  v2 = ireduce.i8 v0
+  store little v2, v1
   return
 }
 
@@ -74,7 +75,8 @@ block0(v0: i64, v1: i64):
 function %istore8_imm_i64(i64) {
 block0(v0: i64):
   v1 = iconst.i64 123
-  istore8.i64 little v1, v0
+  v2 = ireduce.i8 v1
+  store little v2, v0
   return
 }
 
@@ -90,7 +92,8 @@ block0(v0: i64):
 
 function %istore16_i64(i64, i64) {
 block0(v0: i64, v1: i64):
-  istore16.i64 little v0, v1
+  v2 = ireduce.i16 v0
+  store little v2, v1
   return
 }
 
@@ -108,7 +111,8 @@ function %istore16_i64_sym(i64) {
   gv0 = symbol colocated %sym
 block0(v0: i64):
   v1 = symbol_value.i64 gv0
-  istore16.i64 aligned little v0, v1
+  v2 = ireduce.i16 v0
+  store aligned little v2, v1
   return
 }
 
@@ -126,7 +130,8 @@ block0(v0: i64):
 function %istore16_imm_i64(i64) {
 block0(v0: i64):
   v1 = iconst.i64 12345
-  istore16.i64 little v1, v0
+  v2 = ireduce.i16 v1
+  store little v2, v0
   return
 }
 
@@ -142,7 +147,8 @@ block0(v0: i64):
 
 function %istore32_i64(i64, i64) {
 block0(v0: i64, v1: i64):
-  istore32.i64 little v0, v1
+  v2 = ireduce.i32 v0
+  store little v2, v1
   return
 }
 
@@ -160,7 +166,8 @@ function %istore32_i64_sym(i64) {
   gv0 = symbol colocated %sym
 block0(v0: i64):
   v1 = symbol_value.i64 gv0
-  istore32.i64 aligned little v0, v1
+  v2 = ireduce.i32 v0
+  store aligned little v2, v1
   return
 }
 
@@ -178,7 +185,8 @@ block0(v0: i64):
 function %istore32_imm_i64(i64) {
 block0(v0: i64):
   v1 = iconst.i64 12345
-  istore32.i64 little v1, v0
+  v2 = ireduce.i32 v1
+  store little v2, v0
   return
 }
 
@@ -250,7 +258,8 @@ block0(v0: i64):
 
 function %istore8_i32(i32, i64) {
 block0(v0: i32, v1: i64):
-  istore8.i32 little v0, v1
+  v2 = ireduce.i8 v0
+  store little v2, v1
   return
 }
 
@@ -267,7 +276,8 @@ block0(v0: i32, v1: i64):
 function %istore8_imm_i32(i64) {
 block0(v0: i64):
   v1 = iconst.i32 123
-  istore8.i32 little v1, v0
+  v2 = ireduce.i8 v1
+  store little v2, v0
   return
 }
 
@@ -283,7 +293,8 @@ block0(v0: i64):
 
 function %istore16_i32(i32, i64) {
 block0(v0: i32, v1: i64):
-  istore16.i32 little v0, v1
+  v2 = ireduce.i16 v0
+  store little v2, v1
   return
 }
 
@@ -301,7 +312,8 @@ function %istore16_i32_sym(i32) {
   gv0 = symbol colocated %sym
 block0(v0: i32):
   v1 = symbol_value.i64 gv0
-  istore16.i32 aligned little v0, v1
+  v2 = ireduce.i16 v0
+  store aligned little v2, v1
   return
 }
 
@@ -319,7 +331,8 @@ block0(v0: i32):
 function %istore16_imm_i32(i64) {
 block0(v0: i64):
   v1 = iconst.i32 12345
-  istore16.i32 little v1, v0
+  v2 = ireduce.i16 v1
+  store little v2, v0
   return
 }
 
@@ -387,7 +400,8 @@ block0(v0: i64):
 
 function %istore8_i16(i16, i64) {
 block0(v0: i16, v1: i64):
-  istore8.i16 little v0, v1
+  v2 = ireduce.i8 v0
+  store little v2, v1
   return
 }
 
@@ -404,7 +418,8 @@ block0(v0: i16, v1: i64):
 function %istore8_imm_i16(i64) {
 block0(v0: i64):
   v1 = iconst.i16 123
-  istore8.i16 little v1, v0
+  v2 = ireduce.i8 v1
+  store little v2, v0
   return
 }
 
diff --git a/cranelift/filetests/filetests/isa/s390x/store.clif b/cranelift/filetests/filetests/isa/s390x/store.clif
index cfbfc17c3773..f37ece9e491f 100644
--- a/cranelift/filetests/filetests/isa/s390x/store.clif
+++ b/cranelift/filetests/filetests/isa/s390x/store.clif
@@ -54,7 +54,8 @@ block0(v0: i64):
 
 function %istore8_i64(i64, i64) {
 block0(v0: i64, v1: i64):
-  istore8.i64 v0, v1
+  v2 = ireduce.i8 v0
+  store v2, v1
   return
 }
 
@@ -71,7 +72,8 @@ block0(v0: i64, v1: i64):
 function %istore8_imm_i64(i64) {
 block0(v0: i64):
   v1 = iconst.i64 123
-  istore8.i64 v1, v0
+  v2 = ireduce.i8 v1
+  store v2, v0
   return
 }
 
@@ -87,7 +89,8 @@ block0(v0: i64):
 
 function %istore16_i64(i64, i64) {
 block0(v0: i64, v1: i64):
-  istore16.i64 v0, v1
+  v2 = ireduce.i16 v0
+  store v2, v1
   return
 }
 
@@ -105,7 +108,8 @@ function %istore16_i64_sym(i64) {
   gv0 = symbol colocated %sym
 block0(v0: i64):
   v1 = symbol_value.i64 gv0
-  istore16.i64 aligned v0, v1
+  v2 = ireduce.i16 v0
+  store aligned v2, v1
   return
 }
 
@@ -122,7 +126,8 @@ block0(v0: i64):
 function %istore16_imm_i64(i64) {
 block0(v0: i64):
   v1 = iconst.i64 12345
-  istore16.i64 v1, v0
+  v2 = ireduce.i16 v1
+  store v2, v0
   return
 }
 
@@ -138,7 +143,8 @@ block0(v0: i64):
 
 function %istore32_i64(i64, i64) {
 block0(v0: i64, v1: i64):
-  istore32.i64 v0, v1
+  v2 = ireduce.i32 v0
+  store v2, v1
   return
 }
 
@@ -156,7 +162,8 @@ function %istore32_i64_sym(i64) {
   gv0 = symbol colocated %sym
 block0(v0: i64):
   v1 = symbol_value.i64 gv0
-  istore32.i64 aligned v0, v1
+  v2 = ireduce.i32 v0
+  store aligned v2, v1
   return
 }
 
@@ -173,7 +180,8 @@ block0(v0: i64):
 function %istore32_imm_i64(i64) {
 block0(v0: i64):
   v1 = iconst.i64 12345
-  istore32.i64 v1, v0
+  v2 = ireduce.i32 v1
+  store v2, v0
   return
 }
 
@@ -256,7 +264,8 @@ block0(v0: i64):
 
 function %istore8_i32(i32, i64) {
 block0(v0: i32, v1: i64):
-  istore8.i32 v0, v1
+  v2 = ireduce.i8 v0
+  store v2, v1
   return
 }
 
@@ -273,7 +282,8 @@ block0(v0: i32, v1: i64):
 function %istore8_imm_i32(i64) {
 block0(v0: i64):
   v1 = iconst.i32 123
-  istore8.i32 v1, v0
+  v2 = ireduce.i8 v1
+  store v2, v0
   return
 }
 
@@ -289,7 +299,8 @@ block0(v0: i64):
 
 function %istore16_i32(i32, i64) {
 block0(v0: i32, v1: i64):
-  istore16.i32 v0, v1
+  v2 = ireduce.i16 v0
+  store v2, v1
   return
 }
 
@@ -307,7 +318,8 @@ function %istore16_i32_sym(i32) {
   gv0 = symbol colocated %sym
 block0(v0: i32):
   v1 = symbol_value.i64 gv0
-  istore16.i32 aligned v0, v1
+  v2 = ireduce.i16 v0
+  store aligned v2, v1
   return
 }
 
@@ -324,7 +336,8 @@ block0(v0: i32):
 function %istore16_imm_i32(i64) {
 block0(v0: i64):
   v1 = iconst.i32 12345
-  istore16.i32 v1, v0
+  v2 = ireduce.i16 v1
+  store v2, v0
   return
 }
 
@@ -407,7 +420,8 @@ block0(v0: i64):
 
 function %istore8_i16(i16, i64) {
 block0(v0: i16, v1: i64):
-  istore8.i16 v0, v1
+  v2 = ireduce.i8 v0
+  store v2, v1
   return
 }
 
@@ -424,7 +438,8 @@ block0(v0: i16, v1: i64):
 function %istore8_imm_i16(i64) {
 block0(v0: i64):
   v1 = iconst.i16 123
-  istore8.i16 v1, v0
+  v2 = ireduce.i8 v1
+  store v2, v0
   return
 }
 
diff --git a/cranelift/filetests/filetests/isa/x64/big-endian.clif b/cranelift/filetests/filetests/isa/x64/big-endian.clif
index 0a0d0d413ffd..5e92e2798df9 100644
--- a/cranelift/filetests/filetests/isa/x64/big-endian.clif
+++ b/cranelift/filetests/filetests/isa/x64/big-endian.clif
@@ -73,37 +73,43 @@ function %f(i64) -> f64x2 {
 
 function %f(i64) -> i32 {
     block0(v0: i64):
-        v1 = uload8.i32 big v0+8
+        v2 = load.i8 big v0+8
+        v1 = uextend.i32 v2
         return v1
 }
 
 function %f(i64) -> i32 {
     block0(v0: i64):
-        v1 = sload8.i32 big v0+8
+        v2 = load.i8 big v0+8
+        v1 = sextend.i32 v2
         return v1
 }
 
 function %f(i64) -> i32 {
     block0(v0: i64):
-        v1 = uload16.i32 big v0+8
+        v2 = load.i16 big v0+8
+        v1 = uextend.i32 v2
         return v1
 }
 
 function %f(i64) -> i32 {
     block0(v0: i64):
-        v1 = sload16.i32 big v0+8
+        v2 = load.i16 big v0+8
+        v1 = sextend.i32 v2
         return v1
 }
 
 function %f(i64) -> i64 {
     block0(v0: i64):
-        v1 = uload32.i64 big v0+8
+        v2 = load.i32 big v0+8
+        v1 = uextend.i64 v2
         return v1
 }
 
 function %f(i64) -> i64 {
     block0(v0: i64):
-        v1 = sload32.i64 big v0+8
+        v2 = load.i32 big v0+8
+        v1 = sextend.i64 v2
         return v1
 }
 
@@ -139,19 +145,22 @@ function %f(i64, i128) {
 
 function %f(i64, i64) {
     block0(v0: i64, v1: i64):
-        istore8.i64 big v1, v0+8
+        v2 = ireduce.i8 v1
+        store big v2, v0+8
         return
 }
 
 function %f(i64, i64) {
     block0(v0: i64, v1: i64):
-        istore16.i64 big v1, v0+8
+        v2 = ireduce.i16 v1
+        store big v2, v0+8
         return
 }
 
 function %f(i64, i64) {
     block0(v0: i64, v1: i64):
-        istore32.i64 big v1, v0+8
+        v2 = ireduce.i32 v1
+        store big v2, v0+8
         return
 }
 
diff --git a/cranelift/filetests/filetests/isa/x64/dead-notrap-load.clif b/cranelift/filetests/filetests/isa/x64/dead-notrap-load.clif
index 64f82a18e4c0..e5a3fb940981 100644
--- a/cranelift/filetests/filetests/isa/x64/dead-notrap-load.clif
+++ b/cranelift/filetests/filetests/isa/x64/dead-notrap-load.clif
@@ -31,7 +31,8 @@ block0(v0: i64):
 
 function %dead_notrap_uload8(i64) {
 block0(v0: i64):
-    v1 = uload8.i32 notrap aligned v0
+    v2 = load.i8 notrap aligned v0
+    v1 = uextend.i32 v2
     return
 }
 
diff --git a/cranelift/filetests/filetests/runtests/alias-analysis-endianness.clif b/cranelift/filetests/filetests/runtests/alias-analysis-endianness.clif
new file mode 100644
index 000000000000..bb53ed0c797e
--- /dev/null
+++ b/cranelift/filetests/filetests/runtests/alias-analysis-endianness.clif
@@ -0,0 +1,51 @@
+test interpret
+test run
+set opt_level=speed
+
+;; XXX: only the s390x and Pulley backends implement non-native byte order for
+;; memory accesses at the time of writing, and these tests need a mismatched
+;; pair to exercise the alias-analysis behavior at all.
+target s390x
+target pulley64
+
+;; Redundant-load elimination between a little-endian and a big-endian load:
+;; the big-endian load must not be replaced with the little-endian one's
+;; result. Correct result: 0x1234 ^ 0x3412 == 0x2626.
+function %rle_across_endianness(i16) -> i16 {
+    ss0 = explicit_slot 8
+block0(v1: i16):
+    v0 = stack_addr.i64 ss0
+    store little v1, v0
+    v2 = load.i16 little v0
+    v3 = load.i16 big v0
+    v4 = bxor v2, v3
+    return v4
+}
+; run: %rle_across_endianness(0x1234) == 0x2626
+
+;; Store-to-load forwarding between a little-endian store and a big-endian
+;; load: the load must not be replaced with the store's data.
+function %stl_across_endianness(i16) -> i16 {
+    ss0 = explicit_slot 8
+block0(v1: i16):
+    v0 = stack_addr.i64 ss0
+    store little v1, v0
+    v2 = load.i16 big v0
+    return v2
+}
+; run: %stl_across_endianness(0x1234) == 0x3412
+
+;; Idempotent-store elimination between a big-endian load and a little-endian
+;; store: the store writes the byte-swapped value, so it is not idempotent and
+;; must not be deleted.
+function %idempotent_store_across_endianness(i16) -> i16 {
+    ss0 = explicit_slot 8
+block0(v1: i16):
+    v0 = stack_addr.i64 ss0
+    store little v1, v0
+    v2 = load.i16 big v0
+    store little v2, v0
+    v3 = load.i16 little v0
+    return v3
+}
+; run: %idempotent_store_across_endianness(0x1234) == 0x3412
diff --git a/cranelift/interpreter/src/step.rs b/cranelift/interpreter/src/step.rs
index 8e4c5bd1dea7..8c8d44a6f9c8 100644
--- a/cranelift/interpreter/src/step.rs
+++ b/cranelift/interpreter/src/step.rs
@@ -464,27 +464,14 @@ where
             })
         }
         Opcode::Load
-        | Opcode::Uload8
-        | Opcode::Sload8
-        | Opcode::Uload16
-        | Opcode::Sload16
-        | Opcode::Uload32
-        | Opcode::Sload32
         | Opcode::Uload8x8
         | Opcode::Sload8x8
         | Opcode::Uload16x4
         | Opcode::Sload16x4
         | Opcode::Uload32x2
         | Opcode::Sload32x2 => {
-            let ctrl_ty = inst_context.controlling_type().unwrap();
-            let (load_ty, kind) = match inst.opcode() {
-                Opcode::Load => (ctrl_ty, None),
-                Opcode::Uload8 => (types::I8, Some(ValueConversionKind::ZeroExtend(ctrl_ty))),
-                Opcode::Sload8 => (types::I8, Some(ValueConversionKind::SignExtend(ctrl_ty))),
-                Opcode::Uload16 => (types::I16, Some(ValueConversionKind::ZeroExtend(ctrl_ty))),
-                Opcode::Sload16 => (types::I16, Some(ValueConversionKind::SignExtend(ctrl_ty))),
-                Opcode::Uload32 => (types::I32, Some(ValueConversionKind::ZeroExtend(ctrl_ty))),
-                Opcode::Sload32 => (types::I32, Some(ValueConversionKind::SignExtend(ctrl_ty))),
+            let load_ty = match inst.opcode() {
+                Opcode::Load => inst_context.controlling_type().unwrap(),
                 Opcode::Uload8x8
                 | Opcode::Sload8x8
                 | Opcode::Uload16x4
@@ -496,39 +483,18 @@ where
 
             let addr_value = calculate_addr(types::I64, imm(), args())?;
             let mem_flags = resolve_memflags();
-            let loaded = assign_or_memtrap(
+            assign_or_memtrap(
                 Address::try_from(addr_value)
                     .and_then(|addr| state.checked_load(addr, load_ty, mem_flags)),
-            );
-
-            match (loaded, kind) {
-                (ControlFlow::Assign(ret), Some(c)) => ControlFlow::Assign(
-                    ret.into_iter()
-                        .map(|loaded| loaded.convert(c.clone()))
-                        .collect::<ValueResult<SmallVec<[DataValue; 1]>>>()?,
-                ),
-                (cf, _) => cf,
-            }
+            )
         }
-        Opcode::Store | Opcode::Istore8 | Opcode::Istore16 | Opcode::Istore32 => {
-            let kind = match inst.opcode() {
-                Opcode::Store => None,
-                Opcode::Istore8 => Some(ValueConversionKind::Truncate(types::I8)),
-                Opcode::Istore16 => Some(ValueConversionKind::Truncate(types::I16)),
-                Opcode::Istore32 => Some(ValueConversionKind::Truncate(types::I32)),
-                _ => unreachable!(),
-            };
-
+        Opcode::Store => {
             let addr_value = calculate_addr(types::I64, imm(), args_range(1..)?)?;
             let mem_flags = resolve_memflags();
-            let reduced = if let Some(c) = kind {
-                arg(0).convert(c)?
-            } else {
-                arg(0)
-            };
+            let value = arg(0);
             continue_or_memtrap(
                 Address::try_from(addr_value)
-                    .and_then(|addr| state.checked_store(addr, reduced, mem_flags)),
+                    .and_then(|addr| state.checked_store(addr, value, mem_flags)),
             )
         }
         Opcode::StackAddr => {
diff --git a/crates/cranelift/src/translate/code_translator.rs b/crates/cranelift/src/translate/code_translator.rs
index 088e0f2bd488..a10075bcc331 100644
--- a/crates/cranelift/src/translate/code_translator.rs
+++ b/crates/cranelift/src/translate/code_translator.rs
@@ -873,91 +873,91 @@ pub fn translate_operator(
         Operator::I32Load8U { memarg } => {
             unwrap_or_return_unreachable_state!(
                 environ,
-                translate_load(memarg, ir::Opcode::Uload8, I32, builder, environ)?
+                translate_extending_load(memarg, I8, I32, false, builder, environ)?
             );
         }
         Operator::I32Load16U { memarg } => {
             unwrap_or_return_unreachable_state!(
                 environ,
-                translate_load(memarg, ir::Opcode::Uload16, I32, builder, environ)?
+                translate_extending_load(memarg, I16, I32, false, builder, environ)?
             );
         }
         Operator::I32Load8S { memarg } => {
             unwrap_or_return_unreachable_state!(
                 environ,
-                translate_load(memarg, ir::Opcode::Sload8, I32, builder, environ)?
+                translate_extending_load(memarg, I8, I32, true, builder, environ)?
             );
         }
         Operator::I32Load16S { memarg } => {
             unwrap_or_return_unreachable_state!(
                 environ,
-                translate_load(memarg, ir::Opcode::Sload16, I32, builder, environ)?
+                translate_extending_load(memarg, I16, I32, true, builder, environ)?
             );
         }
         Operator::I64Load8U { memarg } => {
             unwrap_or_return_unreachable_state!(
                 environ,
-                translate_load(memarg, ir::Opcode::Uload8, I64, builder, environ)?
+                translate_extending_load(memarg, I8, I64, false, builder, environ)?
             );
         }
         Operator::I64Load16U { memarg } => {
             unwrap_or_return_unreachable_state!(
                 environ,
-                translate_load(memarg, ir::Opcode::Uload16, I64, builder, environ)?
+                translate_extending_load(memarg, I16, I64, false, builder, environ)?
             );
         }
         Operator::I64Load8S { memarg } => {
             unwrap_or_return_unreachable_state!(
                 environ,
-                translate_load(memarg, ir::Opcode::Sload8, I64, builder, environ)?
+                translate_extending_load(memarg, I8, I64, true, builder, environ)?
             );
         }
         Operator::I64Load16S { memarg } => {
             unwrap_or_return_unreachable_state!(
                 environ,
-                translate_load(memarg, ir::Opcode::Sload16, I64, builder, environ)?
+                translate_extending_load(memarg, I16, I64, true, builder, environ)?
             );
         }
         Operator::I64Load32S { memarg } => {
             unwrap_or_return_unreachable_state!(
                 environ,
-                translate_load(memarg, ir::Opcode::Sload32, I64, builder, environ)?
+                translate_extending_load(memarg, I32, I64, true, builder, environ)?
             );
         }
         Operator::I64Load32U { memarg } => {
             unwrap_or_return_unreachable_state!(
                 environ,
-                translate_load(memarg, ir::Opcode::Uload32, I64, builder, environ)?
+                translate_extending_load(memarg, I32, I64, false, builder, environ)?
             );
         }
         Operator::I32Load { memarg } => {
             unwrap_or_return_unreachable_state!(
                 environ,
-                translate_load(memarg, ir::Opcode::Load, I32, builder, environ)?
+                translate_load(memarg, I32, builder, environ)?
             );
         }
         Operator::F32Load { memarg } => {
             unwrap_or_return_unreachable_state!(
                 environ,
-                translate_load(memarg, ir::Opcode::Load, F32, builder, environ)?
+                translate_load(memarg, F32, builder, environ)?
             );
         }
         Operator::I64Load { memarg } => {
             unwrap_or_return_unreachable_state!(
                 environ,
-                translate_load(memarg, ir::Opcode::Load, I64, builder, environ)?
+                translate_load(memarg, I64, builder, environ)?
             );
         }
         Operator::F64Load { memarg } => {
             unwrap_or_return_unreachable_state!(
                 environ,
-                translate_load(memarg, ir::Opcode::Load, F64, builder, environ)?
+                translate_load(memarg, F64, builder, environ)?
             );
         }
         Operator::V128Load { memarg } => {
             unwrap_or_return_unreachable_state!(
                 environ,
-                translate_load(memarg, ir::Opcode::Load, I8X16, builder, environ)?
+                translate_load(memarg, I8X16, builder, environ)?
             );
         }
         Operator::V128Load8x8S { memarg } => {
@@ -1017,19 +1017,19 @@ pub fn translate_operator(
         | Operator::I64Store { memarg }
         | Operator::F32Store { memarg }
         | Operator::F64Store { memarg } => {
-            translate_store(memarg, ir::Opcode::Store, builder, environ)?;
+            translate_store(memarg, None, builder, environ)?;
         }
         Operator::I32Store8 { memarg } | Operator::I64Store8 { memarg } => {
-            translate_store(memarg, ir::Opcode::Istore8, builder, environ)?;
+            translate_store(memarg, Some(I8), builder, environ)?;
         }
         Operator::I32Store16 { memarg } | Operator::I64Store16 { memarg } => {
-            translate_store(memarg, ir::Opcode::Istore16, builder, environ)?;
+            translate_store(memarg, Some(I16), builder, environ)?;
         }
         Operator::I64Store32 { memarg } => {
-            translate_store(memarg, ir::Opcode::Istore32, builder, environ)?;
+            translate_store(memarg, Some(I32), builder, environ)?;
         }
         Operator::V128Store { memarg } => {
-            translate_store(memarg, ir::Opcode::Store, builder, environ)?;
+            translate_store(memarg, None, builder, environ)?;
         }
         /****************************** Nullary Operators ************************************/
         Operator::I32Const { value } => {
@@ -1781,13 +1781,7 @@ pub fn translate_operator(
         | Operator::V128Load64Splat { memarg } => {
             unwrap_or_return_unreachable_state!(
                 environ,
-                translate_load(
-                    memarg,
-                    ir::Opcode::Load,
-                    type_of(op).lane_type(),
-                    builder,
-                    environ,
-                )?
+                translate_load(memarg, type_of(op).lane_type(), builder, environ)?
             );
             let splatted = builder.ins().splat(type_of(op), environ.stacks.pop1());
             environ.stacks.push1(splatted)
@@ -1795,13 +1789,7 @@ pub fn translate_operator(
         Operator::V128Load32Zero { memarg } | Operator::V128Load64Zero { memarg } => {
             unwrap_or_return_unreachable_state!(
                 environ,
-                translate_load(
-                    memarg,
-                    ir::Opcode::Load,
-                    type_of(op).lane_type(),
-                    builder,
-                    environ,
-                )?
+                translate_load(memarg, type_of(op).lane_type(), builder, environ)?
             );
             let as_vector = builder
                 .ins()
@@ -1815,13 +1803,7 @@ pub fn translate_operator(
             let vector = pop1_with_bitcast(environ, type_of(op), builder);
             unwrap_or_return_unreachable_state!(
                 environ,
-                translate_load(
-                    memarg,
-                    ir::Opcode::Load,
-                    type_of(op).lane_type(),
-                    builder,
-                    environ,
-                )?
+                translate_load(memarg, type_of(op).lane_type(), builder, environ)?
             );
             let replacement = environ.stacks.pop1();
             environ
@@ -1836,7 +1818,7 @@ pub fn translate_operator(
             environ
                 .stacks
                 .push1(builder.ins().extractlane(vector, *lane));
-            translate_store(memarg, ir::Opcode::Store, builder, environ)?;
+            translate_store(memarg, None, builder, environ)?;
         }
         Operator::I8x16ExtractLaneS { lane } | Operator::I16x8ExtractLaneS { lane } => {
             let vector = pop1_with_bitcast(environ, type_of(op), builder);
@@ -3814,17 +3796,16 @@ fn prepare_atomic_addr(
     prepare_addr(memarg, loaded_bytes, builder, environ)
 }
 
-/// Translate a load instruction.
+/// Translate a load instruction, reading `access_ty` from memory.
 ///
 /// Returns the execution state's reachability after the load is translated.
 fn translate_load(
     memarg: &MemArg,
-    opcode: ir::Opcode,
-    result_ty: Type,
+    access_ty: Type,
     builder: &mut FunctionBuilder,
     environ: &mut FuncEnvironment<'_>,
 ) -> WasmResult<Reachability<()>> {
-    let mem_op_size = mem_op_size(opcode, result_ty);
+    let mem_op_size = u8::try_from(access_ty.bytes()).unwrap();
     let (flags, wasm_index, base) = match prepare_addr(memarg, mem_op_size, builder, environ)? {
         Reachability::Unreachable => return Ok(Reachability::Unreachable),
         Reachability::Reachable((f, i, b)) => (f, i, b),
@@ -3832,24 +3813,52 @@ fn translate_load(
 
     environ.before_load(builder, mem_op_size, wasm_index, memarg.offset);
 
-    let flags = builder.func.dfg.mem_flags.insert(flags).unwrap();
-    let (load, dfg) = builder
-        .ins()
-        .Load(opcode, result_ty, flags, Offset32::new(0), base);
-    environ.stacks.push1(dfg.first_result(load));
+    let loaded = builder.ins().load(access_ty, flags, base, Offset32::new(0));
+    environ.stacks.push1(loaded);
     Ok(Reachability::Reachable(()))
 }
 
+/// Translate a load instruction that reads `access_ty` from memory and then
+/// widens it to `result_ty`, either sign- or zero-extending it.
+///
+/// Returns the execution state's reachability after the load is translated.
+fn translate_extending_load(
+    memarg: &MemArg,
+    access_ty: Type,
+    result_ty: Type,
+    signed: bool,
+    builder: &mut FunctionBuilder,
+    environ: &mut FuncEnvironment<'_>,
+) -> WasmResult<Reachability<()>> {
+    match translate_load(memarg, access_ty, builder, environ)? {
+        Reachability::Unreachable => Ok(Reachability::Unreachable),
+        Reachability::Reachable(()) => {
+            let loaded = environ.stacks.pop1();
+            let extended = if signed {
+                builder.ins().sextend(result_ty, loaded)
+            } else {
+                builder.ins().uextend(result_ty, loaded)
+            };
+            environ.stacks.push1(extended);
+            Ok(Reachability::Reachable(()))
+        }
+    }
+}
+
 /// Translate a store instruction.
+///
+/// When `access_ty` is `Some`, only that many low bits of the stored value are
+/// written to memory, i.e. this is one of Wasm's narrowing `i32.store8`-style
+/// operators. Otherwise the value is stored at its own type.
 fn translate_store(
     memarg: &MemArg,
-    opcode: ir::Opcode,
+    access_ty: Option<Type>,
     builder: &mut FunctionBuilder,
     environ: &mut FuncEnvironment<'_>,
 ) -> WasmResult<()> {
     let val = environ.stacks.pop1();
-    let val_ty = builder.func.dfg.value_type(val);
-    let mem_op_size = mem_op_size(opcode, val_ty);
+    let access_ty = access_ty.unwrap_or_else(|| builder.func.dfg.value_type(val));
+    let mem_op_size = u8::try_from(access_ty.bytes()).unwrap();
 
     let (flags, wasm_index, base) = unwrap_or_return_unreachable_state!(
         environ,
@@ -3858,23 +3867,15 @@ fn translate_store(
 
     environ.before_store(builder, mem_op_size, wasm_index, memarg.offset);
 
-    let flags = builder.func.dfg.mem_flags.insert(flags).unwrap();
-    builder
-        .ins()
-        .Store(opcode, val_ty, flags, Offset32::new(0), val, base);
+    let val = if builder.func.dfg.value_type(val) == access_ty {
+        val
+    } else {
+        builder.ins().ireduce(access_ty, val)
+    };
+    builder.ins().store(flags, val, base, Offset32::new(0));
     Ok(())
 }
 
-fn mem_op_size(opcode: ir::Opcode, ty: Type) -> u8 {
-    match opcode {
-        ir::Opcode::Istore8 | ir::Opcode::Sload8 | ir::Opcode::Uload8 => 1,
-        ir::Opcode::Istore16 | ir::Opcode::Sload16 | ir::Opcode::Uload16 => 2,
-        ir::Opcode::Istore32 | ir::Opcode::Sload32 | ir::Opcode::Uload32 => 4,
-        ir::Opcode::Store | ir::Opcode::Load => u8::try_from(ty.bytes()).unwrap(),
-        _ => panic!("unknown size of mem op for {opcode:?}"),
-    }
-}
-
 fn translate_icmp(cc: IntCC, builder: &mut FunctionBuilder, environ: &mut FuncEnvironment<'_>) {
     let (arg0, arg1) = environ.stacks.pop2();
     let val = builder.ins().icmp(cc, arg0, arg1);
diff --git a/tests/disas/array-fill-i16.wat b/tests/disas/array-fill-i16.wat
index 145c04ad6c59..0ba173d94d03 100644
--- a/tests/disas/array-fill-i16.wat
+++ b/tests/disas/array-fill-i16.wat
@@ -51,25 +51,26 @@
 ;; @0031                               v24 = iconst.i64 20
 ;; @0031                               v25 = iadd v9, v24  ; v24 = 20
 ;; @0031                               v16 = iconst.i64 1
-;;                                     v50 = ishl v14, v16  ; v16 = 1
-;; @0031                               v29 = iadd v25, v50
-;;                                     v54 = ishl v15, v16  ; v16 = 1
-;; @0031                               v38 = uadd_overflow_trap v29, v54, user2
+;;                                     v51 = ishl v14, v16  ; v16 = 1
+;; @0031                               v29 = iadd v25, v51
+;;                                     v55 = ishl v15, v16  ; v16 = 1
+;; @0031                               v38 = uadd_overflow_trap v29, v55, user2
 ;; @0031                               v37 = iadd v8, v36
 ;; @0031                               v39 = icmp ugt v38, v37
 ;; @0031                               trapnz v39, user2
-;;                                     v47 = iconst.i64 0
-;; @0031                               v42 = icmp eq v15, v47  ; v47 = 0
+;;                                     v48 = iconst.i64 0
+;; @0031                               v42 = icmp eq v15, v48  ; v48 = 0
+;; @0031                               v44 = ireduce.i16 v4
 ;; @0031                               v27 = iconst.i64 2
-;; @0031                               v40 = iadd v29, v54
+;; @0031                               v40 = iadd v29, v55
 ;; @0031                               brif v42, block3, block2(v29)
 ;;
 ;;                                 block2(v43: i64):
-;; @0031                               istore16.i32 user2 little region4 v4, v43
-;;                                     v57 = iconst.i64 2
-;;                                     v58 = iadd v43, v57  ; v57 = 2
-;; @0031                               v46 = icmp eq v58, v40
-;; @0031                               brif v46, block3, block2(v58)
+;; @0031                               store.i16 user2 little region4 v44, v43
+;;                                     v58 = iconst.i64 2
+;;                                     v59 = iadd v43, v58  ; v58 = 2
+;; @0031                               v47 = icmp eq v59, v40
+;; @0031                               brif v47, block3, block2(v59)
 ;;
 ;;                                 block3:
 ;; @0034                               jump block1
@@ -202,27 +203,27 @@
 ;; @005d                               v24 = iconst.i64 20
 ;; @005d                               v25 = iadd v9, v24  ; v24 = 20
 ;; @005d                               v16 = iconst.i64 1
-;;                                     v50 = ishl v14, v16  ; v16 = 1
-;; @005d                               v29 = iadd v25, v50
-;;                                     v54 = ishl v15, v16  ; v16 = 1
-;; @005d                               v38 = uadd_overflow_trap v29, v54, user2
+;;                                     v51 = ishl v14, v16  ; v16 = 1
+;; @005d                               v29 = iadd v25, v51
+;;                                     v55 = ishl v15, v16  ; v16 = 1
+;; @005d                               v38 = uadd_overflow_trap v29, v55, user2
 ;; @005d                               v37 = iadd v8, v36
 ;; @005d                               v39 = icmp ugt v38, v37
 ;; @005d                               trapnz v39, user2
-;;                                     v47 = iconst.i64 0
-;; @005d                               v42 = icmp eq v15, v47  ; v47 = 0
-;; @0057                               v5 = iconst.i32 0xdead
+;;                                     v48 = iconst.i64 0
+;; @005d                               v42 = icmp eq v15, v48  ; v48 = 0
+;;                                     v58 = iconst.i16 -8531
 ;; @005d                               v27 = iconst.i64 2
-;; @005d                               v40 = iadd v29, v54
+;; @005d                               v40 = iadd v29, v55
 ;; @005d                               brif v42, block3, block2(v29)
 ;;
 ;;                                 block2(v43: i64):
-;;                                     v57 = iconst.i32 0xdead
-;; @005d                               istore16 user2 little region4 v57, v43  ; v57 = 0xdead
-;;                                     v58 = iconst.i64 2
-;;                                     v59 = iadd v43, v58  ; v58 = 2
-;; @005d                               v46 = icmp eq v59, v40
-;; @005d                               brif v46, block3, block2(v59)
+;;                                     v59 = iconst.i16 -8531
+;; @005d                               store user2 little region4 v59, v43  ; v59 = -8531
+;;                                     v60 = iconst.i64 2
+;;                                     v61 = iadd v43, v60  ; v60 = 2
+;; @005d                               v47 = icmp eq v61, v40
+;; @005d                               brif v47, block3, block2(v61)
 ;;
 ;;                                 block3:
 ;; @0060                               jump block1
diff --git a/tests/disas/bounds-check.wat b/tests/disas/bounds-check.wat
index 8271ac7954af..2b1899e619f7 100644
--- a/tests/disas/bounds-check.wat
+++ b/tests/disas/bounds-check.wat
@@ -36,21 +36,21 @@
 ;;     stack_limit = gv2
 ;;
 ;;                                 block0(v0: i64, v1: i64, v2: i32):
-;; @002a                               v3 = iconst.i32 0
+;;                                     v26 = iconst.i8 0
 ;; @002c                               v5 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @002c                               v4 = uextend.i64 v2
 ;; @002c                               v6 = iadd v5, v4
-;; @002c                               istore8 little region4 v3, v6  ; v3 = 0
-;; @0033                               v11 = iconst.i64 0x07ff_ffff
-;; @0033                               v12 = iadd v6, v11  ; v11 = 0x07ff_ffff
-;; @0033                               istore8 little region4 v3, v12  ; v3 = 0
-;; @003d                               v15 = load.i64 notrap aligned region3 v0+64
-;; @003d                               v16 = icmp ugt v4, v15
-;; @003d                               v21 = iconst.i64 0
-;; @003d                               v19 = iconst.i64 0xffff_ffff
-;; @003d                               v20 = iadd v6, v19  ; v19 = 0xffff_ffff
-;; @003d                               v22 = select_spectre_guard v16, v21, v20  ; v21 = 0
-;; @003d                               istore8 little region4 v3, v22  ; v3 = 0
+;; @002c                               store little region4 v26, v6  ; v26 = 0
+;; @0033                               v12 = iconst.i64 0x07ff_ffff
+;; @0033                               v13 = iadd v6, v12  ; v12 = 0x07ff_ffff
+;; @0033                               store little region4 v26, v13  ; v26 = 0
+;; @003d                               v17 = load.i64 notrap aligned region3 v0+64
+;; @003d                               v18 = icmp ugt v4, v17
+;; @003d                               v23 = iconst.i64 0
+;; @003d                               v21 = iconst.i64 0xffff_ffff
+;; @003d                               v22 = iadd v6, v21  ; v21 = 0xffff_ffff
+;; @003d                               v24 = select_spectre_guard v18, v23, v22  ; v23 = 0
+;; @003d                               store little region4 v26, v24  ; v26 = 0
 ;; @0044                               jump block1
 ;;
 ;;                                 block1:
diff --git a/tests/disas/debug-exceptions.wat b/tests/disas/debug-exceptions.wat
index 251ca92806a3..e67436863d27 100644
--- a/tests/disas/debug-exceptions.wat
+++ b/tests/disas/debug-exceptions.wat
@@ -70,8 +70,9 @@
 ;;       cmp     x1, x2
 ;;       b.hi    #0x198
 ;;   ac: ldur    x4, [sp, #0x18]
-;;       add     w2, w3, #0x20
-;;       str     w2, [x0]
+;;       mov     w2, #0x20
+;;       add     w5, w3, #0x20
+;;       str     w5, [x0]
 ;;       mov     w5, #2
 ;;       movk    w5, #0x400, lsl #16
 ;;       ldr     x6, [x4, #0x20]
@@ -81,8 +82,7 @@
 ;;       ldr     x4, [x0, #0x28]
 ;;       ldr     w4, [x4, #8]
 ;;       str     w4, [x1, #4]
-;;       mov     x5, #0x20
-;;       str     w5, [x1, #8]
+;;       str     w2, [x1, #8]
 ;;       mov     w7, #0x2a
 ;;       str     w7, [x1, #0x18]
 ;;       mov     x2, x19
@@ -100,11 +100,11 @@
 ;;       cset    x15, hs
 ;;       tst     w15, #0xff
 ;;       b.ne    #0x200
-;;  120: ldur    x2, [sp, #0x18]
-;;       ldr     x1, [x2, #0x28]
+;;  120: ldur    x4, [sp, #0x18]
+;;       ldr     x1, [x4, #0x28]
 ;;       cmp     x13, x1
 ;;       b.hi    #0x1e8
-;;  130: ldr     x1, [x2, #0x20]
+;;  130: ldr     x1, [x4, #0x20]
 ;;       add     x0, x1, w0, uxtw
 ;;       ldr     w0, [x0, #0x18]
 ;;       stur    w0, [sp, #8]
diff --git a/tests/disas/exceptions.wat b/tests/disas/exceptions.wat
index a544f5701bcd..0c3642601120 100644
--- a/tests/disas/exceptions.wat
+++ b/tests/disas/exceptions.wat
@@ -23,7 +23,7 @@
 ;;       movq    0x18(%r10), %r10
 ;;       addq    $0x50, %r10
 ;;       cmpq    %rsp, %r10
-;;       ja      0xec
+;;       ja      0xeb
 ;;   19: subq    $0x40, %rsp
 ;;       movq    %rbx, 0x10(%rsp)
 ;;       movq    %r12, 0x18(%rsp)
@@ -41,7 +41,7 @@
 ;;       leaq    0x30(%rcx), %rax
 ;;       movl    4(%rdx), %edi
 ;;       cmpq    %rdi, %rax
-;;       ja      0xb6
+;;       ja      0xb5
 ;;   5f: leal    0x30(%rsi), %eax
 ;;       movl    %eax, (%rdx)
 ;;       movq    8(%rbx), %rax
@@ -51,10 +51,9 @@
 ;;       movq    0x28(%rbx), %rax
 ;;       movl    0xc(%rax), %eax
 ;;       movl    %eax, 4(%rdi, %rcx)
-;;       movl    $0x30, %eax
-;;       movl    %eax, 8(%rdi, %rcx)
-;;       movq    %r14, %rdi
-;;       movl    %edi, 0x18(%rdx)
+;;       movl    $0x30, 8(%rdi, %rcx)
+;;       movq    %r14, %rcx
+;;       movl    %ecx, 0x18(%rdx)
 ;;       movq    %r13, %rcx
 ;;       movq    %rcx, 0x20(%rdx)
 ;;       movq    %r12, %rax
@@ -63,8 +62,8 @@
 ;;       movq    %rbx, %rdi
 ;;       movq    %rbx, (%rsp)
 ;;       callq   0x42e
-;;       jmp     0xea
-;;   b6: movl    $0x4000002, %esi
+;;       jmp     0xe9
+;;   b5: movl    $0x4000002, %esi
 ;;       movq    0x28(%rbx), %rax
 ;;       movl    0xc(%rax), %edx
 ;;       movl    $0x30, %ecx
@@ -74,10 +73,10 @@
 ;;       movq    8(%rbx), %rcx
 ;;       movl    %eax, %edx
 ;;       addq    0x20(%rcx), %rdx
+;;       movq    %r14, %rcx
 ;;       movq    %rax, %rsi
-;;       movq    %r14, %rdi
-;;       jmp     0x8e
-;;   ea: ud2
+;;       jmp     0x8d
+;;   e9: ud2
 ;;       ud2
 ;;
 ;; wasm[0]::function[1]::catch:
diff --git a/tests/disas/fixed-size-memory.wat b/tests/disas/fixed-size-memory.wat
index b3f59e57d3fc..2c7b5fd708d0 100644
--- a/tests/disas/fixed-size-memory.wat
+++ b/tests/disas/fixed-size-memory.wat
@@ -38,7 +38,8 @@
 ;; @0041                               trapnz v6, heap_oob
 ;; @0041                               v7 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0041                               v8 = iadd v7, v4
-;; @0041                               istore8 little region4 v3, v8
+;; @0041                               v9 = ireduce.i8 v3
+;; @0041                               store little region4 v9, v8
 ;; @0044                               jump block1
 ;;
 ;;                                 block1:
@@ -63,9 +64,10 @@
 ;; @0049                               trapnz v5, heap_oob
 ;; @0049                               v6 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0049                               v7 = iadd v6, v3
-;; @0049                               v8 = uload8.i32 little region4 v7
+;; @0049                               v8 = load.i8 little region4 v7
+;; @0049                               v9 = uextend.i32 v8
 ;; @004c                               jump block1
 ;;
 ;;                                 block1:
-;; @004c                               return v8
+;; @004c                               return v9
 ;; }
diff --git a/tests/disas/gc/array-new-data.wat b/tests/disas/gc/array-new-data.wat
index 3da18b18d8d7..1f36287a2185 100644
--- a/tests/disas/gc/array-new-data.wat
+++ b/tests/disas/gc/array-new-data.wat
@@ -11,70 +11,6 @@
     local.get 1
     array.new_data $a $passive)
 )
-;; function u0:0(i64 vmctx, i64, i32, i32) -> i32 tail {
-;;     ss0 = explicit_slot 4, align = 4
-;;     gv0 = vmctx
-;;     gv1 = load.i64 notrap aligned readonly gv0+8
-;;     gv2 = load.i64 notrap aligned gv1+24
-;;     gv3 = vmctx
-;;     gv4 = load.i64 notrap aligned readonly can_move gv3+8
-;;     gv5 = load.i64 notrap aligned readonly can_move gv4+32
-;;     gv6 = load.i64 notrap aligned gv4+40
-;;     sig0 = (i64 vmctx, i32, i32, i32) -> i64 tail
-;;     sig1 = (i64 vmctx, i32, i32, i32, i32) -> i32 tail
-;;     sig2 = (i64 vmctx, i64, i64, i64) tail
-;;     fn0 = colocated u805306368:6 sig0
-;;     fn1 = colocated u805306368:26 sig1
-;;     fn2 = colocated u805306368:4 sig2
-;;     stack_limit = gv2
-;;
-;;                                 block0(v0: i64, v1: i64, v2: i32, v3: i32):
-;; @0025                               v5 = uextend.i64 v3
-;;                                     v72 = iconst.i64 32
-;; @0025                               v7 = ushr v5, v72  ; v72 = 32
-;; @0025                               trapnz v7, heap_oob
-;; @0025                               v10 = uload32 notrap aligned v0+48
-;; @0025                               v11 = uextend.i64 v2
-;; @0025                               v13 = iadd v11, v5
-;; @0025                               v14 = icmp ugt v13, v10
-;; @0025                               trapnz v14, heap_oob
-;; @0025                               v15 = iconst.i32 0
-;; @0025                               v16 = call fn0(v0, v15, v2, v3)  ; v15 = 0
-;; @0025                               trapnz v7, user18
-;; @0025                               v17 = iconst.i32 28
-;; @0025                               v22 = uadd_overflow_trap v17, v3, user18  ; v17 = 28
-;; @0025                               v24 = iconst.i32 -1476395008
-;; @0025                               v26 = load.i64 notrap aligned readonly can_move v0+40
-;; @0025                               v27 = load.i32 notrap aligned readonly can_move v26
-;; @0025                               v28 = iconst.i32 8
-;; @0025                               v29 = call fn1(v0, v24, v27, v22, v28)  ; v24 = -1476395008, v28 = 8
-;;                                     v69 = stack_addr.i64 ss0
-;;                                     store notrap v29, v69
-;; @0025                               v67 = load.i64 notrap aligned readonly can_move v0+8
-;; @0025                               v30 = load.i64 notrap aligned readonly can_move v67+32
-;; @0025                               v31 = uextend.i64 v29
-;; @0025                               v32 = iadd v30, v31
-;;                                     v65 = iconst.i64 24
-;; @0025                               v33 = iadd v32, v65  ; v65 = 24
-;; @0025                               store user2 v3, v33
-;; @0025                               v41 = ushr v5, v72  ; v72 = 32
-;; @0025                               trapnz v41, user2
-;; @0025                               v44 = uadd_overflow_trap v3, v17, user2  ; v17 = 28
-;;                                     v58 = load.i32 notrap v69
-;; @0025                               v48 = uadd_overflow_trap v58, v44, user2
-;; @0025                               v49 = uextend.i64 v48
-;; @0025                               v51 = iadd v30, v49
-;; @0025                               v52 = isub v44, v17  ; v17 = 28
-;; @0025                               v53 = uextend.i64 v52
-;; @0025                               v54 = isub v51, v53
-;; @0025                               call fn2(v0, v54, v16, v5), stack_map=[i32 @ ss0+0]
-;;                                     v57 = load.i32 notrap v69
-;; @0029                               jump block1
-;;
-;;                                 block1:
-;; @0029                               return v57
-;; }
-
 ;; function u0:0(i64 vmctx, i64, i32, i32) -> i32 tail {
 ;;     ss0 = explicit_slot 4, align = 4
 ;;     region0 = 8 "VMContext+0x8"
@@ -128,22 +64,21 @@
 ;; @0025                               brif v34, block2, block3
 ;;
 ;;                                 block2:
-;;                                     v120 = iconst.i32 15
-;;                                     v121 = iadd.i32 v22, v120  ; v120 = 15
-;;                                     v124 = iconst.i32 -16
-;;                                     v125 = band v121, v124  ; v124 = -16
-;;                                     v127 = iadd.i32 v24, v125
-;; @0025                               store notrap aligned region5 v127, v23
-;;                                     v141 = iconst.i32 -1476395002
-;;                                     v142 = load.i64 notrap aligned readonly can_move region0 v0+8
-;;                                     v143 = load.i64 notrap aligned readonly can_move region9 v142+32
-;; @0025                               v48 = iadd v143, v31
-;; @0025                               store user2 region10 v141, v48  ; v141 = -1476395002
-;;                                     v144 = load.i64 notrap aligned readonly can_move region7 v0+40
-;;                                     v145 = load.i32 notrap aligned readonly can_move region8 v144
-;; @0025                               store user2 region10 v145, v48+4
-;;                                     v146 = band.i64 v29, v28  ; v28 = -16
-;; @0025                               istore32 user2 region10 v146, v48+8
+;;                                     v121 = iconst.i32 15
+;;                                     v122 = iadd.i32 v22, v121  ; v121 = 15
+;;                                     v125 = iconst.i32 -16
+;;                                     v126 = band v122, v125  ; v125 = -16
+;;                                     v128 = iadd.i32 v24, v126
+;; @0025                               store notrap aligned region5 v128, v23
+;;                                     v142 = iconst.i32 -1476395002
+;;                                     v143 = load.i64 notrap aligned readonly can_move region0 v0+8
+;;                                     v144 = load.i64 notrap aligned readonly can_move region9 v143+32
+;; @0025                               v48 = iadd v144, v31
+;; @0025                               store user2 region10 v142, v48  ; v142 = -1476395002
+;;                                     v145 = load.i64 notrap aligned readonly can_move region7 v0+40
+;;                                     v146 = load.i32 notrap aligned readonly can_move region8 v145
+;; @0025                               store user2 region10 v146, v48+4
+;; @0025                               store user2 region10 v126, v48+8
 ;; @0025                               jump block4(v24, v48)
 ;;
 ;;                                 block3 cold:
@@ -158,39 +93,39 @@
 ;; @0025                               v43 = iadd v41, v42
 ;; @0025                               jump block4(v39, v43)
 ;;
-;;                                 block4(v52: i32, v53: i64):
-;;                                     v112 = stack_addr.i64 ss0
-;;                                     store notrap aligned region12 v52, v112
-;; @0025                               v54 = iconst.i64 16
-;; @0025                               v55 = iadd v53, v54  ; v54 = 16
-;; @0025                               store.i32 user2 region10 v3, v55
-;; @0025                               trapz v52, user16
+;;                                 block4(v53: i32, v54: i64):
+;;                                     v113 = stack_addr.i64 ss0
+;;                                     store notrap aligned region12 v53, v113
+;; @0025                               v55 = iconst.i64 16
+;; @0025                               v56 = iadd v54, v55  ; v55 = 16
+;; @0025                               store.i32 user2 region10 v3, v56
+;; @0025                               trapz v53, user16
 ;;                                     v147 = load.i64 notrap aligned readonly can_move region0 v0+8
 ;;                                     v148 = load.i64 notrap aligned readonly can_move region9 v147+32
-;; @0025                               v57 = uextend.i64 v52
-;; @0025                               v60 = iadd v148, v57
-;; @0025                               v62 = iadd v60, v54  ; v54 = 16
-;; @0025                               v63 = load.i32 user2 readonly region10 v62
-;; @0025                               v64 = uextend.i64 v63
-;; @0025                               v70 = icmp.i64 ugt v7, v64
-;; @0025                               trapnz v70, user17
-;; @0025                               v81 = load.i32 notrap aligned region2 v0+56
-;; @0025                               v82 = uextend.i64 v81
-;; @0025                               v88 = icmp.i64 ugt v10, v82
-;; @0025                               trapnz v88, heap_oob
-;; @0025                               v89 = load.i64 notrap aligned region3 v0+48
-;; @0025                               v100 = load.i64 notrap aligned region11 v147+40
-;; @0025                               v75 = iconst.i64 20
-;; @0025                               v76 = iadd v60, v75  ; v75 = 20
-;; @0025                               v102 = uadd_overflow_trap v76, v7, user2
-;; @0025                               v101 = iadd v148, v100
-;; @0025                               v103 = icmp ugt v102, v101
-;; @0025                               trapnz v103, user2
-;; @0025                               v91 = iadd v89, v6
-;; @0025                               call fn1(v0, v76, v91, v7), stack_map=[i32 @ ss0+0]
+;; @0025                               v58 = uextend.i64 v53
+;; @0025                               v61 = iadd v148, v58
+;; @0025                               v63 = iadd v61, v55  ; v55 = 16
+;; @0025                               v64 = load.i32 user2 readonly region10 v63
+;; @0025                               v65 = uextend.i64 v64
+;; @0025                               v71 = icmp.i64 ugt v7, v65
+;; @0025                               trapnz v71, user17
+;; @0025                               v82 = load.i32 notrap aligned region2 v0+56
+;; @0025                               v83 = uextend.i64 v82
+;; @0025                               v89 = icmp.i64 ugt v10, v83
+;; @0025                               trapnz v89, heap_oob
+;; @0025                               v90 = load.i64 notrap aligned region3 v0+48
+;; @0025                               v101 = load.i64 notrap aligned region11 v147+40
+;; @0025                               v76 = iconst.i64 20
+;; @0025                               v77 = iadd v61, v76  ; v76 = 20
+;; @0025                               v103 = uadd_overflow_trap v77, v7, user2
+;; @0025                               v102 = iadd v148, v101
+;; @0025                               v104 = icmp ugt v103, v102
+;; @0025                               trapnz v104, user2
+;; @0025                               v92 = iadd v90, v6
+;; @0025                               call fn1(v0, v77, v92, v7), stack_map=[i32 @ ss0+0]
 ;; @0029                               jump block1
 ;;
 ;;                                 block1:
-;;                                     v105 = load.i32 notrap aligned region12 v112
-;; @0029                               return v105
+;;                                     v106 = load.i32 notrap aligned region12 v113
+;; @0029                               return v106
 ;; }
diff --git a/tests/disas/gc/array-new-default-anyref.wat b/tests/disas/gc/array-new-default-anyref.wat
index 4daa0f087b41..1cf6950aaadf 100644
--- a/tests/disas/gc/array-new-default-anyref.wat
+++ b/tests/disas/gc/array-new-default-anyref.wat
@@ -29,15 +29,15 @@
 ;;
 ;;                                 block0(v0: i64, v1: i64, v2: i32):
 ;; @001f                               v4 = uextend.i64 v2
-;;                                     v87 = iconst.i64 2
-;;                                     v88 = ishl v4, v87  ; v87 = 2
+;;                                     v88 = iconst.i64 2
+;;                                     v89 = ishl v4, v88  ; v88 = 2
 ;; @001f                               v7 = iconst.i64 32
-;; @001f                               v8 = ushr v88, v7  ; v7 = 32
+;; @001f                               v8 = ushr v89, v7  ; v7 = 32
 ;; @001f                               trapnz v8, user18
 ;; @001f                               v3 = iconst.i32 20
-;;                                     v94 = iconst.i32 2
-;;                                     v95 = ishl v2, v94  ; v94 = 2
-;; @001f                               v10 = uadd_overflow_trap v3, v95, user18  ; v3 = 20
+;;                                     v95 = iconst.i32 2
+;;                                     v96 = ishl v2, v95  ; v95 = 2
+;; @001f                               v10 = uadd_overflow_trap v3, v96, user18  ; v3 = 20
 ;; @001f                               v11 = load.i64 notrap aligned readonly can_move region2 v0+32
 ;; @001f                               v12 = load.i32 notrap aligned region3 v11
 ;; @001f                               v13 = load.i32 notrap aligned region4 v11+4
@@ -53,22 +53,21 @@
 ;; @001f                               brif v22, block2, block3
 ;;
 ;;                                 block2:
-;;                                     v103 = iconst.i32 15
-;;                                     v104 = iadd.i32 v10, v103  ; v103 = 15
-;;                                     v107 = iconst.i32 -16
-;;                                     v108 = band v104, v107  ; v107 = -16
-;;                                     v110 = iadd.i32 v12, v108
-;; @001f                               store notrap aligned region3 v110, v11
-;;                                     v126 = iconst.i32 -1476394994
-;;                                     v127 = load.i64 notrap aligned readonly can_move region0 v0+8
-;;                                     v128 = load.i64 notrap aligned readonly can_move region7 v127+32
-;; @001f                               v36 = iadd v128, v19
-;; @001f                               store user2 region8 v126, v36  ; v126 = -1476394994
-;;                                     v129 = load.i64 notrap aligned readonly can_move region5 v0+40
-;;                                     v130 = load.i32 notrap aligned readonly can_move region6 v129
-;; @001f                               store user2 region8 v130, v36+4
-;;                                     v131 = band.i64 v17, v16  ; v16 = -16
-;; @001f                               istore32 user2 region8 v131, v36+8
+;;                                     v104 = iconst.i32 15
+;;                                     v105 = iadd.i32 v10, v104  ; v104 = 15
+;;                                     v108 = iconst.i32 -16
+;;                                     v109 = band v105, v108  ; v108 = -16
+;;                                     v111 = iadd.i32 v12, v109
+;; @001f                               store notrap aligned region3 v111, v11
+;;                                     v127 = iconst.i32 -1476394994
+;;                                     v128 = load.i64 notrap aligned readonly can_move region0 v0+8
+;;                                     v129 = load.i64 notrap aligned readonly can_move region7 v128+32
+;; @001f                               v36 = iadd v129, v19
+;; @001f                               store user2 region8 v127, v36  ; v127 = -1476394994
+;;                                     v130 = load.i64 notrap aligned readonly can_move region5 v0+40
+;;                                     v131 = load.i32 notrap aligned readonly can_move region6 v130
+;; @001f                               store user2 region8 v131, v36+4
+;; @001f                               store user2 region8 v109, v36+8
 ;; @001f                               jump block4(v12, v36)
 ;;
 ;;                                 block3 cold:
@@ -83,45 +82,45 @@
 ;; @001f                               v31 = iadd v29, v30
 ;; @001f                               jump block4(v27, v31)
 ;;
-;;                                 block4(v40: i32, v41: i64):
-;; @001f                               v42 = iconst.i64 16
-;; @001f                               v43 = iadd v41, v42  ; v42 = 16
-;; @001f                               store.i32 user2 region8 v2, v43
-;; @001f                               trapz v40, user16
+;;                                 block4(v41: i32, v42: i64):
+;; @001f                               v43 = iconst.i64 16
+;; @001f                               v44 = iadd v42, v43  ; v43 = 16
+;; @001f                               store.i32 user2 region8 v2, v44
+;; @001f                               trapz v41, user16
 ;;                                     v132 = load.i64 notrap aligned readonly can_move region0 v0+8
 ;;                                     v133 = load.i64 notrap aligned readonly can_move region7 v132+32
-;; @001f                               v46 = uextend.i64 v40
-;; @001f                               v49 = iadd v133, v46
-;; @001f                               v51 = iadd v49, v42  ; v42 = 16
-;; @001f                               v52 = load.i32 user2 readonly region8 v51
-;; @001f                               v53 = uextend.i64 v52
-;; @001f                               v59 = icmp.i64 ugt v4, v53
-;; @001f                               trapnz v59, user17
-;; @001f                               v76 = load.i64 notrap aligned region9 v132+40
-;; @001f                               v64 = iconst.i64 20
-;; @001f                               v65 = iadd v49, v64  ; v64 = 20
-;; @001f                               v78 = uadd_overflow_trap v65, v88, user2
-;; @001f                               v77 = iadd v133, v76
-;; @001f                               v79 = icmp ugt v78, v77
-;; @001f                               trapnz v79, user2
-;;                                     v112 = iconst.i64 0
-;; @001f                               v82 = icmp.i64 eq v4, v112  ; v112 = 0
-;; @001f                               v44 = iconst.i32 0
+;; @001f                               v47 = uextend.i64 v41
+;; @001f                               v50 = iadd v133, v47
+;; @001f                               v52 = iadd v50, v43  ; v43 = 16
+;; @001f                               v53 = load.i32 user2 readonly region8 v52
+;; @001f                               v54 = uextend.i64 v53
+;; @001f                               v60 = icmp.i64 ugt v4, v54
+;; @001f                               trapnz v60, user17
+;; @001f                               v77 = load.i64 notrap aligned region9 v132+40
+;; @001f                               v65 = iconst.i64 20
+;; @001f                               v66 = iadd v50, v65  ; v65 = 20
+;; @001f                               v79 = uadd_overflow_trap v66, v89, user2
+;; @001f                               v78 = iadd v133, v77
+;; @001f                               v80 = icmp ugt v79, v78
+;; @001f                               trapnz v80, user2
+;;                                     v113 = iconst.i64 0
+;; @001f                               v83 = icmp.i64 eq v4, v113  ; v113 = 0
+;; @001f                               v45 = iconst.i32 0
 ;; @001f                               v5 = iconst.i64 4
-;; @001f                               v80 = iadd v65, v88
-;; @001f                               brif v82, block6, block5(v65)
+;; @001f                               v81 = iadd v66, v89
+;; @001f                               brif v83, block6, block5(v66)
 ;;
-;;                                 block5(v83: i64):
+;;                                 block5(v84: i64):
 ;;                                     v134 = iconst.i32 0
-;; @001f                               store user2 little region8 v134, v83  ; v134 = 0
+;; @001f                               store user2 little region8 v134, v84  ; v134 = 0
 ;;                                     v135 = iconst.i64 4
-;;                                     v136 = iadd v83, v135  ; v135 = 4
-;; @001f                               v86 = icmp eq v136, v80
-;; @001f                               brif v86, block6, block5(v136)
+;;                                     v136 = iadd v84, v135  ; v135 = 4
+;; @001f                               v87 = icmp eq v136, v81
+;; @001f                               brif v87, block6, block5(v136)
 ;;
 ;;                                 block6:
 ;; @0022                               jump block1
 ;;
 ;;                                 block1:
-;; @0022                               return v40
+;; @0022                               return v41
 ;; }
diff --git a/tests/disas/gc/array-new-default-exnref.wat b/tests/disas/gc/array-new-default-exnref.wat
index baeed321b8ca..9240eb55ecab 100644
--- a/tests/disas/gc/array-new-default-exnref.wat
+++ b/tests/disas/gc/array-new-default-exnref.wat
@@ -29,15 +29,15 @@
 ;;
 ;;                                 block0(v0: i64, v1: i64, v2: i32):
 ;; @001f                               v4 = uextend.i64 v2
-;;                                     v87 = iconst.i64 2
-;;                                     v88 = ishl v4, v87  ; v87 = 2
+;;                                     v88 = iconst.i64 2
+;;                                     v89 = ishl v4, v88  ; v88 = 2
 ;; @001f                               v7 = iconst.i64 32
-;; @001f                               v8 = ushr v88, v7  ; v7 = 32
+;; @001f                               v8 = ushr v89, v7  ; v7 = 32
 ;; @001f                               trapnz v8, user18
 ;; @001f                               v3 = iconst.i32 20
-;;                                     v94 = iconst.i32 2
-;;                                     v95 = ishl v2, v94  ; v94 = 2
-;; @001f                               v10 = uadd_overflow_trap v3, v95, user18  ; v3 = 20
+;;                                     v95 = iconst.i32 2
+;;                                     v96 = ishl v2, v95  ; v95 = 2
+;; @001f                               v10 = uadd_overflow_trap v3, v96, user18  ; v3 = 20
 ;; @001f                               v11 = load.i64 notrap aligned readonly can_move region2 v0+32
 ;; @001f                               v12 = load.i32 notrap aligned region3 v11
 ;; @001f                               v13 = load.i32 notrap aligned region4 v11+4
@@ -53,22 +53,21 @@
 ;; @001f                               brif v22, block2, block3
 ;;
 ;;                                 block2:
-;;                                     v103 = iconst.i32 15
-;;                                     v104 = iadd.i32 v10, v103  ; v103 = 15
-;;                                     v107 = iconst.i32 -16
-;;                                     v108 = band v104, v107  ; v107 = -16
-;;                                     v110 = iadd.i32 v12, v108
-;; @001f                               store notrap aligned region3 v110, v11
-;;                                     v126 = iconst.i32 -1476394994
-;;                                     v127 = load.i64 notrap aligned readonly can_move region0 v0+8
-;;                                     v128 = load.i64 notrap aligned readonly can_move region7 v127+32
-;; @001f                               v36 = iadd v128, v19
-;; @001f                               store user2 region8 v126, v36  ; v126 = -1476394994
-;;                                     v129 = load.i64 notrap aligned readonly can_move region5 v0+40
-;;                                     v130 = load.i32 notrap aligned readonly can_move region6 v129
-;; @001f                               store user2 region8 v130, v36+4
-;;                                     v131 = band.i64 v17, v16  ; v16 = -16
-;; @001f                               istore32 user2 region8 v131, v36+8
+;;                                     v104 = iconst.i32 15
+;;                                     v105 = iadd.i32 v10, v104  ; v104 = 15
+;;                                     v108 = iconst.i32 -16
+;;                                     v109 = band v105, v108  ; v108 = -16
+;;                                     v111 = iadd.i32 v12, v109
+;; @001f                               store notrap aligned region3 v111, v11
+;;                                     v127 = iconst.i32 -1476394994
+;;                                     v128 = load.i64 notrap aligned readonly can_move region0 v0+8
+;;                                     v129 = load.i64 notrap aligned readonly can_move region7 v128+32
+;; @001f                               v36 = iadd v129, v19
+;; @001f                               store user2 region8 v127, v36  ; v127 = -1476394994
+;;                                     v130 = load.i64 notrap aligned readonly can_move region5 v0+40
+;;                                     v131 = load.i32 notrap aligned readonly can_move region6 v130
+;; @001f                               store user2 region8 v131, v36+4
+;; @001f                               store user2 region8 v109, v36+8
 ;; @001f                               jump block4(v12, v36)
 ;;
 ;;                                 block3 cold:
@@ -83,45 +82,45 @@
 ;; @001f                               v31 = iadd v29, v30
 ;; @001f                               jump block4(v27, v31)
 ;;
-;;                                 block4(v40: i32, v41: i64):
-;; @001f                               v42 = iconst.i64 16
-;; @001f                               v43 = iadd v41, v42  ; v42 = 16
-;; @001f                               store.i32 user2 region8 v2, v43
-;; @001f                               trapz v40, user16
+;;                                 block4(v41: i32, v42: i64):
+;; @001f                               v43 = iconst.i64 16
+;; @001f                               v44 = iadd v42, v43  ; v43 = 16
+;; @001f                               store.i32 user2 region8 v2, v44
+;; @001f                               trapz v41, user16
 ;;                                     v132 = load.i64 notrap aligned readonly can_move region0 v0+8
 ;;                                     v133 = load.i64 notrap aligned readonly can_move region7 v132+32
-;; @001f                               v46 = uextend.i64 v40
-;; @001f                               v49 = iadd v133, v46
-;; @001f                               v51 = iadd v49, v42  ; v42 = 16
-;; @001f                               v52 = load.i32 user2 readonly region8 v51
-;; @001f                               v53 = uextend.i64 v52
-;; @001f                               v59 = icmp.i64 ugt v4, v53
-;; @001f                               trapnz v59, user17
-;; @001f                               v76 = load.i64 notrap aligned region9 v132+40
-;; @001f                               v64 = iconst.i64 20
-;; @001f                               v65 = iadd v49, v64  ; v64 = 20
-;; @001f                               v78 = uadd_overflow_trap v65, v88, user2
-;; @001f                               v77 = iadd v133, v76
-;; @001f                               v79 = icmp ugt v78, v77
-;; @001f                               trapnz v79, user2
-;;                                     v112 = iconst.i64 0
-;; @001f                               v82 = icmp.i64 eq v4, v112  ; v112 = 0
-;; @001f                               v44 = iconst.i32 0
+;; @001f                               v47 = uextend.i64 v41
+;; @001f                               v50 = iadd v133, v47
+;; @001f                               v52 = iadd v50, v43  ; v43 = 16
+;; @001f                               v53 = load.i32 user2 readonly region8 v52
+;; @001f                               v54 = uextend.i64 v53
+;; @001f                               v60 = icmp.i64 ugt v4, v54
+;; @001f                               trapnz v60, user17
+;; @001f                               v77 = load.i64 notrap aligned region9 v132+40
+;; @001f                               v65 = iconst.i64 20
+;; @001f                               v66 = iadd v50, v65  ; v65 = 20
+;; @001f                               v79 = uadd_overflow_trap v66, v89, user2
+;; @001f                               v78 = iadd v133, v77
+;; @001f                               v80 = icmp ugt v79, v78
+;; @001f                               trapnz v80, user2
+;;                                     v113 = iconst.i64 0
+;; @001f                               v83 = icmp.i64 eq v4, v113  ; v113 = 0
+;; @001f                               v45 = iconst.i32 0
 ;; @001f                               v5 = iconst.i64 4
-;; @001f                               v80 = iadd v65, v88
-;; @001f                               brif v82, block6, block5(v65)
+;; @001f                               v81 = iadd v66, v89
+;; @001f                               brif v83, block6, block5(v66)
 ;;
-;;                                 block5(v83: i64):
+;;                                 block5(v84: i64):
 ;;                                     v134 = iconst.i32 0
-;; @001f                               store user2 little region8 v134, v83  ; v134 = 0
+;; @001f                               store user2 little region8 v134, v84  ; v134 = 0
 ;;                                     v135 = iconst.i64 4
-;;                                     v136 = iadd v83, v135  ; v135 = 4
-;; @001f                               v86 = icmp eq v136, v80
-;; @001f                               brif v86, block6, block5(v136)
+;;                                     v136 = iadd v84, v135  ; v135 = 4
+;; @001f                               v87 = icmp eq v136, v81
+;; @001f                               brif v87, block6, block5(v136)
 ;;
 ;;                                 block6:
 ;; @0022                               jump block1
 ;;
 ;;                                 block1:
-;; @0022                               return v40
+;; @0022                               return v41
 ;; }
diff --git a/tests/disas/gc/array-new-default-externref.wat b/tests/disas/gc/array-new-default-externref.wat
index 78db3263ea42..4aea5c490e76 100644
--- a/tests/disas/gc/array-new-default-externref.wat
+++ b/tests/disas/gc/array-new-default-externref.wat
@@ -29,15 +29,15 @@
 ;;
 ;;                                 block0(v0: i64, v1: i64, v2: i32):
 ;; @001f                               v4 = uextend.i64 v2
-;;                                     v87 = iconst.i64 2
-;;                                     v88 = ishl v4, v87  ; v87 = 2
+;;                                     v88 = iconst.i64 2
+;;                                     v89 = ishl v4, v88  ; v88 = 2
 ;; @001f                               v7 = iconst.i64 32
-;; @001f                               v8 = ushr v88, v7  ; v7 = 32
+;; @001f                               v8 = ushr v89, v7  ; v7 = 32
 ;; @001f                               trapnz v8, user18
 ;; @001f                               v3 = iconst.i32 20
-;;                                     v94 = iconst.i32 2
-;;                                     v95 = ishl v2, v94  ; v94 = 2
-;; @001f                               v10 = uadd_overflow_trap v3, v95, user18  ; v3 = 20
+;;                                     v95 = iconst.i32 2
+;;                                     v96 = ishl v2, v95  ; v95 = 2
+;; @001f                               v10 = uadd_overflow_trap v3, v96, user18  ; v3 = 20
 ;; @001f                               v11 = load.i64 notrap aligned readonly can_move region2 v0+32
 ;; @001f                               v12 = load.i32 notrap aligned region3 v11
 ;; @001f                               v13 = load.i32 notrap aligned region4 v11+4
@@ -53,22 +53,21 @@
 ;; @001f                               brif v22, block2, block3
 ;;
 ;;                                 block2:
-;;                                     v103 = iconst.i32 15
-;;                                     v104 = iadd.i32 v10, v103  ; v103 = 15
-;;                                     v107 = iconst.i32 -16
-;;                                     v108 = band v104, v107  ; v107 = -16
-;;                                     v110 = iadd.i32 v12, v108
-;; @001f                               store notrap aligned region3 v110, v11
-;;                                     v126 = iconst.i32 -1476394994
-;;                                     v127 = load.i64 notrap aligned readonly can_move region0 v0+8
-;;                                     v128 = load.i64 notrap aligned readonly can_move region7 v127+32
-;; @001f                               v36 = iadd v128, v19
-;; @001f                               store user2 region8 v126, v36  ; v126 = -1476394994
-;;                                     v129 = load.i64 notrap aligned readonly can_move region5 v0+40
-;;                                     v130 = load.i32 notrap aligned readonly can_move region6 v129
-;; @001f                               store user2 region8 v130, v36+4
-;;                                     v131 = band.i64 v17, v16  ; v16 = -16
-;; @001f                               istore32 user2 region8 v131, v36+8
+;;                                     v104 = iconst.i32 15
+;;                                     v105 = iadd.i32 v10, v104  ; v104 = 15
+;;                                     v108 = iconst.i32 -16
+;;                                     v109 = band v105, v108  ; v108 = -16
+;;                                     v111 = iadd.i32 v12, v109
+;; @001f                               store notrap aligned region3 v111, v11
+;;                                     v127 = iconst.i32 -1476394994
+;;                                     v128 = load.i64 notrap aligned readonly can_move region0 v0+8
+;;                                     v129 = load.i64 notrap aligned readonly can_move region7 v128+32
+;; @001f                               v36 = iadd v129, v19
+;; @001f                               store user2 region8 v127, v36  ; v127 = -1476394994
+;;                                     v130 = load.i64 notrap aligned readonly can_move region5 v0+40
+;;                                     v131 = load.i32 notrap aligned readonly can_move region6 v130
+;; @001f                               store user2 region8 v131, v36+4
+;; @001f                               store user2 region8 v109, v36+8
 ;; @001f                               jump block4(v12, v36)
 ;;
 ;;                                 block3 cold:
@@ -83,45 +82,45 @@
 ;; @001f                               v31 = iadd v29, v30
 ;; @001f                               jump block4(v27, v31)
 ;;
-;;                                 block4(v40: i32, v41: i64):
-;; @001f                               v42 = iconst.i64 16
-;; @001f                               v43 = iadd v41, v42  ; v42 = 16
-;; @001f                               store.i32 user2 region8 v2, v43
-;; @001f                               trapz v40, user16
+;;                                 block4(v41: i32, v42: i64):
+;; @001f                               v43 = iconst.i64 16
+;; @001f                               v44 = iadd v42, v43  ; v43 = 16
+;; @001f                               store.i32 user2 region8 v2, v44
+;; @001f                               trapz v41, user16
 ;;                                     v132 = load.i64 notrap aligned readonly can_move region0 v0+8
 ;;                                     v133 = load.i64 notrap aligned readonly can_move region7 v132+32
-;; @001f                               v46 = uextend.i64 v40
-;; @001f                               v49 = iadd v133, v46
-;; @001f                               v51 = iadd v49, v42  ; v42 = 16
-;; @001f                               v52 = load.i32 user2 readonly region8 v51
-;; @001f                               v53 = uextend.i64 v52
-;; @001f                               v59 = icmp.i64 ugt v4, v53
-;; @001f                               trapnz v59, user17
-;; @001f                               v76 = load.i64 notrap aligned region9 v132+40
-;; @001f                               v64 = iconst.i64 20
-;; @001f                               v65 = iadd v49, v64  ; v64 = 20
-;; @001f                               v78 = uadd_overflow_trap v65, v88, user2
-;; @001f                               v77 = iadd v133, v76
-;; @001f                               v79 = icmp ugt v78, v77
-;; @001f                               trapnz v79, user2
-;;                                     v112 = iconst.i64 0
-;; @001f                               v82 = icmp.i64 eq v4, v112  ; v112 = 0
-;; @001f                               v44 = iconst.i32 0
+;; @001f                               v47 = uextend.i64 v41
+;; @001f                               v50 = iadd v133, v47
+;; @001f                               v52 = iadd v50, v43  ; v43 = 16
+;; @001f                               v53 = load.i32 user2 readonly region8 v52
+;; @001f                               v54 = uextend.i64 v53
+;; @001f                               v60 = icmp.i64 ugt v4, v54
+;; @001f                               trapnz v60, user17
+;; @001f                               v77 = load.i64 notrap aligned region9 v132+40
+;; @001f                               v65 = iconst.i64 20
+;; @001f                               v66 = iadd v50, v65  ; v65 = 20
+;; @001f                               v79 = uadd_overflow_trap v66, v89, user2
+;; @001f                               v78 = iadd v133, v77
+;; @001f                               v80 = icmp ugt v79, v78
+;; @001f                               trapnz v80, user2
+;;                                     v113 = iconst.i64 0
+;; @001f                               v83 = icmp.i64 eq v4, v113  ; v113 = 0
+;; @001f                               v45 = iconst.i32 0
 ;; @001f                               v5 = iconst.i64 4
-;; @001f                               v80 = iadd v65, v88
-;; @001f                               brif v82, block6, block5(v65)
+;; @001f                               v81 = iadd v66, v89
+;; @001f                               brif v83, block6, block5(v66)
 ;;
-;;                                 block5(v83: i64):
+;;                                 block5(v84: i64):
 ;;                                     v134 = iconst.i32 0
-;; @001f                               store user2 little region8 v134, v83  ; v134 = 0
+;; @001f                               store user2 little region8 v134, v84  ; v134 = 0
 ;;                                     v135 = iconst.i64 4
-;;                                     v136 = iadd v83, v135  ; v135 = 4
-;; @001f                               v86 = icmp eq v136, v80
-;; @001f                               brif v86, block6, block5(v136)
+;;                                     v136 = iadd v84, v135  ; v135 = 4
+;; @001f                               v87 = icmp eq v136, v81
+;; @001f                               brif v87, block6, block5(v136)
 ;;
 ;;                                 block6:
 ;; @0022                               jump block1
 ;;
 ;;                                 block1:
-;; @0022                               return v40
+;; @0022                               return v41
 ;; }
diff --git a/tests/disas/gc/array-new-default-f32.wat b/tests/disas/gc/array-new-default-f32.wat
index 0bb1fa00a05a..6d2d4b7365eb 100644
--- a/tests/disas/gc/array-new-default-f32.wat
+++ b/tests/disas/gc/array-new-default-f32.wat
@@ -33,15 +33,15 @@
 ;;
 ;;                                 block0(v0: i64, v1: i64, v2: i32):
 ;; @001f                               v4 = uextend.i64 v2
-;;                                     v90 = iconst.i64 2
-;;                                     v91 = ishl v4, v90  ; v90 = 2
+;;                                     v91 = iconst.i64 2
+;;                                     v92 = ishl v4, v91  ; v91 = 2
 ;; @001f                               v7 = iconst.i64 32
-;; @001f                               v8 = ushr v91, v7  ; v7 = 32
+;; @001f                               v8 = ushr v92, v7  ; v7 = 32
 ;; @001f                               trapnz v8, user18
 ;; @001f                               v3 = iconst.i32 20
-;;                                     v97 = iconst.i32 2
-;;                                     v98 = ishl v2, v97  ; v97 = 2
-;; @001f                               v10 = uadd_overflow_trap v3, v98, user18  ; v3 = 20
+;;                                     v98 = iconst.i32 2
+;;                                     v99 = ishl v2, v98  ; v98 = 2
+;; @001f                               v10 = uadd_overflow_trap v3, v99, user18  ; v3 = 20
 ;; @001f                               v11 = load.i64 notrap aligned readonly can_move region2 v0+32
 ;; @001f                               v12 = load.i32 notrap aligned region3 v11
 ;; @001f                               v13 = load.i32 notrap aligned region4 v11+4
@@ -57,22 +57,21 @@
 ;; @001f                               brif v22, block2, block3
 ;;
 ;;                                 block2:
-;;                                     v106 = iconst.i32 15
-;;                                     v107 = iadd.i32 v10, v106  ; v106 = 15
-;;                                     v110 = iconst.i32 -16
-;;                                     v111 = band v107, v110  ; v110 = -16
-;;                                     v113 = iadd.i32 v12, v111
-;; @001f                               store notrap aligned region3 v113, v11
-;;                                     v129 = iconst.i32 -1476395002
-;;                                     v130 = load.i64 notrap aligned readonly can_move region0 v0+8
-;;                                     v131 = load.i64 notrap aligned readonly can_move region7 v130+32
-;; @001f                               v36 = iadd v131, v19
-;; @001f                               store user2 region8 v129, v36  ; v129 = -1476395002
-;;                                     v132 = load.i64 notrap aligned readonly can_move region5 v0+40
-;;                                     v133 = load.i32 notrap aligned readonly can_move region6 v132
-;; @001f                               store user2 region8 v133, v36+4
-;;                                     v134 = band.i64 v17, v16  ; v16 = -16
-;; @001f                               istore32 user2 region8 v134, v36+8
+;;                                     v107 = iconst.i32 15
+;;                                     v108 = iadd.i32 v10, v107  ; v107 = 15
+;;                                     v111 = iconst.i32 -16
+;;                                     v112 = band v108, v111  ; v111 = -16
+;;                                     v114 = iadd.i32 v12, v112
+;; @001f                               store notrap aligned region3 v114, v11
+;;                                     v130 = iconst.i32 -1476395002
+;;                                     v131 = load.i64 notrap aligned readonly can_move region0 v0+8
+;;                                     v132 = load.i64 notrap aligned readonly can_move region7 v131+32
+;; @001f                               v36 = iadd v132, v19
+;; @001f                               store user2 region8 v130, v36  ; v130 = -1476395002
+;;                                     v133 = load.i64 notrap aligned readonly can_move region5 v0+40
+;;                                     v134 = load.i32 notrap aligned readonly can_move region6 v133
+;; @001f                               store user2 region8 v134, v36+4
+;; @001f                               store user2 region8 v112, v36+8
 ;; @001f                               jump block4(v12, v36)
 ;;
 ;;                                 block3 cold:
@@ -87,34 +86,34 @@
 ;; @001f                               v31 = iadd v29, v30
 ;; @001f                               jump block4(v27, v31)
 ;;
-;;                                 block4(v40: i32, v41: i64):
-;;                                     v89 = stack_addr.i64 ss0
-;;                                     store notrap aligned region10 v40, v89
-;; @001f                               v42 = iconst.i64 16
-;; @001f                               v43 = iadd v41, v42  ; v42 = 16
-;; @001f                               store.i32 user2 region8 v2, v43
-;; @001f                               trapz v40, user16
+;;                                 block4(v41: i32, v42: i64):
+;;                                     v90 = stack_addr.i64 ss0
+;;                                     store notrap aligned region10 v41, v90
+;; @001f                               v43 = iconst.i64 16
+;; @001f                               v44 = iadd v42, v43  ; v43 = 16
+;; @001f                               store.i32 user2 region8 v2, v44
+;; @001f                               trapz v41, user16
 ;;                                     v135 = load.i64 notrap aligned readonly can_move region0 v0+8
 ;;                                     v136 = load.i64 notrap aligned readonly can_move region7 v135+32
-;; @001f                               v46 = uextend.i64 v40
-;; @001f                               v49 = iadd v136, v46
-;; @001f                               v51 = iadd v49, v42  ; v42 = 16
-;; @001f                               v52 = load.i32 user2 readonly region8 v51
-;; @001f                               v53 = uextend.i64 v52
-;; @001f                               v59 = icmp.i64 ugt v4, v53
-;; @001f                               trapnz v59, user17
-;; @001f                               v76 = load.i64 notrap aligned region9 v135+40
-;; @001f                               v64 = iconst.i64 20
-;; @001f                               v65 = iadd v49, v64  ; v64 = 20
-;; @001f                               v78 = uadd_overflow_trap v65, v91, user2
-;; @001f                               v77 = iadd v136, v76
-;; @001f                               v79 = icmp ugt v78, v77
-;; @001f                               trapnz v79, user2
-;; @001f                               v45 = iconst.i32 0
-;; @001f                               call fn1(v0, v65, v45, v91), stack_map=[i32 @ ss0+0]  ; v45 = 0
+;; @001f                               v47 = uextend.i64 v41
+;; @001f                               v50 = iadd v136, v47
+;; @001f                               v52 = iadd v50, v43  ; v43 = 16
+;; @001f                               v53 = load.i32 user2 readonly region8 v52
+;; @001f                               v54 = uextend.i64 v53
+;; @001f                               v60 = icmp.i64 ugt v4, v54
+;; @001f                               trapnz v60, user17
+;; @001f                               v77 = load.i64 notrap aligned region9 v135+40
+;; @001f                               v65 = iconst.i64 20
+;; @001f                               v66 = iadd v50, v65  ; v65 = 20
+;; @001f                               v79 = uadd_overflow_trap v66, v92, user2
+;; @001f                               v78 = iadd v136, v77
+;; @001f                               v80 = icmp ugt v79, v78
+;; @001f                               trapnz v80, user2
+;; @001f                               v46 = iconst.i32 0
+;; @001f                               call fn1(v0, v66, v46, v92), stack_map=[i32 @ ss0+0]  ; v46 = 0
 ;; @0022                               jump block1
 ;;
 ;;                                 block1:
-;;                                     v82 = load.i32 notrap aligned region10 v89
-;; @0022                               return v82
+;;                                     v83 = load.i32 notrap aligned region10 v90
+;; @0022                               return v83
 ;; }
diff --git a/tests/disas/gc/array-new-default-f64.wat b/tests/disas/gc/array-new-default-f64.wat
index 472da45f2867..1fb0bba73f71 100644
--- a/tests/disas/gc/array-new-default-f64.wat
+++ b/tests/disas/gc/array-new-default-f64.wat
@@ -33,15 +33,15 @@
 ;;
 ;;                                 block0(v0: i64, v1: i64, v2: i32):
 ;; @001f                               v4 = uextend.i64 v2
-;;                                     v90 = iconst.i64 3
-;;                                     v91 = ishl v4, v90  ; v90 = 3
+;;                                     v91 = iconst.i64 3
+;;                                     v92 = ishl v4, v91  ; v91 = 3
 ;; @001f                               v7 = iconst.i64 32
-;; @001f                               v8 = ushr v91, v7  ; v7 = 32
+;; @001f                               v8 = ushr v92, v7  ; v7 = 32
 ;; @001f                               trapnz v8, user18
 ;; @001f                               v3 = iconst.i32 24
-;;                                     v97 = iconst.i32 3
-;;                                     v98 = ishl v2, v97  ; v97 = 3
-;; @001f                               v10 = uadd_overflow_trap v3, v98, user18  ; v3 = 24
+;;                                     v98 = iconst.i32 3
+;;                                     v99 = ishl v2, v98  ; v98 = 3
+;; @001f                               v10 = uadd_overflow_trap v3, v99, user18  ; v3 = 24
 ;; @001f                               v11 = load.i64 notrap aligned readonly can_move region2 v0+32
 ;; @001f                               v12 = load.i32 notrap aligned region3 v11
 ;; @001f                               v13 = load.i32 notrap aligned region4 v11+4
@@ -57,22 +57,21 @@
 ;; @001f                               brif v22, block2, block3
 ;;
 ;;                                 block2:
-;;                                     v106 = iconst.i32 15
-;;                                     v107 = iadd.i32 v10, v106  ; v106 = 15
-;;                                     v110 = iconst.i32 -16
-;;                                     v111 = band v107, v110  ; v110 = -16
-;;                                     v113 = iadd.i32 v12, v111
-;; @001f                               store notrap aligned region3 v113, v11
-;;                                     v129 = iconst.i32 -1476395002
-;;                                     v130 = load.i64 notrap aligned readonly can_move region0 v0+8
-;;                                     v131 = load.i64 notrap aligned readonly can_move region7 v130+32
-;; @001f                               v36 = iadd v131, v19
-;; @001f                               store user2 region8 v129, v36  ; v129 = -1476395002
-;;                                     v132 = load.i64 notrap aligned readonly can_move region5 v0+40
-;;                                     v133 = load.i32 notrap aligned readonly can_move region6 v132
-;; @001f                               store user2 region8 v133, v36+4
-;;                                     v134 = band.i64 v17, v16  ; v16 = -16
-;; @001f                               istore32 user2 region8 v134, v36+8
+;;                                     v107 = iconst.i32 15
+;;                                     v108 = iadd.i32 v10, v107  ; v107 = 15
+;;                                     v111 = iconst.i32 -16
+;;                                     v112 = band v108, v111  ; v111 = -16
+;;                                     v114 = iadd.i32 v12, v112
+;; @001f                               store notrap aligned region3 v114, v11
+;;                                     v130 = iconst.i32 -1476395002
+;;                                     v131 = load.i64 notrap aligned readonly can_move region0 v0+8
+;;                                     v132 = load.i64 notrap aligned readonly can_move region7 v131+32
+;; @001f                               v36 = iadd v132, v19
+;; @001f                               store user2 region8 v130, v36  ; v130 = -1476395002
+;;                                     v133 = load.i64 notrap aligned readonly can_move region5 v0+40
+;;                                     v134 = load.i32 notrap aligned readonly can_move region6 v133
+;; @001f                               store user2 region8 v134, v36+4
+;; @001f                               store user2 region8 v112, v36+8
 ;; @001f                               jump block4(v12, v36)
 ;;
 ;;                                 block3 cold:
@@ -87,34 +86,34 @@
 ;; @001f                               v31 = iadd v29, v30
 ;; @001f                               jump block4(v27, v31)
 ;;
-;;                                 block4(v40: i32, v41: i64):
-;;                                     v89 = stack_addr.i64 ss0
-;;                                     store notrap aligned region10 v40, v89
-;; @001f                               v42 = iconst.i64 16
-;; @001f                               v43 = iadd v41, v42  ; v42 = 16
-;; @001f                               store.i32 user2 region8 v2, v43
-;; @001f                               trapz v40, user16
+;;                                 block4(v41: i32, v42: i64):
+;;                                     v90 = stack_addr.i64 ss0
+;;                                     store notrap aligned region10 v41, v90
+;; @001f                               v43 = iconst.i64 16
+;; @001f                               v44 = iadd v42, v43  ; v43 = 16
+;; @001f                               store.i32 user2 region8 v2, v44
+;; @001f                               trapz v41, user16
 ;;                                     v135 = load.i64 notrap aligned readonly can_move region0 v0+8
 ;;                                     v136 = load.i64 notrap aligned readonly can_move region7 v135+32
-;; @001f                               v46 = uextend.i64 v40
-;; @001f                               v49 = iadd v136, v46
-;; @001f                               v51 = iadd v49, v42  ; v42 = 16
-;; @001f                               v52 = load.i32 user2 readonly region8 v51
-;; @001f                               v53 = uextend.i64 v52
-;; @001f                               v59 = icmp.i64 ugt v4, v53
-;; @001f                               trapnz v59, user17
-;; @001f                               v76 = load.i64 notrap aligned region9 v135+40
-;; @001f                               v64 = iconst.i64 24
-;; @001f                               v65 = iadd v49, v64  ; v64 = 24
-;; @001f                               v78 = uadd_overflow_trap v65, v91, user2
-;; @001f                               v77 = iadd v136, v76
-;; @001f                               v79 = icmp ugt v78, v77
-;; @001f                               trapnz v79, user2
-;; @001f                               v45 = iconst.i32 0
-;; @001f                               call fn1(v0, v65, v45, v91), stack_map=[i32 @ ss0+0]  ; v45 = 0
+;; @001f                               v47 = uextend.i64 v41
+;; @001f                               v50 = iadd v136, v47
+;; @001f                               v52 = iadd v50, v43  ; v43 = 16
+;; @001f                               v53 = load.i32 user2 readonly region8 v52
+;; @001f                               v54 = uextend.i64 v53
+;; @001f                               v60 = icmp.i64 ugt v4, v54
+;; @001f                               trapnz v60, user17
+;; @001f                               v77 = load.i64 notrap aligned region9 v135+40
+;; @001f                               v65 = iconst.i64 24
+;; @001f                               v66 = iadd v50, v65  ; v65 = 24
+;; @001f                               v79 = uadd_overflow_trap v66, v92, user2
+;; @001f                               v78 = iadd v136, v77
+;; @001f                               v80 = icmp ugt v79, v78
+;; @001f                               trapnz v80, user2
+;; @001f                               v46 = iconst.i32 0
+;; @001f                               call fn1(v0, v66, v46, v92), stack_map=[i32 @ ss0+0]  ; v46 = 0
 ;; @0022                               jump block1
 ;;
 ;;                                 block1:
-;;                                     v82 = load.i32 notrap aligned region10 v89
-;; @0022                               return v82
+;;                                     v83 = load.i32 notrap aligned region10 v90
+;; @0022                               return v83
 ;; }
diff --git a/tests/disas/gc/array-new-default-funcref.wat b/tests/disas/gc/array-new-default-funcref.wat
index b5e2f4aea84f..67b8cbf2793a 100644
--- a/tests/disas/gc/array-new-default-funcref.wat
+++ b/tests/disas/gc/array-new-default-funcref.wat
@@ -33,15 +33,15 @@
 ;;
 ;;                                 block0(v0: i64, v1: i64, v2: i32):
 ;; @001f                               v4 = uextend.i64 v2
-;;                                     v98 = iconst.i64 2
-;;                                     v99 = ishl v4, v98  ; v98 = 2
+;;                                     v99 = iconst.i64 2
+;;                                     v100 = ishl v4, v99  ; v99 = 2
 ;; @001f                               v7 = iconst.i64 32
-;; @001f                               v8 = ushr v99, v7  ; v7 = 32
+;; @001f                               v8 = ushr v100, v7  ; v7 = 32
 ;; @001f                               trapnz v8, user18
 ;; @001f                               v3 = iconst.i32 20
-;;                                     v105 = iconst.i32 2
-;;                                     v106 = ishl v2, v105  ; v105 = 2
-;; @001f                               v10 = uadd_overflow_trap v3, v106, user18  ; v3 = 20
+;;                                     v106 = iconst.i32 2
+;;                                     v107 = ishl v2, v106  ; v106 = 2
+;; @001f                               v10 = uadd_overflow_trap v3, v107, user18  ; v3 = 20
 ;; @001f                               v11 = load.i64 notrap aligned readonly can_move region2 v0+32
 ;; @001f                               v12 = load.i32 notrap aligned region3 v11
 ;; @001f                               v13 = load.i32 notrap aligned region4 v11+4
@@ -57,22 +57,21 @@
 ;; @001f                               brif v22, block2, block3
 ;;
 ;;                                 block2:
-;;                                     v114 = iconst.i32 15
-;;                                     v115 = iadd.i32 v10, v114  ; v114 = 15
-;;                                     v118 = iconst.i32 -16
-;;                                     v119 = band v115, v118  ; v118 = -16
-;;                                     v121 = iadd.i32 v12, v119
-;; @001f                               store notrap aligned region3 v121, v11
-;;                                     v136 = iconst.i32 -1476395002
-;;                                     v137 = load.i64 notrap aligned readonly can_move region0 v0+8
-;;                                     v138 = load.i64 notrap aligned readonly can_move region7 v137+32
-;; @001f                               v36 = iadd v138, v19
-;; @001f                               store user2 region8 v136, v36  ; v136 = -1476395002
-;;                                     v139 = load.i64 notrap aligned readonly can_move region5 v0+40
-;;                                     v140 = load.i32 notrap aligned readonly can_move region6 v139
-;; @001f                               store user2 region8 v140, v36+4
-;;                                     v141 = band.i64 v17, v16  ; v16 = -16
-;; @001f                               istore32 user2 region8 v141, v36+8
+;;                                     v115 = iconst.i32 15
+;;                                     v116 = iadd.i32 v10, v115  ; v115 = 15
+;;                                     v119 = iconst.i32 -16
+;;                                     v120 = band v116, v119  ; v119 = -16
+;;                                     v122 = iadd.i32 v12, v120
+;; @001f                               store notrap aligned region3 v122, v11
+;;                                     v137 = iconst.i32 -1476395002
+;;                                     v138 = load.i64 notrap aligned readonly can_move region0 v0+8
+;;                                     v139 = load.i64 notrap aligned readonly can_move region7 v138+32
+;; @001f                               v36 = iadd v139, v19
+;; @001f                               store user2 region8 v137, v36  ; v137 = -1476395002
+;;                                     v140 = load.i64 notrap aligned readonly can_move region5 v0+40
+;;                                     v141 = load.i32 notrap aligned readonly can_move region6 v140
+;; @001f                               store user2 region8 v141, v36+4
+;; @001f                               store user2 region8 v120, v36+8
 ;; @001f                               jump block4(v12, v36)
 ;;
 ;;                                 block3 cold:
@@ -87,48 +86,48 @@
 ;; @001f                               v31 = iadd v29, v30
 ;; @001f                               jump block4(v27, v31)
 ;;
-;;                                 block4(v40: i32, v41: i64):
-;;                                     v97 = stack_addr.i64 ss0
-;;                                     store notrap aligned region10 v40, v97
-;; @001f                               v42 = iconst.i64 16
-;; @001f                               v43 = iadd v41, v42  ; v42 = 16
-;; @001f                               store.i32 user2 region8 v2, v43
-;; @001f                               trapz v40, user16
+;;                                 block4(v41: i32, v42: i64):
+;;                                     v98 = stack_addr.i64 ss0
+;;                                     store notrap aligned region10 v41, v98
+;; @001f                               v43 = iconst.i64 16
+;; @001f                               v44 = iadd v42, v43  ; v43 = 16
+;; @001f                               store.i32 user2 region8 v2, v44
+;; @001f                               trapz v41, user16
 ;;                                     v142 = load.i64 notrap aligned readonly can_move region0 v0+8
 ;;                                     v143 = load.i64 notrap aligned readonly can_move region7 v142+32
-;; @001f                               v46 = uextend.i64 v40
-;; @001f                               v49 = iadd v143, v46
-;; @001f                               v51 = iadd v49, v42  ; v42 = 16
-;; @001f                               v52 = load.i32 user2 readonly region8 v51
-;; @001f                               v53 = uextend.i64 v52
-;; @001f                               v59 = icmp.i64 ugt v4, v53
-;; @001f                               trapnz v59, user17
-;; @001f                               v76 = load.i64 notrap aligned region9 v142+40
-;; @001f                               v64 = iconst.i64 20
-;; @001f                               v65 = iadd v49, v64  ; v64 = 20
-;; @001f                               v78 = uadd_overflow_trap v65, v99, user2
-;; @001f                               v77 = iadd v143, v76
-;; @001f                               v79 = icmp ugt v78, v77
-;; @001f                               trapnz v79, user2
-;; @001f                               v44 = iconst.i64 0
-;; @001f                               v80 = call fn1(v0, v44), stack_map=[i32 @ ss0+0]  ; v44 = 0
-;; @001f                               v84 = icmp.i64 eq v4, v44  ; v44 = 0
-;; @001f                               v81 = ireduce.i32 v80
+;; @001f                               v47 = uextend.i64 v41
+;; @001f                               v50 = iadd v143, v47
+;; @001f                               v52 = iadd v50, v43  ; v43 = 16
+;; @001f                               v53 = load.i32 user2 readonly region8 v52
+;; @001f                               v54 = uextend.i64 v53
+;; @001f                               v60 = icmp.i64 ugt v4, v54
+;; @001f                               trapnz v60, user17
+;; @001f                               v77 = load.i64 notrap aligned region9 v142+40
+;; @001f                               v65 = iconst.i64 20
+;; @001f                               v66 = iadd v50, v65  ; v65 = 20
+;; @001f                               v79 = uadd_overflow_trap v66, v100, user2
+;; @001f                               v78 = iadd v143, v77
+;; @001f                               v80 = icmp ugt v79, v78
+;; @001f                               trapnz v80, user2
+;; @001f                               v45 = iconst.i64 0
+;; @001f                               v81 = call fn1(v0, v45), stack_map=[i32 @ ss0+0]  ; v45 = 0
+;; @001f                               v85 = icmp.i64 eq v4, v45  ; v45 = 0
+;; @001f                               v82 = ireduce.i32 v81
 ;; @001f                               v5 = iconst.i64 4
-;; @001f                               v82 = iadd v65, v99
-;; @001f                               brif v84, block6, block5(v65)
+;; @001f                               v83 = iadd v66, v100
+;; @001f                               brif v85, block6, block5(v66)
 ;;
-;;                                 block5(v85: i64):
-;; @001f                               store.i32 notrap aligned little region8 v81, v85
+;;                                 block5(v86: i64):
+;; @001f                               store.i32 notrap aligned little region8 v82, v86
 ;;                                     v144 = iconst.i64 4
-;;                                     v145 = iadd v85, v144  ; v144 = 4
-;; @001f                               v88 = icmp eq v145, v82
-;; @001f                               brif v88, block6, block5(v145)
+;;                                     v145 = iadd v86, v144  ; v144 = 4
+;; @001f                               v89 = icmp eq v145, v83
+;; @001f                               brif v89, block6, block5(v145)
 ;;
 ;;                                 block6:
 ;; @0022                               jump block1
 ;;
 ;;                                 block1:
-;;                                     v90 = load.i32 notrap aligned region10 v97
-;; @0022                               return v90
+;;                                     v91 = load.i32 notrap aligned region10 v98
+;; @0022                               return v91
 ;; }
diff --git a/tests/disas/gc/array-new-default-i16.wat b/tests/disas/gc/array-new-default-i16.wat
index a966b5d624e6..b0a00386e0d9 100644
--- a/tests/disas/gc/array-new-default-i16.wat
+++ b/tests/disas/gc/array-new-default-i16.wat
@@ -33,14 +33,14 @@
 ;;
 ;;                                 block0(v0: i64, v1: i64, v2: i32):
 ;; @001f                               v4 = uextend.i64 v2
-;;                                     v91 = iconst.i64 1
-;;                                     v92 = ishl v4, v91  ; v91 = 1
+;;                                     v92 = iconst.i64 1
+;;                                     v93 = ishl v4, v92  ; v92 = 1
 ;; @001f                               v7 = iconst.i64 32
-;; @001f                               v8 = ushr v92, v7  ; v7 = 32
+;; @001f                               v8 = ushr v93, v7  ; v7 = 32
 ;; @001f                               trapnz v8, user18
 ;; @001f                               v3 = iconst.i32 20
-;;                                     v96 = iadd v2, v2
-;; @001f                               v10 = uadd_overflow_trap v3, v96, user18  ; v3 = 20
+;;                                     v97 = iadd v2, v2
+;; @001f                               v10 = uadd_overflow_trap v3, v97, user18  ; v3 = 20
 ;; @001f                               v11 = load.i64 notrap aligned readonly can_move region2 v0+32
 ;; @001f                               v12 = load.i32 notrap aligned region3 v11
 ;; @001f                               v13 = load.i32 notrap aligned region4 v11+4
@@ -56,22 +56,21 @@
 ;; @001f                               brif v22, block2, block3
 ;;
 ;;                                 block2:
-;;                                     v111 = iconst.i32 15
-;;                                     v112 = iadd.i32 v10, v111  ; v111 = 15
-;;                                     v115 = iconst.i32 -16
-;;                                     v116 = band v112, v115  ; v115 = -16
-;;                                     v118 = iadd.i32 v12, v116
-;; @001f                               store notrap aligned region3 v118, v11
-;;                                     v139 = iconst.i32 -1476395002
-;;                                     v140 = load.i64 notrap aligned readonly can_move region0 v0+8
-;;                                     v141 = load.i64 notrap aligned readonly can_move region7 v140+32
-;; @001f                               v36 = iadd v141, v19
-;; @001f                               store user2 region8 v139, v36  ; v139 = -1476395002
-;;                                     v142 = load.i64 notrap aligned readonly can_move region5 v0+40
-;;                                     v143 = load.i32 notrap aligned readonly can_move region6 v142
-;; @001f                               store user2 region8 v143, v36+4
-;;                                     v144 = band.i64 v17, v16  ; v16 = -16
-;; @001f                               istore32 user2 region8 v144, v36+8
+;;                                     v112 = iconst.i32 15
+;;                                     v113 = iadd.i32 v10, v112  ; v112 = 15
+;;                                     v116 = iconst.i32 -16
+;;                                     v117 = band v113, v116  ; v116 = -16
+;;                                     v119 = iadd.i32 v12, v117
+;; @001f                               store notrap aligned region3 v119, v11
+;;                                     v140 = iconst.i32 -1476395002
+;;                                     v141 = load.i64 notrap aligned readonly can_move region0 v0+8
+;;                                     v142 = load.i64 notrap aligned readonly can_move region7 v141+32
+;; @001f                               v36 = iadd v142, v19
+;; @001f                               store user2 region8 v140, v36  ; v140 = -1476395002
+;;                                     v143 = load.i64 notrap aligned readonly can_move region5 v0+40
+;;                                     v144 = load.i32 notrap aligned readonly can_move region6 v143
+;; @001f                               store user2 region8 v144, v36+4
+;; @001f                               store user2 region8 v117, v36+8
 ;; @001f                               jump block4(v12, v36)
 ;;
 ;;                                 block3 cold:
@@ -86,34 +85,34 @@
 ;; @001f                               v31 = iadd v29, v30
 ;; @001f                               jump block4(v27, v31)
 ;;
-;;                                 block4(v40: i32, v41: i64):
-;;                                     v89 = stack_addr.i64 ss0
-;;                                     store notrap aligned region10 v40, v89
-;; @001f                               v42 = iconst.i64 16
-;; @001f                               v43 = iadd v41, v42  ; v42 = 16
-;; @001f                               store.i32 user2 region8 v2, v43
-;; @001f                               trapz v40, user16
+;;                                 block4(v41: i32, v42: i64):
+;;                                     v90 = stack_addr.i64 ss0
+;;                                     store notrap aligned region10 v41, v90
+;; @001f                               v43 = iconst.i64 16
+;; @001f                               v44 = iadd v42, v43  ; v43 = 16
+;; @001f                               store.i32 user2 region8 v2, v44
+;; @001f                               trapz v41, user16
 ;;                                     v145 = load.i64 notrap aligned readonly can_move region0 v0+8
 ;;                                     v146 = load.i64 notrap aligned readonly can_move region7 v145+32
-;; @001f                               v46 = uextend.i64 v40
-;; @001f                               v49 = iadd v146, v46
-;; @001f                               v51 = iadd v49, v42  ; v42 = 16
-;; @001f                               v52 = load.i32 user2 readonly region8 v51
-;; @001f                               v53 = uextend.i64 v52
-;; @001f                               v59 = icmp.i64 ugt v4, v53
-;; @001f                               trapnz v59, user17
-;; @001f                               v76 = load.i64 notrap aligned region9 v145+40
-;; @001f                               v64 = iconst.i64 20
-;; @001f                               v65 = iadd v49, v64  ; v64 = 20
-;; @001f                               v78 = uadd_overflow_trap v65, v92, user2
-;; @001f                               v77 = iadd v146, v76
-;; @001f                               v79 = icmp ugt v78, v77
-;; @001f                               trapnz v79, user2
-;; @001f                               v44 = iconst.i32 0
-;; @001f                               call fn1(v0, v65, v44, v92), stack_map=[i32 @ ss0+0]  ; v44 = 0
+;; @001f                               v47 = uextend.i64 v41
+;; @001f                               v50 = iadd v146, v47
+;; @001f                               v52 = iadd v50, v43  ; v43 = 16
+;; @001f                               v53 = load.i32 user2 readonly region8 v52
+;; @001f                               v54 = uextend.i64 v53
+;; @001f                               v60 = icmp.i64 ugt v4, v54
+;; @001f                               trapnz v60, user17
+;; @001f                               v77 = load.i64 notrap aligned region9 v145+40
+;; @001f                               v65 = iconst.i64 20
+;; @001f                               v66 = iadd v50, v65  ; v65 = 20
+;; @001f                               v79 = uadd_overflow_trap v66, v93, user2
+;; @001f                               v78 = iadd v146, v77
+;; @001f                               v80 = icmp ugt v79, v78
+;; @001f                               trapnz v80, user2
+;; @001f                               v45 = iconst.i32 0
+;; @001f                               call fn1(v0, v66, v45, v93), stack_map=[i32 @ ss0+0]  ; v45 = 0
 ;; @0022                               jump block1
 ;;
 ;;                                 block1:
-;;                                     v82 = load.i32 notrap aligned region10 v89
-;; @0022                               return v82
+;;                                     v83 = load.i32 notrap aligned region10 v90
+;; @0022                               return v83
 ;; }
diff --git a/tests/disas/gc/array-new-default-i32.wat b/tests/disas/gc/array-new-default-i32.wat
index 25ecce075555..4cb63202b64d 100644
--- a/tests/disas/gc/array-new-default-i32.wat
+++ b/tests/disas/gc/array-new-default-i32.wat
@@ -33,15 +33,15 @@
 ;;
 ;;                                 block0(v0: i64, v1: i64, v2: i32):
 ;; @001f                               v4 = uextend.i64 v2
-;;                                     v90 = iconst.i64 2
-;;                                     v91 = ishl v4, v90  ; v90 = 2
+;;                                     v91 = iconst.i64 2
+;;                                     v92 = ishl v4, v91  ; v91 = 2
 ;; @001f                               v7 = iconst.i64 32
-;; @001f                               v8 = ushr v91, v7  ; v7 = 32
+;; @001f                               v8 = ushr v92, v7  ; v7 = 32
 ;; @001f                               trapnz v8, user18
 ;; @001f                               v3 = iconst.i32 20
-;;                                     v97 = iconst.i32 2
-;;                                     v98 = ishl v2, v97  ; v97 = 2
-;; @001f                               v10 = uadd_overflow_trap v3, v98, user18  ; v3 = 20
+;;                                     v98 = iconst.i32 2
+;;                                     v99 = ishl v2, v98  ; v98 = 2
+;; @001f                               v10 = uadd_overflow_trap v3, v99, user18  ; v3 = 20
 ;; @001f                               v11 = load.i64 notrap aligned readonly can_move region2 v0+32
 ;; @001f                               v12 = load.i32 notrap aligned region3 v11
 ;; @001f                               v13 = load.i32 notrap aligned region4 v11+4
@@ -57,22 +57,21 @@
 ;; @001f                               brif v22, block2, block3
 ;;
 ;;                                 block2:
-;;                                     v106 = iconst.i32 15
-;;                                     v107 = iadd.i32 v10, v106  ; v106 = 15
-;;                                     v110 = iconst.i32 -16
-;;                                     v111 = band v107, v110  ; v110 = -16
-;;                                     v113 = iadd.i32 v12, v111
-;; @001f                               store notrap aligned region3 v113, v11
-;;                                     v129 = iconst.i32 -1476395002
-;;                                     v130 = load.i64 notrap aligned readonly can_move region0 v0+8
-;;                                     v131 = load.i64 notrap aligned readonly can_move region7 v130+32
-;; @001f                               v36 = iadd v131, v19
-;; @001f                               store user2 region8 v129, v36  ; v129 = -1476395002
-;;                                     v132 = load.i64 notrap aligned readonly can_move region5 v0+40
-;;                                     v133 = load.i32 notrap aligned readonly can_move region6 v132
-;; @001f                               store user2 region8 v133, v36+4
-;;                                     v134 = band.i64 v17, v16  ; v16 = -16
-;; @001f                               istore32 user2 region8 v134, v36+8
+;;                                     v107 = iconst.i32 15
+;;                                     v108 = iadd.i32 v10, v107  ; v107 = 15
+;;                                     v111 = iconst.i32 -16
+;;                                     v112 = band v108, v111  ; v111 = -16
+;;                                     v114 = iadd.i32 v12, v112
+;; @001f                               store notrap aligned region3 v114, v11
+;;                                     v130 = iconst.i32 -1476395002
+;;                                     v131 = load.i64 notrap aligned readonly can_move region0 v0+8
+;;                                     v132 = load.i64 notrap aligned readonly can_move region7 v131+32
+;; @001f                               v36 = iadd v132, v19
+;; @001f                               store user2 region8 v130, v36  ; v130 = -1476395002
+;;                                     v133 = load.i64 notrap aligned readonly can_move region5 v0+40
+;;                                     v134 = load.i32 notrap aligned readonly can_move region6 v133
+;; @001f                               store user2 region8 v134, v36+4
+;; @001f                               store user2 region8 v112, v36+8
 ;; @001f                               jump block4(v12, v36)
 ;;
 ;;                                 block3 cold:
@@ -87,34 +86,34 @@
 ;; @001f                               v31 = iadd v29, v30
 ;; @001f                               jump block4(v27, v31)
 ;;
-;;                                 block4(v40: i32, v41: i64):
-;;                                     v89 = stack_addr.i64 ss0
-;;                                     store notrap aligned region10 v40, v89
-;; @001f                               v42 = iconst.i64 16
-;; @001f                               v43 = iadd v41, v42  ; v42 = 16
-;; @001f                               store.i32 user2 region8 v2, v43
-;; @001f                               trapz v40, user16
+;;                                 block4(v41: i32, v42: i64):
+;;                                     v90 = stack_addr.i64 ss0
+;;                                     store notrap aligned region10 v41, v90
+;; @001f                               v43 = iconst.i64 16
+;; @001f                               v44 = iadd v42, v43  ; v43 = 16
+;; @001f                               store.i32 user2 region8 v2, v44
+;; @001f                               trapz v41, user16
 ;;                                     v135 = load.i64 notrap aligned readonly can_move region0 v0+8
 ;;                                     v136 = load.i64 notrap aligned readonly can_move region7 v135+32
-;; @001f                               v46 = uextend.i64 v40
-;; @001f                               v49 = iadd v136, v46
-;; @001f                               v51 = iadd v49, v42  ; v42 = 16
-;; @001f                               v52 = load.i32 user2 readonly region8 v51
-;; @001f                               v53 = uextend.i64 v52
-;; @001f                               v59 = icmp.i64 ugt v4, v53
-;; @001f                               trapnz v59, user17
-;; @001f                               v76 = load.i64 notrap aligned region9 v135+40
-;; @001f                               v64 = iconst.i64 20
-;; @001f                               v65 = iadd v49, v64  ; v64 = 20
-;; @001f                               v78 = uadd_overflow_trap v65, v91, user2
-;; @001f                               v77 = iadd v136, v76
-;; @001f                               v79 = icmp ugt v78, v77
-;; @001f                               trapnz v79, user2
-;; @001f                               v44 = iconst.i32 0
-;; @001f                               call fn1(v0, v65, v44, v91), stack_map=[i32 @ ss0+0]  ; v44 = 0
+;; @001f                               v47 = uextend.i64 v41
+;; @001f                               v50 = iadd v136, v47
+;; @001f                               v52 = iadd v50, v43  ; v43 = 16
+;; @001f                               v53 = load.i32 user2 readonly region8 v52
+;; @001f                               v54 = uextend.i64 v53
+;; @001f                               v60 = icmp.i64 ugt v4, v54
+;; @001f                               trapnz v60, user17
+;; @001f                               v77 = load.i64 notrap aligned region9 v135+40
+;; @001f                               v65 = iconst.i64 20
+;; @001f                               v66 = iadd v50, v65  ; v65 = 20
+;; @001f                               v79 = uadd_overflow_trap v66, v92, user2
+;; @001f                               v78 = iadd v136, v77
+;; @001f                               v80 = icmp ugt v79, v78
+;; @001f                               trapnz v80, user2
+;; @001f                               v45 = iconst.i32 0
+;; @001f                               call fn1(v0, v66, v45, v92), stack_map=[i32 @ ss0+0]  ; v45 = 0
 ;; @0022                               jump block1
 ;;
 ;;                                 block1:
-;;                                     v82 = load.i32 notrap aligned region10 v89
-;; @0022                               return v82
+;;                                     v83 = load.i32 notrap aligned region10 v90
+;; @0022                               return v83
 ;; }
diff --git a/tests/disas/gc/array-new-default-i64.wat b/tests/disas/gc/array-new-default-i64.wat
index 65b9b9114187..f60ad7e45daa 100644
--- a/tests/disas/gc/array-new-default-i64.wat
+++ b/tests/disas/gc/array-new-default-i64.wat
@@ -33,15 +33,15 @@
 ;;
 ;;                                 block0(v0: i64, v1: i64, v2: i32):
 ;; @001f                               v4 = uextend.i64 v2
-;;                                     v90 = iconst.i64 3
-;;                                     v91 = ishl v4, v90  ; v90 = 3
+;;                                     v91 = iconst.i64 3
+;;                                     v92 = ishl v4, v91  ; v91 = 3
 ;; @001f                               v7 = iconst.i64 32
-;; @001f                               v8 = ushr v91, v7  ; v7 = 32
+;; @001f                               v8 = ushr v92, v7  ; v7 = 32
 ;; @001f                               trapnz v8, user18
 ;; @001f                               v3 = iconst.i32 24
-;;                                     v97 = iconst.i32 3
-;;                                     v98 = ishl v2, v97  ; v97 = 3
-;; @001f                               v10 = uadd_overflow_trap v3, v98, user18  ; v3 = 24
+;;                                     v98 = iconst.i32 3
+;;                                     v99 = ishl v2, v98  ; v98 = 3
+;; @001f                               v10 = uadd_overflow_trap v3, v99, user18  ; v3 = 24
 ;; @001f                               v11 = load.i64 notrap aligned readonly can_move region2 v0+32
 ;; @001f                               v12 = load.i32 notrap aligned region3 v11
 ;; @001f                               v13 = load.i32 notrap aligned region4 v11+4
@@ -57,22 +57,21 @@
 ;; @001f                               brif v22, block2, block3
 ;;
 ;;                                 block2:
-;;                                     v106 = iconst.i32 15
-;;                                     v107 = iadd.i32 v10, v106  ; v106 = 15
-;;                                     v110 = iconst.i32 -16
-;;                                     v111 = band v107, v110  ; v110 = -16
-;;                                     v113 = iadd.i32 v12, v111
-;; @001f                               store notrap aligned region3 v113, v11
-;;                                     v128 = iconst.i32 -1476395002
-;;                                     v129 = load.i64 notrap aligned readonly can_move region0 v0+8
-;;                                     v130 = load.i64 notrap aligned readonly can_move region7 v129+32
-;; @001f                               v36 = iadd v130, v19
-;; @001f                               store user2 region8 v128, v36  ; v128 = -1476395002
-;;                                     v131 = load.i64 notrap aligned readonly can_move region5 v0+40
-;;                                     v132 = load.i32 notrap aligned readonly can_move region6 v131
-;; @001f                               store user2 region8 v132, v36+4
-;;                                     v133 = band.i64 v17, v16  ; v16 = -16
-;; @001f                               istore32 user2 region8 v133, v36+8
+;;                                     v107 = iconst.i32 15
+;;                                     v108 = iadd.i32 v10, v107  ; v107 = 15
+;;                                     v111 = iconst.i32 -16
+;;                                     v112 = band v108, v111  ; v111 = -16
+;;                                     v114 = iadd.i32 v12, v112
+;; @001f                               store notrap aligned region3 v114, v11
+;;                                     v129 = iconst.i32 -1476395002
+;;                                     v130 = load.i64 notrap aligned readonly can_move region0 v0+8
+;;                                     v131 = load.i64 notrap aligned readonly can_move region7 v130+32
+;; @001f                               v36 = iadd v131, v19
+;; @001f                               store user2 region8 v129, v36  ; v129 = -1476395002
+;;                                     v132 = load.i64 notrap aligned readonly can_move region5 v0+40
+;;                                     v133 = load.i32 notrap aligned readonly can_move region6 v132
+;; @001f                               store user2 region8 v133, v36+4
+;; @001f                               store user2 region8 v112, v36+8
 ;; @001f                               jump block4(v12, v36)
 ;;
 ;;                                 block3 cold:
@@ -87,34 +86,34 @@
 ;; @001f                               v31 = iadd v29, v30
 ;; @001f                               jump block4(v27, v31)
 ;;
-;;                                 block4(v40: i32, v41: i64):
-;;                                     v89 = stack_addr.i64 ss0
-;;                                     store notrap aligned region10 v40, v89
-;; @001f                               v42 = iconst.i64 16
-;; @001f                               v43 = iadd v41, v42  ; v42 = 16
-;; @001f                               store.i32 user2 region8 v2, v43
-;; @001f                               trapz v40, user16
+;;                                 block4(v41: i32, v42: i64):
+;;                                     v90 = stack_addr.i64 ss0
+;;                                     store notrap aligned region10 v41, v90
+;; @001f                               v43 = iconst.i64 16
+;; @001f                               v44 = iadd v42, v43  ; v43 = 16
+;; @001f                               store.i32 user2 region8 v2, v44
+;; @001f                               trapz v41, user16
 ;;                                     v134 = load.i64 notrap aligned readonly can_move region0 v0+8
 ;;                                     v135 = load.i64 notrap aligned readonly can_move region7 v134+32
-;; @001f                               v46 = uextend.i64 v40
-;; @001f                               v49 = iadd v135, v46
-;; @001f                               v51 = iadd v49, v42  ; v42 = 16
-;; @001f                               v52 = load.i32 user2 readonly region8 v51
-;; @001f                               v53 = uextend.i64 v52
-;; @001f                               v59 = icmp.i64 ugt v4, v53
-;; @001f                               trapnz v59, user17
-;; @001f                               v76 = load.i64 notrap aligned region9 v134+40
-;; @001f                               v64 = iconst.i64 24
-;; @001f                               v65 = iadd v49, v64  ; v64 = 24
-;; @001f                               v78 = uadd_overflow_trap v65, v91, user2
-;; @001f                               v77 = iadd v135, v76
-;; @001f                               v79 = icmp ugt v78, v77
-;; @001f                               trapnz v79, user2
-;; @001f                               v45 = iconst.i32 0
-;; @001f                               call fn1(v0, v65, v45, v91), stack_map=[i32 @ ss0+0]  ; v45 = 0
+;; @001f                               v47 = uextend.i64 v41
+;; @001f                               v50 = iadd v135, v47
+;; @001f                               v52 = iadd v50, v43  ; v43 = 16
+;; @001f                               v53 = load.i32 user2 readonly region8 v52
+;; @001f                               v54 = uextend.i64 v53
+;; @001f                               v60 = icmp.i64 ugt v4, v54
+;; @001f                               trapnz v60, user17
+;; @001f                               v77 = load.i64 notrap aligned region9 v134+40
+;; @001f                               v65 = iconst.i64 24
+;; @001f                               v66 = iadd v50, v65  ; v65 = 24
+;; @001f                               v79 = uadd_overflow_trap v66, v92, user2
+;; @001f                               v78 = iadd v135, v77
+;; @001f                               v80 = icmp ugt v79, v78
+;; @001f                               trapnz v80, user2
+;; @001f                               v46 = iconst.i32 0
+;; @001f                               call fn1(v0, v66, v46, v92), stack_map=[i32 @ ss0+0]  ; v46 = 0
 ;; @0022                               jump block1
 ;;
 ;;                                 block1:
-;;                                     v82 = load.i32 notrap aligned region10 v89
-;; @0022                               return v82
+;;                                     v83 = load.i32 notrap aligned region10 v90
+;; @0022                               return v83
 ;; }
diff --git a/tests/disas/gc/array-new-default-i8.wat b/tests/disas/gc/array-new-default-i8.wat
index 45f840d560d0..2ee385e542cf 100644
--- a/tests/disas/gc/array-new-default-i8.wat
+++ b/tests/disas/gc/array-new-default-i8.wat
@@ -53,22 +53,21 @@
 ;; @001f                               brif v22, block2, block3
 ;;
 ;;                                 block2:
-;;                                     v96 = iconst.i32 15
-;;                                     v97 = iadd.i32 v10, v96  ; v96 = 15
-;;                                     v100 = iconst.i32 -16
-;;                                     v101 = band v97, v100  ; v100 = -16
-;;                                     v103 = iadd.i32 v12, v101
-;; @001f                               store notrap aligned region3 v103, v11
-;;                                     v117 = iconst.i32 -1476395002
-;;                                     v118 = load.i64 notrap aligned readonly can_move region0 v0+8
-;;                                     v119 = load.i64 notrap aligned readonly can_move region7 v118+32
-;; @001f                               v36 = iadd v119, v19
-;; @001f                               store user2 region8 v117, v36  ; v117 = -1476395002
-;;                                     v120 = load.i64 notrap aligned readonly can_move region5 v0+40
-;;                                     v121 = load.i32 notrap aligned readonly can_move region6 v120
-;; @001f                               store user2 region8 v121, v36+4
-;;                                     v122 = band.i64 v17, v16  ; v16 = -16
-;; @001f                               istore32 user2 region8 v122, v36+8
+;;                                     v97 = iconst.i32 15
+;;                                     v98 = iadd.i32 v10, v97  ; v97 = 15
+;;                                     v101 = iconst.i32 -16
+;;                                     v102 = band v98, v101  ; v101 = -16
+;;                                     v104 = iadd.i32 v12, v102
+;; @001f                               store notrap aligned region3 v104, v11
+;;                                     v118 = iconst.i32 -1476395002
+;;                                     v119 = load.i64 notrap aligned readonly can_move region0 v0+8
+;;                                     v120 = load.i64 notrap aligned readonly can_move region7 v119+32
+;; @001f                               v36 = iadd v120, v19
+;; @001f                               store user2 region8 v118, v36  ; v118 = -1476395002
+;;                                     v121 = load.i64 notrap aligned readonly can_move region5 v0+40
+;;                                     v122 = load.i32 notrap aligned readonly can_move region6 v121
+;; @001f                               store user2 region8 v122, v36+4
+;; @001f                               store user2 region8 v102, v36+8
 ;; @001f                               jump block4(v12, v36)
 ;;
 ;;                                 block3 cold:
@@ -83,34 +82,34 @@
 ;; @001f                               v31 = iadd v29, v30
 ;; @001f                               jump block4(v27, v31)
 ;;
-;;                                 block4(v40: i32, v41: i64):
-;;                                     v88 = stack_addr.i64 ss0
-;;                                     store notrap aligned region10 v40, v88
-;; @001f                               v42 = iconst.i64 16
-;; @001f                               v43 = iadd v41, v42  ; v42 = 16
-;; @001f                               store.i32 user2 region8 v2, v43
-;; @001f                               trapz v40, user16
+;;                                 block4(v41: i32, v42: i64):
+;;                                     v89 = stack_addr.i64 ss0
+;;                                     store notrap aligned region10 v41, v89
+;; @001f                               v43 = iconst.i64 16
+;; @001f                               v44 = iadd v42, v43  ; v43 = 16
+;; @001f                               store.i32 user2 region8 v2, v44
+;; @001f                               trapz v41, user16
 ;;                                     v123 = load.i64 notrap aligned readonly can_move region0 v0+8
 ;;                                     v124 = load.i64 notrap aligned readonly can_move region7 v123+32
-;; @001f                               v46 = uextend.i64 v40
-;; @001f                               v49 = iadd v124, v46
-;; @001f                               v51 = iadd v49, v42  ; v42 = 16
-;; @001f                               v52 = load.i32 user2 readonly region8 v51
-;; @001f                               v53 = uextend.i64 v52
-;; @001f                               v59 = icmp.i64 ugt v4, v53
-;; @001f                               trapnz v59, user17
-;; @001f                               v76 = load.i64 notrap aligned region9 v123+40
-;; @001f                               v64 = iconst.i64 20
-;; @001f                               v65 = iadd v49, v64  ; v64 = 20
-;; @001f                               v78 = uadd_overflow_trap v65, v4, user2
-;; @001f                               v77 = iadd v124, v76
-;; @001f                               v79 = icmp ugt v78, v77
-;; @001f                               trapnz v79, user2
-;; @001f                               v44 = iconst.i32 0
-;; @001f                               call fn1(v0, v65, v44, v4), stack_map=[i32 @ ss0+0]  ; v44 = 0
+;; @001f                               v47 = uextend.i64 v41
+;; @001f                               v50 = iadd v124, v47
+;; @001f                               v52 = iadd v50, v43  ; v43 = 16
+;; @001f                               v53 = load.i32 user2 readonly region8 v52
+;; @001f                               v54 = uextend.i64 v53
+;; @001f                               v60 = icmp.i64 ugt v4, v54
+;; @001f                               trapnz v60, user17
+;; @001f                               v77 = load.i64 notrap aligned region9 v123+40
+;; @001f                               v65 = iconst.i64 20
+;; @001f                               v66 = iadd v50, v65  ; v65 = 20
+;; @001f                               v79 = uadd_overflow_trap v66, v4, user2
+;; @001f                               v78 = iadd v124, v77
+;; @001f                               v80 = icmp ugt v79, v78
+;; @001f                               trapnz v80, user2
+;; @001f                               v45 = iconst.i32 0
+;; @001f                               call fn1(v0, v66, v45, v4), stack_map=[i32 @ ss0+0]  ; v45 = 0
 ;; @0022                               jump block1
 ;;
 ;;                                 block1:
-;;                                     v81 = load.i32 notrap aligned region10 v88
-;; @0022                               return v81
+;;                                     v82 = load.i32 notrap aligned region10 v89
+;; @0022                               return v82
 ;; }
diff --git a/tests/disas/gc/copying/array-new-fixed-of-gc-refs.wat b/tests/disas/gc/copying/array-new-fixed-of-gc-refs.wat
index c5f20774d01e..cc946bdaff56 100644
--- a/tests/disas/gc/copying/array-new-fixed-of-gc-refs.wat
+++ b/tests/disas/gc/copying/array-new-fixed-of-gc-refs.wat
@@ -33,12 +33,12 @@
 ;;     stack_limit = gv2
 ;;
 ;;                                 block0(v0: i64, v1: i64, v2: i32, v3: i32, v4: i32):
-;;                                     v137 = stack_addr.i64 ss2
-;;                                     store notrap aligned region12 v2, v137
-;;                                     v138 = stack_addr.i64 ss1
-;;                                     store notrap aligned region11 v3, v138
-;;                                     v139 = stack_addr.i64 ss0
-;;                                     store notrap aligned region10 v4, v139
+;;                                     v138 = stack_addr.i64 ss2
+;;                                     store notrap aligned region12 v2, v138
+;;                                     v139 = stack_addr.i64 ss1
+;;                                     store notrap aligned region11 v3, v139
+;;                                     v140 = stack_addr.i64 ss0
+;;                                     store notrap aligned region10 v4, v140
 ;; @0025                               v14 = load.i64 notrap aligned readonly can_move region2 v0+32
 ;; @0025                               v15 = load.i32 notrap aligned region3 v14
 ;; @0025                               v16 = load.i32 notrap aligned region4 v14+4
@@ -50,104 +50,103 @@
 ;; @0025                               brif v25, block2, block3
 ;;
 ;;                                 block2:
-;;                                     v253 = iconst.i32 32
-;;                                     v165 = iadd.i32 v15, v253  ; v253 = 32
-;; @0025                               store notrap aligned region3 v165, v14
-;;                                     v254 = iconst.i32 -1476394994
-;;                                     v255 = load.i64 notrap aligned readonly can_move region0 v0+8
-;;                                     v256 = load.i64 notrap aligned readonly can_move region7 v255+32
-;; @0025                               v39 = iadd v256, v22
-;; @0025                               store user2 region8 v254, v39  ; v254 = -1476394994
-;;                                     v257 = load.i64 notrap aligned readonly can_move region5 v0+40
-;;                                     v258 = load.i32 notrap aligned readonly can_move region6 v257
-;; @0025                               store user2 region8 v258, v39+4
-;;                                     v259 = iconst.i64 32
-;; @0025                               istore32 user2 region8 v259, v39+8  ; v259 = 32
+;;                                     v254 = iconst.i32 32
+;;                                     v166 = iadd.i32 v15, v254  ; v254 = 32
+;; @0025                               store notrap aligned region3 v166, v14
+;;                                     v255 = iconst.i32 -1476394994
+;;                                     v256 = load.i64 notrap aligned readonly can_move region0 v0+8
+;;                                     v257 = load.i64 notrap aligned readonly can_move region7 v256+32
+;; @0025                               v39 = iadd v257, v22
+;; @0025                               store user2 region8 v255, v39  ; v255 = -1476394994
+;;                                     v258 = load.i64 notrap aligned readonly can_move region5 v0+40
+;;                                     v259 = load.i32 notrap aligned readonly can_move region6 v258
+;; @0025                               store user2 region8 v259, v39+4
+;; @0025                               store user2 region8 v254, v39+8  ; v254 = 32
 ;; @0025                               jump block4(v15, v39)
 ;;
 ;;                                 block3 cold:
 ;; @0025                               v26 = iconst.i32 -1476394994
 ;; @0025                               v27 = load.i64 notrap aligned readonly can_move region5 v0+40
 ;; @0025                               v28 = load.i32 notrap aligned readonly can_move region6 v27
-;;                                     v151 = iconst.i32 32
+;;                                     v152 = iconst.i32 32
 ;; @0025                               v29 = iconst.i32 16
-;; @0025                               v30 = call fn0(v0, v26, v28, v151, v29), stack_map=[i32 @ ss2+0, i32 @ ss1+0, i32 @ ss0+0]  ; v26 = -1476394994, v151 = 32, v29 = 16
+;; @0025                               v30 = call fn0(v0, v26, v28, v152, v29), stack_map=[i32 @ ss2+0, i32 @ ss1+0, i32 @ ss0+0]  ; v26 = -1476394994, v152 = 32, v29 = 16
 ;; @0025                               v31 = load.i64 notrap aligned readonly can_move region0 v0+8
 ;; @0025                               v32 = load.i64 notrap aligned readonly can_move region7 v31+32
 ;; @0025                               v33 = uextend.i64 v30
 ;; @0025                               v34 = iadd v32, v33
 ;; @0025                               jump block4(v30, v34)
 ;;
-;;                                 block4(v43: i32, v44: i64):
+;;                                 block4(v44: i32, v45: i64):
 ;; @0025                               v5 = iconst.i32 3
-;; @0025                               v45 = iconst.i64 16
-;; @0025                               v46 = iadd v44, v45  ; v45 = 16
-;; @0025                               store user2 region8 v5, v46  ; v5 = 3
-;; @0025                               trapz v43, user16
+;; @0025                               v46 = iconst.i64 16
+;; @0025                               v47 = iadd v45, v46  ; v46 = 16
+;; @0025                               store user2 region8 v5, v47  ; v5 = 3
+;; @0025                               trapz v44, user16
 ;;                                     v260 = load.i64 notrap aligned readonly can_move region0 v0+8
 ;;                                     v261 = load.i64 notrap aligned readonly can_move region7 v260+32
-;; @0025                               v48 = uextend.i64 v43
-;; @0025                               v51 = iadd v261, v48
-;; @0025                               v53 = iadd v51, v45  ; v45 = 16
-;; @0025                               v54 = load.i32 user2 readonly region8 v53
-;; @0025                               trapz v54, user17
-;; @0025                               v57 = uextend.i64 v54
-;;                                     v142 = iconst.i64 2
-;;                                     v172 = ishl v57, v142  ; v142 = 2
+;; @0025                               v49 = uextend.i64 v44
+;; @0025                               v52 = iadd v261, v49
+;; @0025                               v54 = iadd v52, v46  ; v46 = 16
+;; @0025                               v55 = load.i32 user2 readonly region8 v54
+;; @0025                               trapz v55, user17
+;; @0025                               v58 = uextend.i64 v55
+;;                                     v143 = iconst.i64 2
+;;                                     v173 = ishl v58, v143  ; v143 = 2
 ;;                                     v262 = iconst.i64 32
-;;                                     v263 = ushr v172, v262  ; v262 = 32
+;;                                     v263 = ushr v173, v262  ; v262 = 32
 ;; @0025                               trapnz v263, user2
-;;                                     v179 = iconst.i32 2
-;;                                     v180 = ishl v54, v179  ; v179 = 2
+;;                                     v180 = iconst.i32 2
+;;                                     v181 = ishl v55, v180  ; v180 = 2
 ;; @0025                               v6 = iconst.i32 20
-;; @0025                               v63 = uadd_overflow_trap v180, v6, user2  ; v6 = 20
-;; @0025                               v67 = uadd_overflow_trap v43, v63, user2
-;;                                     v136 = load.i32 notrap aligned region12 v137
-;; @0025                               v68 = uextend.i64 v67
-;; @0025                               v71 = iadd v261, v68
-;; @0025                               v72 = isub v63, v6  ; v6 = 20
-;; @0025                               v73 = uextend.i64 v72
-;; @0025                               v74 = isub v71, v73
-;; @0025                               store user2 little region8 v136, v74
-;; @0025                               v82 = load.i32 user2 readonly region8 v53
-;; @0025                               v75 = iconst.i32 1
-;;                                     v196 = icmp ugt v82, v75  ; v75 = 1
-;; @0025                               trapz v196, user17
-;; @0025                               v85 = uextend.i64 v82
-;;                                     v199 = ishl v85, v142  ; v142 = 2
-;;                                     v264 = ushr v199, v262  ; v262 = 32
+;; @0025                               v64 = uadd_overflow_trap v181, v6, user2  ; v6 = 20
+;; @0025                               v68 = uadd_overflow_trap v44, v64, user2
+;;                                     v137 = load.i32 notrap aligned region12 v138
+;; @0025                               v69 = uextend.i64 v68
+;; @0025                               v72 = iadd v261, v69
+;; @0025                               v73 = isub v64, v6  ; v6 = 20
+;; @0025                               v74 = uextend.i64 v73
+;; @0025                               v75 = isub v72, v74
+;; @0025                               store user2 little region8 v137, v75
+;; @0025                               v83 = load.i32 user2 readonly region8 v54
+;; @0025                               v76 = iconst.i32 1
+;;                                     v197 = icmp ugt v83, v76  ; v76 = 1
+;; @0025                               trapz v197, user17
+;; @0025                               v86 = uextend.i64 v83
+;;                                     v200 = ishl v86, v143  ; v143 = 2
+;;                                     v264 = ushr v200, v262  ; v262 = 32
 ;; @0025                               trapnz v264, user2
-;;                                     v204 = ishl v82, v179  ; v179 = 2
-;; @0025                               v91 = uadd_overflow_trap v204, v6, user2  ; v6 = 20
-;; @0025                               v95 = uadd_overflow_trap v43, v91, user2
-;;                                     v134 = load.i32 notrap aligned region11 v138
-;; @0025                               v96 = uextend.i64 v95
-;; @0025                               v99 = iadd v261, v96
-;;                                     v216 = iconst.i32 24
-;; @0025                               v100 = isub v91, v216  ; v216 = 24
-;; @0025                               v101 = uextend.i64 v100
-;; @0025                               v102 = isub v99, v101
-;; @0025                               store user2 little region8 v134, v102
-;; @0025                               v110 = load.i32 user2 readonly region8 v53
-;;                                     v222 = icmp ugt v110, v179  ; v179 = 2
-;; @0025                               trapz v222, user17
-;; @0025                               v113 = uextend.i64 v110
-;;                                     v225 = ishl v113, v142  ; v142 = 2
-;;                                     v265 = ushr v225, v262  ; v262 = 32
+;;                                     v205 = ishl v83, v180  ; v180 = 2
+;; @0025                               v92 = uadd_overflow_trap v205, v6, user2  ; v6 = 20
+;; @0025                               v96 = uadd_overflow_trap v44, v92, user2
+;;                                     v135 = load.i32 notrap aligned region11 v139
+;; @0025                               v97 = uextend.i64 v96
+;; @0025                               v100 = iadd v261, v97
+;;                                     v217 = iconst.i32 24
+;; @0025                               v101 = isub v92, v217  ; v217 = 24
+;; @0025                               v102 = uextend.i64 v101
+;; @0025                               v103 = isub v100, v102
+;; @0025                               store user2 little region8 v135, v103
+;; @0025                               v111 = load.i32 user2 readonly region8 v54
+;;                                     v223 = icmp ugt v111, v180  ; v180 = 2
+;; @0025                               trapz v223, user17
+;; @0025                               v114 = uextend.i64 v111
+;;                                     v226 = ishl v114, v143  ; v143 = 2
+;;                                     v265 = ushr v226, v262  ; v262 = 32
 ;; @0025                               trapnz v265, user2
-;;                                     v230 = ishl v110, v179  ; v179 = 2
-;; @0025                               v119 = uadd_overflow_trap v230, v6, user2  ; v6 = 20
-;; @0025                               v123 = uadd_overflow_trap v43, v119, user2
-;;                                     v132 = load.i32 notrap aligned region10 v139
-;; @0025                               v124 = uextend.i64 v123
-;; @0025                               v127 = iadd v261, v124
-;;                                     v247 = iconst.i32 28
-;; @0025                               v128 = isub v119, v247  ; v247 = 28
-;; @0025                               v129 = uextend.i64 v128
-;; @0025                               v130 = isub v127, v129
-;; @0025                               store user2 little region8 v132, v130
+;;                                     v231 = ishl v111, v180  ; v180 = 2
+;; @0025                               v120 = uadd_overflow_trap v231, v6, user2  ; v6 = 20
+;; @0025                               v124 = uadd_overflow_trap v44, v120, user2
+;;                                     v133 = load.i32 notrap aligned region10 v140
+;; @0025                               v125 = uextend.i64 v124
+;; @0025                               v128 = iadd v261, v125
+;;                                     v248 = iconst.i32 28
+;; @0025                               v129 = isub v120, v248  ; v248 = 28
+;; @0025                               v130 = uextend.i64 v129
+;; @0025                               v131 = isub v128, v130
+;; @0025                               store user2 little region8 v133, v131
 ;; @0029                               jump block1
 ;;
 ;;                                 block1:
-;; @0029                               return v43
+;; @0029                               return v44
 ;; }
diff --git a/tests/disas/gc/copying/array-new-fixed.wat b/tests/disas/gc/copying/array-new-fixed.wat
index 59c33d89e77f..cb3b6977414e 100644
--- a/tests/disas/gc/copying/array-new-fixed.wat
+++ b/tests/disas/gc/copying/array-new-fixed.wat
@@ -31,108 +31,107 @@
 ;; @0025                               v15 = load.i32 notrap aligned region3 v14
 ;; @0025                               v16 = load.i32 notrap aligned region4 v14+4
 ;; @0025                               v22 = uextend.i64 v15
-;;                                     v141 = iconst.i64 48
-;; @0025                               v23 = iadd v22, v141  ; v141 = 48
+;;                                     v142 = iconst.i64 48
+;; @0025                               v23 = iadd v22, v142  ; v142 = 48
 ;; @0025                               v24 = uextend.i64 v16
 ;; @0025                               v25 = icmp ule v23, v24
 ;; @0025                               brif v25, block2, block3
 ;;
 ;;                                 block2:
-;;                                     v241 = iconst.i32 48
-;;                                     v155 = iadd.i32 v15, v241  ; v241 = 48
-;; @0025                               store notrap aligned region3 v155, v14
-;;                                     v242 = iconst.i32 -1476395002
-;;                                     v243 = load.i64 notrap aligned readonly can_move region0 v0+8
-;;                                     v244 = load.i64 notrap aligned readonly can_move region7 v243+32
-;; @0025                               v39 = iadd v244, v22
-;; @0025                               store user2 region8 v242, v39  ; v242 = -1476395002
-;;                                     v245 = load.i64 notrap aligned readonly can_move region5 v0+40
-;;                                     v246 = load.i32 notrap aligned readonly can_move region6 v245
-;; @0025                               store user2 region8 v246, v39+4
-;;                                     v247 = iconst.i64 48
-;; @0025                               istore32 user2 region8 v247, v39+8  ; v247 = 48
+;;                                     v242 = iconst.i32 48
+;;                                     v156 = iadd.i32 v15, v242  ; v242 = 48
+;; @0025                               store notrap aligned region3 v156, v14
+;;                                     v243 = iconst.i32 -1476395002
+;;                                     v244 = load.i64 notrap aligned readonly can_move region0 v0+8
+;;                                     v245 = load.i64 notrap aligned readonly can_move region7 v244+32
+;; @0025                               v39 = iadd v245, v22
+;; @0025                               store user2 region8 v243, v39  ; v243 = -1476395002
+;;                                     v246 = load.i64 notrap aligned readonly can_move region5 v0+40
+;;                                     v247 = load.i32 notrap aligned readonly can_move region6 v246
+;; @0025                               store user2 region8 v247, v39+4
+;; @0025                               store user2 region8 v242, v39+8  ; v242 = 48
 ;; @0025                               jump block4(v15, v39)
 ;;
 ;;                                 block3 cold:
 ;; @0025                               v26 = iconst.i32 -1476395002
 ;; @0025                               v27 = load.i64 notrap aligned readonly can_move region5 v0+40
 ;; @0025                               v28 = load.i32 notrap aligned readonly can_move region6 v27
-;;                                     v140 = iconst.i32 48
+;;                                     v141 = iconst.i32 48
 ;; @0025                               v29 = iconst.i32 16
-;; @0025                               v30 = call fn0(v0, v26, v28, v140, v29)  ; v26 = -1476395002, v140 = 48, v29 = 16
+;; @0025                               v30 = call fn0(v0, v26, v28, v141, v29)  ; v26 = -1476395002, v141 = 48, v29 = 16
 ;; @0025                               v31 = load.i64 notrap aligned readonly can_move region0 v0+8
 ;; @0025                               v32 = load.i64 notrap aligned readonly can_move region7 v31+32
 ;; @0025                               v33 = uextend.i64 v30
 ;; @0025                               v34 = iadd v32, v33
 ;; @0025                               jump block4(v30, v34)
 ;;
-;;                                 block4(v43: i32, v44: i64):
+;;                                 block4(v44: i32, v45: i64):
 ;; @0025                               v5 = iconst.i32 3
-;; @0025                               v45 = iconst.i64 16
-;; @0025                               v46 = iadd v44, v45  ; v45 = 16
-;; @0025                               store user2 region8 v5, v46  ; v5 = 3
-;; @0025                               trapz v43, user16
+;; @0025                               v46 = iconst.i64 16
+;; @0025                               v47 = iadd v45, v46  ; v46 = 16
+;; @0025                               store user2 region8 v5, v47  ; v5 = 3
+;; @0025                               trapz v44, user16
 ;;                                     v248 = load.i64 notrap aligned readonly can_move region0 v0+8
 ;;                                     v249 = load.i64 notrap aligned readonly can_move region7 v248+32
-;; @0025                               v48 = uextend.i64 v43
-;; @0025                               v51 = iadd v249, v48
-;; @0025                               v53 = iadd v51, v45  ; v45 = 16
-;; @0025                               v54 = load.i32 user2 readonly region8 v53
-;; @0025                               trapz v54, user17
-;; @0025                               v57 = uextend.i64 v54
-;;                                     v131 = iconst.i64 3
-;;                                     v162 = ishl v57, v131  ; v131 = 3
+;; @0025                               v49 = uextend.i64 v44
+;; @0025                               v52 = iadd v249, v49
+;; @0025                               v54 = iadd v52, v46  ; v46 = 16
+;; @0025                               v55 = load.i32 user2 readonly region8 v54
+;; @0025                               trapz v55, user17
+;; @0025                               v58 = uextend.i64 v55
+;;                                     v132 = iconst.i64 3
+;;                                     v163 = ishl v58, v132  ; v132 = 3
 ;; @0025                               v10 = iconst.i64 32
-;; @0025                               v60 = ushr v162, v10  ; v10 = 32
-;; @0025                               trapnz v60, user2
-;;                                     v169 = ishl v54, v5  ; v5 = 3
+;; @0025                               v61 = ushr v163, v10  ; v10 = 32
+;; @0025                               trapnz v61, user2
+;;                                     v170 = ishl v55, v5  ; v5 = 3
 ;; @0025                               v6 = iconst.i32 24
-;; @0025                               v63 = uadd_overflow_trap v169, v6, user2  ; v6 = 24
-;; @0025                               v67 = uadd_overflow_trap v43, v63, user2
-;; @0025                               v68 = uextend.i64 v67
-;; @0025                               v71 = iadd v249, v68
-;; @0025                               v72 = isub v63, v6  ; v6 = 24
-;; @0025                               v73 = uextend.i64 v72
-;; @0025                               v74 = isub v71, v73
-;; @0025                               store.i64 user2 little region8 v2, v74
-;; @0025                               v82 = load.i32 user2 readonly region8 v53
-;; @0025                               v75 = iconst.i32 1
-;;                                     v185 = icmp ugt v82, v75  ; v75 = 1
-;; @0025                               trapz v185, user17
-;; @0025                               v85 = uextend.i64 v82
-;;                                     v188 = ishl v85, v131  ; v131 = 3
-;; @0025                               v88 = ushr v188, v10  ; v10 = 32
-;; @0025                               trapnz v88, user2
-;;                                     v193 = ishl v82, v5  ; v5 = 3
-;; @0025                               v91 = uadd_overflow_trap v193, v6, user2  ; v6 = 24
-;; @0025                               v95 = uadd_overflow_trap v43, v91, user2
-;; @0025                               v96 = uextend.i64 v95
-;; @0025                               v99 = iadd v249, v96
-;;                                     v205 = iconst.i32 32
-;; @0025                               v100 = isub v91, v205  ; v205 = 32
-;; @0025                               v101 = uextend.i64 v100
-;; @0025                               v102 = isub v99, v101
-;; @0025                               store.i64 user2 little region8 v3, v102
-;; @0025                               v110 = load.i32 user2 readonly region8 v53
-;; @0025                               v103 = iconst.i32 2
-;;                                     v211 = icmp ugt v110, v103  ; v103 = 2
-;; @0025                               trapz v211, user17
-;; @0025                               v113 = uextend.i64 v110
-;;                                     v214 = ishl v113, v131  ; v131 = 3
-;; @0025                               v116 = ushr v214, v10  ; v10 = 32
-;; @0025                               trapnz v116, user2
-;;                                     v219 = ishl v110, v5  ; v5 = 3
-;; @0025                               v119 = uadd_overflow_trap v219, v6, user2  ; v6 = 24
-;; @0025                               v123 = uadd_overflow_trap v43, v119, user2
-;; @0025                               v124 = uextend.i64 v123
-;; @0025                               v127 = iadd v249, v124
-;;                                     v235 = iconst.i32 40
-;; @0025                               v128 = isub v119, v235  ; v235 = 40
-;; @0025                               v129 = uextend.i64 v128
-;; @0025                               v130 = isub v127, v129
-;; @0025                               store.i64 user2 little region8 v4, v130
+;; @0025                               v64 = uadd_overflow_trap v170, v6, user2  ; v6 = 24
+;; @0025                               v68 = uadd_overflow_trap v44, v64, user2
+;; @0025                               v69 = uextend.i64 v68
+;; @0025                               v72 = iadd v249, v69
+;; @0025                               v73 = isub v64, v6  ; v6 = 24
+;; @0025                               v74 = uextend.i64 v73
+;; @0025                               v75 = isub v72, v74
+;; @0025                               store.i64 user2 little region8 v2, v75
+;; @0025                               v83 = load.i32 user2 readonly region8 v54
+;; @0025                               v76 = iconst.i32 1
+;;                                     v186 = icmp ugt v83, v76  ; v76 = 1
+;; @0025                               trapz v186, user17
+;; @0025                               v86 = uextend.i64 v83
+;;                                     v189 = ishl v86, v132  ; v132 = 3
+;; @0025                               v89 = ushr v189, v10  ; v10 = 32
+;; @0025                               trapnz v89, user2
+;;                                     v194 = ishl v83, v5  ; v5 = 3
+;; @0025                               v92 = uadd_overflow_trap v194, v6, user2  ; v6 = 24
+;; @0025                               v96 = uadd_overflow_trap v44, v92, user2
+;; @0025                               v97 = uextend.i64 v96
+;; @0025                               v100 = iadd v249, v97
+;;                                     v206 = iconst.i32 32
+;; @0025                               v101 = isub v92, v206  ; v206 = 32
+;; @0025                               v102 = uextend.i64 v101
+;; @0025                               v103 = isub v100, v102
+;; @0025                               store.i64 user2 little region8 v3, v103
+;; @0025                               v111 = load.i32 user2 readonly region8 v54
+;; @0025                               v104 = iconst.i32 2
+;;                                     v212 = icmp ugt v111, v104  ; v104 = 2
+;; @0025                               trapz v212, user17
+;; @0025                               v114 = uextend.i64 v111
+;;                                     v215 = ishl v114, v132  ; v132 = 3
+;; @0025                               v117 = ushr v215, v10  ; v10 = 32
+;; @0025                               trapnz v117, user2
+;;                                     v220 = ishl v111, v5  ; v5 = 3
+;; @0025                               v120 = uadd_overflow_trap v220, v6, user2  ; v6 = 24
+;; @0025                               v124 = uadd_overflow_trap v44, v120, user2
+;; @0025                               v125 = uextend.i64 v124
+;; @0025                               v128 = iadd v249, v125
+;;                                     v236 = iconst.i32 40
+;; @0025                               v129 = isub v120, v236  ; v236 = 40
+;; @0025                               v130 = uextend.i64 v129
+;; @0025                               v131 = isub v128, v130
+;; @0025                               store.i64 user2 little region8 v4, v131
 ;; @0029                               jump block1
 ;;
 ;;                                 block1:
-;; @0029                               return v43
+;; @0029                               return v44
 ;; }
diff --git a/tests/disas/gc/copying/array-new.wat b/tests/disas/gc/copying/array-new.wat
index ab880a95bff6..24d59a2335c2 100644
--- a/tests/disas/gc/copying/array-new.wat
+++ b/tests/disas/gc/copying/array-new.wat
@@ -28,15 +28,15 @@
 ;;
 ;;                                 block0(v0: i64, v1: i64, v2: i64, v3: i32):
 ;; @0022                               v5 = uextend.i64 v3
-;;                                     v87 = iconst.i64 3
-;;                                     v88 = ishl v5, v87  ; v87 = 3
+;;                                     v88 = iconst.i64 3
+;;                                     v89 = ishl v5, v88  ; v88 = 3
 ;; @0022                               v8 = iconst.i64 32
-;; @0022                               v9 = ushr v88, v8  ; v8 = 32
+;; @0022                               v9 = ushr v89, v8  ; v8 = 32
 ;; @0022                               trapnz v9, user18
 ;; @0022                               v4 = iconst.i32 24
-;;                                     v94 = iconst.i32 3
-;;                                     v95 = ishl v3, v94  ; v94 = 3
-;; @0022                               v11 = uadd_overflow_trap v4, v95, user18  ; v4 = 24
+;;                                     v95 = iconst.i32 3
+;;                                     v96 = ishl v3, v95  ; v95 = 3
+;; @0022                               v11 = uadd_overflow_trap v4, v96, user18  ; v4 = 24
 ;; @0022                               v12 = load.i64 notrap aligned readonly can_move region2 v0+32
 ;; @0022                               v13 = load.i32 notrap aligned region3 v12
 ;; @0022                               v14 = load.i32 notrap aligned region4 v12+4
@@ -52,22 +52,21 @@
 ;; @0022                               brif v23, block2, block3
 ;;
 ;;                                 block2:
-;;                                     v103 = iconst.i32 15
-;;                                     v104 = iadd.i32 v11, v103  ; v103 = 15
-;;                                     v107 = iconst.i32 -16
-;;                                     v108 = band v104, v107  ; v107 = -16
-;;                                     v110 = iadd.i32 v13, v108
-;; @0022                               store notrap aligned region3 v110, v12
-;;                                     v126 = iconst.i32 -1476395002
-;;                                     v127 = load.i64 notrap aligned readonly can_move region0 v0+8
-;;                                     v128 = load.i64 notrap aligned readonly can_move region7 v127+32
-;; @0022                               v37 = iadd v128, v20
-;; @0022                               store user2 region8 v126, v37  ; v126 = -1476395002
-;;                                     v129 = load.i64 notrap aligned readonly can_move region5 v0+40
-;;                                     v130 = load.i32 notrap aligned readonly can_move region6 v129
-;; @0022                               store user2 region8 v130, v37+4
-;;                                     v131 = band.i64 v18, v17  ; v17 = -16
-;; @0022                               istore32 user2 region8 v131, v37+8
+;;                                     v104 = iconst.i32 15
+;;                                     v105 = iadd.i32 v11, v104  ; v104 = 15
+;;                                     v108 = iconst.i32 -16
+;;                                     v109 = band v105, v108  ; v108 = -16
+;;                                     v111 = iadd.i32 v13, v109
+;; @0022                               store notrap aligned region3 v111, v12
+;;                                     v127 = iconst.i32 -1476395002
+;;                                     v128 = load.i64 notrap aligned readonly can_move region0 v0+8
+;;                                     v129 = load.i64 notrap aligned readonly can_move region7 v128+32
+;; @0022                               v37 = iadd v129, v20
+;; @0022                               store user2 region8 v127, v37  ; v127 = -1476395002
+;;                                     v130 = load.i64 notrap aligned readonly can_move region5 v0+40
+;;                                     v131 = load.i32 notrap aligned readonly can_move region6 v130
+;; @0022                               store user2 region8 v131, v37+4
+;; @0022                               store user2 region8 v109, v37+8
 ;; @0022                               jump block4(v13, v37)
 ;;
 ;;                                 block3 cold:
@@ -82,43 +81,43 @@
 ;; @0022                               v32 = iadd v30, v31
 ;; @0022                               jump block4(v28, v32)
 ;;
-;;                                 block4(v41: i32, v42: i64):
-;; @0022                               v43 = iconst.i64 16
-;; @0022                               v44 = iadd v42, v43  ; v43 = 16
-;; @0022                               store.i32 user2 region8 v3, v44
-;; @0022                               trapz v41, user16
+;;                                 block4(v42: i32, v43: i64):
+;; @0022                               v44 = iconst.i64 16
+;; @0022                               v45 = iadd v43, v44  ; v44 = 16
+;; @0022                               store.i32 user2 region8 v3, v45
+;; @0022                               trapz v42, user16
 ;;                                     v132 = load.i64 notrap aligned readonly can_move region0 v0+8
 ;;                                     v133 = load.i64 notrap aligned readonly can_move region7 v132+32
-;; @0022                               v46 = uextend.i64 v41
-;; @0022                               v49 = iadd v133, v46
-;; @0022                               v51 = iadd v49, v43  ; v43 = 16
-;; @0022                               v52 = load.i32 user2 readonly region8 v51
-;; @0022                               v53 = uextend.i64 v52
-;; @0022                               v59 = icmp.i64 ugt v5, v53
-;; @0022                               trapnz v59, user17
-;; @0022                               v76 = load.i64 notrap aligned region9 v132+40
-;; @0022                               v64 = iconst.i64 24
-;; @0022                               v65 = iadd v49, v64  ; v64 = 24
-;; @0022                               v78 = uadd_overflow_trap v65, v88, user2
-;; @0022                               v77 = iadd v133, v76
-;; @0022                               v79 = icmp ugt v78, v77
-;; @0022                               trapnz v79, user2
-;;                                     v112 = iconst.i64 0
-;; @0022                               v82 = icmp.i64 eq v5, v112  ; v112 = 0
+;; @0022                               v47 = uextend.i64 v42
+;; @0022                               v50 = iadd v133, v47
+;; @0022                               v52 = iadd v50, v44  ; v44 = 16
+;; @0022                               v53 = load.i32 user2 readonly region8 v52
+;; @0022                               v54 = uextend.i64 v53
+;; @0022                               v60 = icmp.i64 ugt v5, v54
+;; @0022                               trapnz v60, user17
+;; @0022                               v77 = load.i64 notrap aligned region9 v132+40
+;; @0022                               v65 = iconst.i64 24
+;; @0022                               v66 = iadd v50, v65  ; v65 = 24
+;; @0022                               v79 = uadd_overflow_trap v66, v89, user2
+;; @0022                               v78 = iadd v133, v77
+;; @0022                               v80 = icmp ugt v79, v78
+;; @0022                               trapnz v80, user2
+;;                                     v113 = iconst.i64 0
+;; @0022                               v83 = icmp.i64 eq v5, v113  ; v113 = 0
 ;; @0022                               v6 = iconst.i64 8
-;; @0022                               v80 = iadd v65, v88
-;; @0022                               brif v82, block6, block5(v65)
+;; @0022                               v81 = iadd v66, v89
+;; @0022                               brif v83, block6, block5(v66)
 ;;
-;;                                 block5(v83: i64):
-;; @0022                               store.i64 user2 little region8 v2, v83
+;;                                 block5(v84: i64):
+;; @0022                               store.i64 user2 little region8 v2, v84
 ;;                                     v134 = iconst.i64 8
-;;                                     v135 = iadd v83, v134  ; v134 = 8
-;; @0022                               v86 = icmp eq v135, v80
-;; @0022                               brif v86, block6, block5(v135)
+;;                                     v135 = iadd v84, v134  ; v134 = 8
+;; @0022                               v87 = icmp eq v135, v81
+;; @0022                               brif v87, block6, block5(v135)
 ;;
 ;;                                 block6:
 ;; @0025                               jump block1
 ;;
 ;;                                 block1:
-;; @0025                               return v41
+;; @0025                               return v42
 ;; }
diff --git a/tests/disas/gc/copying/funcref-in-gc-heap-new.wat b/tests/disas/gc/copying/funcref-in-gc-heap-new.wat
index 95345ad6a2a1..1ad16d046b29 100644
--- a/tests/disas/gc/copying/funcref-in-gc-heap-new.wat
+++ b/tests/disas/gc/copying/funcref-in-gc-heap-new.wat
@@ -34,26 +34,25 @@
 ;; @0020                               v5 = load.i32 notrap aligned region3 v4
 ;; @0020                               v6 = load.i32 notrap aligned region4 v4+4
 ;; @0020                               v12 = uextend.i64 v5
-;;                                     v42 = iconst.i64 32
-;; @0020                               v13 = iadd v12, v42  ; v42 = 32
+;;                                     v43 = iconst.i64 32
+;; @0020                               v13 = iadd v12, v43  ; v43 = 32
 ;; @0020                               v14 = uextend.i64 v6
 ;; @0020                               v15 = icmp ule v13, v14
 ;; @0020                               brif v15, block2, block3
 ;;
 ;;                                 block2:
-;;                                     v58 = iconst.i32 32
-;;                                     v56 = iadd.i32 v5, v58  ; v58 = 32
-;; @0020                               store notrap aligned region3 v56, v4
-;;                                     v59 = iconst.i32 -1342177278
-;;                                     v60 = load.i64 notrap aligned readonly can_move region0 v0+8
-;;                                     v61 = load.i64 notrap aligned readonly can_move region7 v60+32
-;; @0020                               v29 = iadd v61, v12
-;; @0020                               store user2 region8 v59, v29  ; v59 = -1342177278
-;;                                     v62 = load.i64 notrap aligned readonly can_move region5 v0+40
-;;                                     v63 = load.i32 notrap aligned readonly can_move region6 v62
-;; @0020                               store user2 region8 v63, v29+4
-;;                                     v64 = iconst.i64 32
-;; @0020                               istore32 user2 region8 v64, v29+8  ; v64 = 32
+;;                                     v59 = iconst.i32 32
+;;                                     v57 = iadd.i32 v5, v59  ; v59 = 32
+;; @0020                               store notrap aligned region3 v57, v4
+;;                                     v60 = iconst.i32 -1342177278
+;;                                     v61 = load.i64 notrap aligned readonly can_move region0 v0+8
+;;                                     v62 = load.i64 notrap aligned readonly can_move region7 v61+32
+;; @0020                               v29 = iadd v62, v12
+;; @0020                               store user2 region8 v60, v29  ; v60 = -1342177278
+;;                                     v63 = load.i64 notrap aligned readonly can_move region5 v0+40
+;;                                     v64 = load.i32 notrap aligned readonly can_move region6 v63
+;; @0020                               store user2 region8 v64, v29+4
+;; @0020                               store user2 region8 v59, v29+8  ; v59 = 32
 ;; @0020                               jump block4(v5, v29)
 ;;
 ;;                                 block3 cold:
@@ -69,17 +68,17 @@
 ;; @0020                               v24 = iadd v22, v23
 ;; @0020                               jump block4(v20, v24)
 ;;
-;;                                 block4(v33: i32, v34: i64):
-;;                                     v41 = stack_addr.i64 ss0
-;;                                     store notrap aligned region9 v33, v41
-;; @0020                               v37 = call fn1(v0, v2), stack_map=[i32 @ ss0+0]
-;; @0020                               v38 = ireduce.i32 v37
-;; @0020                               v35 = iconst.i64 16
-;; @0020                               v36 = iadd v34, v35  ; v35 = 16
-;; @0020                               store user2 little region8 v38, v36
+;;                                 block4(v34: i32, v35: i64):
+;;                                     v42 = stack_addr.i64 ss0
+;;                                     store notrap aligned region9 v34, v42
+;; @0020                               v38 = call fn1(v0, v2), stack_map=[i32 @ ss0+0]
+;; @0020                               v39 = ireduce.i32 v38
+;; @0020                               v36 = iconst.i64 16
+;; @0020                               v37 = iadd v35, v36  ; v36 = 16
+;; @0020                               store user2 little region8 v39, v37
 ;; @0023                               jump block1
 ;;
 ;;                                 block1:
-;;                                     v40 = load.i32 notrap aligned region9 v41
-;; @0023                               return v40
+;;                                     v41 = load.i32 notrap aligned region9 v42
+;; @0023                               return v41
 ;; }
diff --git a/tests/disas/gc/copying/struct-new-default.wat b/tests/disas/gc/copying/struct-new-default.wat
index 4345e54f18e7..2fb2748142b6 100644
--- a/tests/disas/gc/copying/struct-new-default.wat
+++ b/tests/disas/gc/copying/struct-new-default.wat
@@ -32,26 +32,25 @@
 ;; @0021                               v7 = load.i32 notrap aligned region3 v6
 ;; @0021                               v8 = load.i32 notrap aligned region4 v6+4
 ;; @0021                               v14 = uextend.i64 v7
-;;                                     v43 = iconst.i64 32
-;; @0021                               v15 = iadd v14, v43  ; v43 = 32
+;;                                     v45 = iconst.i64 32
+;; @0021                               v15 = iadd v14, v45  ; v45 = 32
 ;; @0021                               v16 = uextend.i64 v8
 ;; @0021                               v17 = icmp ule v15, v16
 ;; @0021                               brif v17, block2, block3
 ;;
 ;;                                 block2:
-;;                                     v59 = iconst.i32 32
-;;                                     v57 = iadd.i32 v7, v59  ; v59 = 32
-;; @0021                               store notrap aligned region3 v57, v6
-;;                                     v60 = iconst.i32 -1342177246
-;;                                     v61 = load.i64 notrap aligned readonly can_move region0 v0+8
-;;                                     v62 = load.i64 notrap aligned readonly can_move region7 v61+32
-;; @0021                               v31 = iadd v62, v14
-;; @0021                               store user2 region8 v60, v31  ; v60 = -1342177246
-;;                                     v63 = load.i64 notrap aligned readonly can_move region5 v0+40
-;;                                     v64 = load.i32 notrap aligned readonly can_move region6 v63
-;; @0021                               store user2 region8 v64, v31+4
-;;                                     v65 = iconst.i64 32
-;; @0021                               istore32 user2 region8 v65, v31+8  ; v65 = 32
+;;                                     v62 = iconst.i32 32
+;;                                     v59 = iadd.i32 v7, v62  ; v62 = 32
+;; @0021                               store notrap aligned region3 v59, v6
+;;                                     v63 = iconst.i32 -1342177246
+;;                                     v64 = load.i64 notrap aligned readonly can_move region0 v0+8
+;;                                     v65 = load.i64 notrap aligned readonly can_move region7 v64+32
+;; @0021                               v31 = iadd v65, v14
+;; @0021                               store user2 region8 v63, v31  ; v63 = -1342177246
+;;                                     v66 = load.i64 notrap aligned readonly can_move region5 v0+40
+;;                                     v67 = load.i32 notrap aligned readonly can_move region6 v66
+;; @0021                               store user2 region8 v67, v31+4
+;; @0021                               store user2 region8 v62, v31+8  ; v62 = 32
 ;; @0021                               jump block4(v7, v31)
 ;;
 ;;                                 block3 cold:
@@ -67,20 +66,21 @@
 ;; @0021                               v26 = iadd v24, v25
 ;; @0021                               jump block4(v22, v26)
 ;;
-;;                                 block4(v35: i32, v36: i64):
+;;                                 block4(v36: i32, v37: i64):
 ;; @0021                               v2 = f32const 0.0
-;; @0021                               v37 = iconst.i64 16
-;; @0021                               v38 = iadd v36, v37  ; v37 = 16
-;; @0021                               store user2 little region8 v2, v38  ; v2 = 0.0
+;; @0021                               v38 = iconst.i64 16
+;; @0021                               v39 = iadd v37, v38  ; v38 = 16
+;; @0021                               store user2 little region8 v2, v39  ; v2 = 0.0
+;;                                     v61 = iconst.i8 0
+;; @0021                               v40 = iconst.i64 20
+;; @0021                               v41 = iadd v37, v40  ; v40 = 20
+;; @0021                               store user2 little region8 v61, v41  ; v61 = 0
 ;; @0021                               v3 = iconst.i32 0
-;; @0021                               v39 = iconst.i64 20
-;; @0021                               v40 = iadd v36, v39  ; v39 = 20
-;; @0021                               istore8 user2 little region8 v3, v40  ; v3 = 0
-;; @0021                               v41 = iconst.i64 24
-;; @0021                               v42 = iadd v36, v41  ; v41 = 24
-;; @0021                               store user2 little region8 v3, v42  ; v3 = 0
+;; @0021                               v43 = iconst.i64 24
+;; @0021                               v44 = iadd v37, v43  ; v43 = 24
+;; @0021                               store user2 little region8 v3, v44  ; v3 = 0
 ;; @0024                               jump block1
 ;;
 ;;                                 block1:
-;; @0024                               return v35
+;; @0024                               return v36
 ;; }
diff --git a/tests/disas/gc/copying/struct-new.wat b/tests/disas/gc/copying/struct-new.wat
index 5d3c5033635d..01fabea96165 100644
--- a/tests/disas/gc/copying/struct-new.wat
+++ b/tests/disas/gc/copying/struct-new.wat
@@ -30,32 +30,31 @@
 ;;     stack_limit = gv2
 ;;
 ;;                                 block0(v0: i64, v1: i64, v2: f32, v3: i32, v4: i32):
-;;                                     v45 = stack_addr.i64 ss0
-;;                                     store notrap aligned region9 v4, v45
+;;                                     v47 = stack_addr.i64 ss0
+;;                                     store notrap aligned region9 v4, v47
 ;; @002a                               v6 = load.i64 notrap aligned readonly can_move region2 v0+32
 ;; @002a                               v7 = load.i32 notrap aligned region3 v6
 ;; @002a                               v8 = load.i32 notrap aligned region4 v6+4
 ;; @002a                               v14 = uextend.i64 v7
-;;                                     v46 = iconst.i64 32
-;; @002a                               v15 = iadd v14, v46  ; v46 = 32
+;;                                     v48 = iconst.i64 32
+;; @002a                               v15 = iadd v14, v48  ; v48 = 32
 ;; @002a                               v16 = uextend.i64 v8
 ;; @002a                               v17 = icmp ule v15, v16
 ;; @002a                               brif v17, block2, block3
 ;;
 ;;                                 block2:
-;;                                     v62 = iconst.i32 32
-;;                                     v60 = iadd.i32 v7, v62  ; v62 = 32
-;; @002a                               store notrap aligned region3 v60, v6
-;;                                     v63 = iconst.i32 -1342177246
-;;                                     v64 = load.i64 notrap aligned readonly can_move region0 v0+8
-;;                                     v65 = load.i64 notrap aligned readonly can_move region7 v64+32
-;; @002a                               v31 = iadd v65, v14
-;; @002a                               store user2 region8 v63, v31  ; v63 = -1342177246
-;;                                     v66 = load.i64 notrap aligned readonly can_move region5 v0+40
-;;                                     v67 = load.i32 notrap aligned readonly can_move region6 v66
-;; @002a                               store user2 region8 v67, v31+4
-;;                                     v68 = iconst.i64 32
-;; @002a                               istore32 user2 region8 v68, v31+8  ; v68 = 32
+;;                                     v64 = iconst.i32 32
+;;                                     v62 = iadd.i32 v7, v64  ; v64 = 32
+;; @002a                               store notrap aligned region3 v62, v6
+;;                                     v65 = iconst.i32 -1342177246
+;;                                     v66 = load.i64 notrap aligned readonly can_move region0 v0+8
+;;                                     v67 = load.i64 notrap aligned readonly can_move region7 v66+32
+;; @002a                               v31 = iadd v67, v14
+;; @002a                               store user2 region8 v65, v31  ; v65 = -1342177246
+;;                                     v68 = load.i64 notrap aligned readonly can_move region5 v0+40
+;;                                     v69 = load.i32 notrap aligned readonly can_move region6 v68
+;; @002a                               store user2 region8 v69, v31+4
+;; @002a                               store user2 region8 v64, v31+8  ; v64 = 32
 ;; @002a                               jump block4(v7, v31)
 ;;
 ;;                                 block3 cold:
@@ -71,19 +70,20 @@
 ;; @002a                               v26 = iadd v24, v25
 ;; @002a                               jump block4(v22, v26)
 ;;
-;;                                 block4(v35: i32, v36: i64):
-;; @002a                               v37 = iconst.i64 16
-;; @002a                               v38 = iadd v36, v37  ; v37 = 16
-;; @002a                               store.f32 user2 little region8 v2, v38
-;; @002a                               v39 = iconst.i64 20
-;; @002a                               v40 = iadd v36, v39  ; v39 = 20
-;; @002a                               istore8.i32 user2 little region8 v3, v40
-;;                                     v44 = load.i32 notrap aligned region9 v45
-;; @002a                               v41 = iconst.i64 24
-;; @002a                               v42 = iadd v36, v41  ; v41 = 24
-;; @002a                               store user2 little region8 v44, v42
+;;                                 block4(v36: i32, v37: i64):
+;; @002a                               v38 = iconst.i64 16
+;; @002a                               v39 = iadd v37, v38  ; v38 = 16
+;; @002a                               store.f32 user2 little region8 v2, v39
+;; @002a                               v42 = ireduce.i8 v3
+;; @002a                               v40 = iconst.i64 20
+;; @002a                               v41 = iadd v37, v40  ; v40 = 20
+;; @002a                               store user2 little region8 v42, v41
+;;                                     v46 = load.i32 notrap aligned region9 v47
+;; @002a                               v43 = iconst.i64 24
+;; @002a                               v44 = iadd v37, v43  ; v43 = 24
+;; @002a                               store user2 little region8 v46, v44
 ;; @002d                               jump block1
 ;;
 ;;                                 block1:
-;; @002d                               return v35
+;; @002d                               return v36
 ;; }
diff --git a/tests/disas/gc/copying/struct-set.wat b/tests/disas/gc/copying/struct-set.wat
index e04ddcf2b202..707cfc6f9e11 100644
--- a/tests/disas/gc/copying/struct-set.wat
+++ b/tests/disas/gc/copying/struct-set.wat
@@ -57,13 +57,14 @@
 ;;
 ;;                                 block0(v0: i64, v1: i64, v2: i32, v3: i32):
 ;; @003f                               trapz v2, user16
+;; @003f                               v10 = ireduce.i8 v3
 ;; @003f                               v5 = load.i64 notrap aligned readonly can_move region0 v0+8
 ;; @003f                               v6 = load.i64 notrap aligned readonly can_move region2 v5+32
 ;; @003f                               v4 = uextend.i64 v2
 ;; @003f                               v7 = iadd v6, v4
 ;; @003f                               v8 = iconst.i64 20
 ;; @003f                               v9 = iadd v7, v8  ; v8 = 20
-;; @003f                               istore8 user2 little region4 v3, v9
+;; @003f                               store user2 little region4 v10, v9
 ;; @0043                               jump block1
 ;;
 ;;                                 block1:
diff --git a/tests/disas/gc/drc/struct-new-default.wat b/tests/disas/gc/drc/struct-new-default.wat
index 913b5862d4b3..2e44fe1c00e7 100644
--- a/tests/disas/gc/drc/struct-new-default.wat
+++ b/tests/disas/gc/drc/struct-new-default.wat
@@ -41,17 +41,17 @@
 ;; @0021                               v15 = iconst.i64 24
 ;; @0021                               v16 = iadd v14, v15  ; v15 = 24
 ;; @0021                               store user2 little region5 v2, v16  ; v2 = 0.0
-;; @0021                               v3 = iconst.i32 0
+;;                                     v43 = iconst.i8 0
 ;; @0021                               v17 = iconst.i64 28
 ;; @0021                               v18 = iadd v14, v17  ; v17 = 28
-;; @0021                               istore8 user2 little region5 v3, v18  ; v3 = 0
+;; @0021                               store user2 little region5 v43, v18  ; v43 = 0
 ;; @0021                               jump block3
 ;;
 ;;                                 block3:
-;;                                     v59 = iconst.i32 0
-;; @0021                               v19 = iconst.i64 32
-;; @0021                               v20 = iadd.i64 v14, v19  ; v19 = 32
-;; @0021                               store user2 little region5 v59, v20  ; v59 = 0
+;; @0021                               v3 = iconst.i32 0
+;; @0021                               v20 = iconst.i64 32
+;; @0021                               v21 = iadd.i64 v14, v20  ; v20 = 32
+;; @0021                               store user2 little region5 v3, v21  ; v3 = 0
 ;; @0024                               jump block1
 ;;
 ;;                                 block1:
diff --git a/tests/disas/gc/drc/struct-new.wat b/tests/disas/gc/drc/struct-new.wat
index 5c83bed9c857..396948dff91b 100644
--- a/tests/disas/gc/drc/struct-new.wat
+++ b/tests/disas/gc/drc/struct-new.wat
@@ -29,8 +29,8 @@
 ;;     stack_limit = gv2
 ;;
 ;;                                 block0(v0: i64, v1: i64, v2: f32, v3: i32, v4: i32):
-;;                                     v52 = stack_addr.i64 ss0
-;;                                     store notrap aligned region7 v4, v52
+;;                                     v53 = stack_addr.i64 ss0
+;;                                     store notrap aligned region7 v4, v53
 ;; @002a                               v6 = iconst.i32 -1342177280
 ;; @002a                               v7 = load.i64 notrap aligned readonly can_move region2 v0+40
 ;; @002a                               v8 = load.i32 notrap aligned readonly can_move region3 v7
@@ -44,33 +44,34 @@
 ;; @002a                               v15 = iconst.i64 24
 ;; @002a                               v16 = iadd v14, v15  ; v15 = 24
 ;; @002a                               store user2 little region5 v2, v16
+;; @002a                               v19 = ireduce.i8 v3
 ;; @002a                               v17 = iconst.i64 28
 ;; @002a                               v18 = iadd v14, v17  ; v17 = 28
-;; @002a                               istore8 user2 little region5 v3, v18
-;;                                     v51 = load.i32 notrap aligned region7 v52
-;; @002a                               v21 = iconst.i32 1
-;; @002a                               v22 = band v51, v21  ; v21 = 1
-;; @002a                               v23 = iconst.i32 0
-;; @002a                               v24 = icmp eq v51, v23  ; v23 = 0
-;; @002a                               v25 = uextend.i32 v24
-;; @002a                               v26 = bor v22, v25
-;; @002a                               brif v26, block3, block2
+;; @002a                               store user2 little region5 v19, v18
+;;                                     v52 = load.i32 notrap aligned region7 v53
+;; @002a                               v22 = iconst.i32 1
+;; @002a                               v23 = band v52, v22  ; v22 = 1
+;; @002a                               v24 = iconst.i32 0
+;; @002a                               v25 = icmp eq v52, v24  ; v24 = 0
+;; @002a                               v26 = uextend.i32 v25
+;; @002a                               v27 = bor v23, v26
+;; @002a                               brif v27, block3, block2
 ;;
 ;;                                 block2:
-;; @002a                               v27 = uextend.i64 v51
-;; @002a                               v30 = iadd.i64 v12, v27
-;; @002a                               v31 = iconst.i64 8
-;; @002a                               v32 = iadd v30, v31  ; v31 = 8
-;; @002a                               v33 = load.i64 user2 region5 v32
-;; @002a                               v34 = iconst.i64 1
-;; @002a                               v35 = iadd v33, v34  ; v34 = 1
-;; @002a                               store user2 region5 v35, v32
+;; @002a                               v28 = uextend.i64 v52
+;; @002a                               v31 = iadd.i64 v12, v28
+;; @002a                               v32 = iconst.i64 8
+;; @002a                               v33 = iadd v31, v32  ; v32 = 8
+;; @002a                               v34 = load.i64 user2 region5 v33
+;; @002a                               v35 = iconst.i64 1
+;; @002a                               v36 = iadd v34, v35  ; v35 = 1
+;; @002a                               store user2 region5 v36, v33
 ;; @002a                               jump block3
 ;;
 ;;                                 block3:
-;; @002a                               v19 = iconst.i64 32
-;; @002a                               v20 = iadd.i64 v14, v19  ; v19 = 32
-;; @002a                               store.i32 user2 little region5 v51, v20
+;; @002a                               v20 = iconst.i64 32
+;; @002a                               v21 = iadd.i64 v14, v20  ; v20 = 32
+;; @002a                               store.i32 user2 little region5 v52, v21
 ;; @002d                               jump block1
 ;;
 ;;                                 block1:
diff --git a/tests/disas/gc/drc/struct-set.wat b/tests/disas/gc/drc/struct-set.wat
index 425f5c60898e..47850aa30b64 100644
--- a/tests/disas/gc/drc/struct-set.wat
+++ b/tests/disas/gc/drc/struct-set.wat
@@ -58,13 +58,14 @@
 ;;
 ;;                                 block0(v0: i64, v1: i64, v2: i32, v3: i32):
 ;; @003f                               trapz v2, user16
+;; @003f                               v10 = ireduce.i8 v3
 ;; @003f                               v5 = load.i64 notrap aligned readonly can_move region0 v0+8
 ;; @003f                               v6 = load.i64 notrap aligned readonly can_move region2 v5+32
 ;; @003f                               v4 = uextend.i64 v2
 ;; @003f                               v7 = iadd v6, v4
 ;; @003f                               v8 = iconst.i64 28
 ;; @003f                               v9 = iadd v7, v8  ; v8 = 28
-;; @003f                               istore8 user2 little region4 v3, v9
+;; @003f                               store user2 little region4 v10, v9
 ;; @0043                               jump block1
 ;;
 ;;                                 block1:
diff --git a/tests/disas/gc/issue-11753.wat b/tests/disas/gc/issue-11753.wat
index bfcf95eeb84e..63e271cbef48 100644
--- a/tests/disas/gc/issue-11753.wat
+++ b/tests/disas/gc/issue-11753.wat
@@ -29,7 +29,7 @@
 ;;       movq    0x18(%r10), %r10
 ;;       addq    $0x50, %r10
 ;;       cmpq    %rsp, %r10
-;;       ja      0x11a
+;;       ja      0x117
 ;;   19: subq    $0x40, %rsp
 ;;       movq    %rbx, 0x10(%rsp)
 ;;       movq    %r12, 0x18(%rsp)
@@ -42,7 +42,7 @@
 ;;       leaq    0x20(%rcx), %rdx
 ;;       movl    4(%rsi), %r8d
 ;;       cmpq    %r8, %rdx
-;;       ja      0xe6
+;;       ja      0xe3
 ;;   4f: movq    %rdi, 8(%rsp)
 ;;       leal    0x20(%rax), %edi
 ;;       movl    %edi, (%rsi)
@@ -56,8 +56,7 @@
 ;;       movl    (%r8), %r8d
 ;;       movl    %r8d, 4(%rdi, %rcx)
 ;;       ╰─╼ trap: GcHeapCorrupt
-;;       movl    $0x20, %r8d
-;;       movl    %r8d, 8(%rdi, %rcx)
+;;       movl    $0x20, 8(%rdi, %rcx)
 ;;       ╰─╼ trap: GcHeapCorrupt
 ;;       movl    %eax, (%rsp)
 ;;       movl    $0x2a, 0x10(%rsi)
@@ -68,12 +67,12 @@
 ;;       movq    8(%rsp), %rsi
 ;;       callq   *%rax
 ;;       ├─╼ exception frame offset: SP = FP - 0x40
-;;       ╰─╼ exception handler: default handler, context at [SP+0x8], handler=0xa6
+;;       ╰─╼ exception handler: default handler, context at [SP+0x8], handler=0xa3
 ;;       movl    (%rsp), %eax
 ;;       ╰─╼ stack_map: frame_size=64, frame_offsets=[0]
 ;;       testl   %eax, %eax
-;;       je      0x11c
-;;   b1: movq    8(%rsp), %r9
+;;       je      0x119
+;;   ae: movq    8(%rsp), %r9
 ;;       movq    8(%r9), %rcx
 ;;       movq    0x20(%rcx), %rcx
 ;;       movl    %eax, %eax
@@ -88,19 +87,19 @@
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   e6: movl    $0xb0000002, %esi
-;;   eb: movq    0x28(%rdi), %rax
-;;   ef: movq    %rdi, 8(%rsp)
-;;   f4: movl    (%rax), %edx
-;;   f6: movl    $0x20, %ecx
-;;   fb: movl    $0x10, %r8d
-;;  101: callq   0x286
-;;  106: movq    8(%rsp), %r9
-;;  10b: movq    8(%r9), %rcx
-;;  10f: movl    %eax, %esi
-;;  111: addq    0x20(%rcx), %rsi
-;;  115: jmp     0x88
-;;  11a: ud2
+;;   e3: movl    $0xb0000002, %esi
+;;   e8: movq    0x28(%rdi), %rax
+;;   ec: movq    %rdi, 8(%rsp)
+;;   f1: movl    (%rax), %edx
+;;   f3: movl    $0x20, %ecx
+;;   f8: movl    $0x10, %r8d
+;;   fe: callq   0x283
+;;  103: movq    8(%rsp), %r9
+;;  108: movq    8(%r9), %rcx
+;;  10c: movl    %eax, %esi
+;;  10e: addq    0x20(%rcx), %rsi
+;;  112: jmp     0x85
+;;  117: ud2
 ;;       ╰─╼ trap: Normal(StackOverflow)
-;;  11c: ud2
+;;  119: ud2
 ;;       ╰─╼ trap: Normal(NullReference)
diff --git a/tests/disas/gc/null/struct-new-default.wat b/tests/disas/gc/null/struct-new-default.wat
index d3b1a3612f97..3df850245e4a 100644
--- a/tests/disas/gc/null/struct-new-default.wat
+++ b/tests/disas/gc/null/struct-new-default.wat
@@ -31,10 +31,10 @@
 ;;                                 block0(v0: i64, v1: i64):
 ;; @0021                               v9 = load.i64 notrap aligned readonly can_move region2 v0+32
 ;; @0021                               v10 = load.i32 notrap aligned region3 v9
-;;                                     v42 = iconst.i32 7
-;; @0021                               v13 = uadd_overflow_trap v10, v42, user18  ; v42 = 7
-;;                                     v48 = iconst.i32 -8
-;; @0021                               v15 = band v13, v48  ; v48 = -8
+;;                                     v43 = iconst.i32 7
+;; @0021                               v13 = uadd_overflow_trap v10, v43, user18  ; v43 = 7
+;;                                     v49 = iconst.i32 -8
+;; @0021                               v15 = band v13, v49  ; v49 = -8
 ;; @0021                               v5 = iconst.i32 24
 ;; @0021                               v16 = uadd_overflow_trap v15, v5, user18  ; v5 = 24
 ;; @0021                               v18 = load.i64 notrap aligned readonly can_move region0 v0+8
@@ -44,12 +44,12 @@
 ;; @0021                               brif v20, block2, block3
 ;;
 ;;                                 block2:
-;;                                     v49 = iconst.i32 -1342177256
+;;                                     v50 = iconst.i32 -1342177256
 ;; @0021                               v24 = load.i64 notrap aligned readonly can_move region5 v18+32
-;;                                     v55 = band.i32 v13, v48  ; v48 = -8
-;;                                     v56 = uextend.i64 v55
-;; @0021                               v26 = iadd v24, v56
-;; @0021                               store user2 region8 v49, v26  ; v49 = -1342177256
+;;                                     v57 = band.i32 v13, v49  ; v49 = -8
+;;                                     v58 = uextend.i64 v57
+;; @0021                               v26 = iadd v24, v58
+;; @0021                               store user2 region8 v50, v26  ; v50 = -1342177256
 ;; @0021                               v29 = load.i64 notrap aligned readonly can_move region6 v0+40
 ;; @0021                               v30 = load.i32 notrap aligned readonly can_move region7 v29
 ;; @0021                               store user2 region8 v30, v26+4
@@ -58,13 +58,14 @@
 ;; @0021                               v31 = iconst.i64 8
 ;; @0021                               v32 = iadd v26, v31  ; v31 = 8
 ;; @0021                               store user2 little region8 v2, v32  ; v2 = 0.0
-;; @0021                               v3 = iconst.i32 0
+;;                                     v56 = iconst.i8 0
 ;; @0021                               v33 = iconst.i64 12
 ;; @0021                               v34 = iadd v26, v33  ; v33 = 12
-;; @0021                               istore8 user2 little region8 v3, v34  ; v3 = 0
-;; @0021                               v35 = iconst.i64 16
-;; @0021                               v36 = iadd v26, v35  ; v35 = 16
-;; @0021                               store user2 little region8 v3, v36  ; v3 = 0
+;; @0021                               store user2 little region8 v56, v34  ; v56 = 0
+;; @0021                               v3 = iconst.i32 0
+;; @0021                               v36 = iconst.i64 16
+;; @0021                               v37 = iadd v26, v36  ; v36 = 16
+;; @0021                               store user2 little region8 v3, v37  ; v3 = 0
 ;; @0024                               jump block1
 ;;
 ;;                                 block3 cold:
@@ -73,6 +74,6 @@
 ;; @0021                               jump block2
 ;;
 ;;                                 block1:
-;;                                     v57 = band.i32 v13, v48  ; v48 = -8
-;; @0024                               return v57
+;;                                     v59 = band.i32 v13, v49  ; v49 = -8
+;; @0024                               return v59
 ;; }
diff --git a/tests/disas/gc/null/struct-new.wat b/tests/disas/gc/null/struct-new.wat
index 6ea9bb70e93b..67a08b56bceb 100644
--- a/tests/disas/gc/null/struct-new.wat
+++ b/tests/disas/gc/null/struct-new.wat
@@ -31,14 +31,14 @@
 ;;     stack_limit = gv2
 ;;
 ;;                                 block0(v0: i64, v1: i64, v2: f32, v3: i32, v4: i32):
-;;                                     v39 = stack_addr.i64 ss0
-;;                                     store notrap aligned region9 v4, v39
+;;                                     v40 = stack_addr.i64 ss0
+;;                                     store notrap aligned region9 v4, v40
 ;; @002a                               v9 = load.i64 notrap aligned readonly can_move region2 v0+32
 ;; @002a                               v10 = load.i32 notrap aligned region3 v9
-;;                                     v46 = iconst.i32 7
-;; @002a                               v13 = uadd_overflow_trap v10, v46, user18  ; v46 = 7
-;;                                     v52 = iconst.i32 -8
-;; @002a                               v15 = band v13, v52  ; v52 = -8
+;;                                     v47 = iconst.i32 7
+;; @002a                               v13 = uadd_overflow_trap v10, v47, user18  ; v47 = 7
+;;                                     v53 = iconst.i32 -8
+;; @002a                               v15 = band v13, v53  ; v53 = -8
 ;; @002a                               v5 = iconst.i32 24
 ;; @002a                               v16 = uadd_overflow_trap v15, v5, user18  ; v5 = 24
 ;; @002a                               v18 = load.i64 notrap aligned readonly can_move region0 v0+8
@@ -48,12 +48,12 @@
 ;; @002a                               brif v20, block2, block3
 ;;
 ;;                                 block2:
-;;                                     v53 = iconst.i32 -1342177256
+;;                                     v54 = iconst.i32 -1342177256
 ;; @002a                               v24 = load.i64 notrap aligned readonly can_move region5 v18+32
-;;                                     v59 = band.i32 v13, v52  ; v52 = -8
-;;                                     v60 = uextend.i64 v59
-;; @002a                               v26 = iadd v24, v60
-;; @002a                               store user2 region8 v53, v26  ; v53 = -1342177256
+;;                                     v60 = band.i32 v13, v53  ; v53 = -8
+;;                                     v61 = uextend.i64 v60
+;; @002a                               v26 = iadd v24, v61
+;; @002a                               store user2 region8 v54, v26  ; v54 = -1342177256
 ;; @002a                               v29 = load.i64 notrap aligned readonly can_move region6 v0+40
 ;; @002a                               v30 = load.i32 notrap aligned readonly can_move region7 v29
 ;; @002a                               store user2 region8 v30, v26+4
@@ -61,13 +61,14 @@
 ;; @002a                               v31 = iconst.i64 8
 ;; @002a                               v32 = iadd v26, v31  ; v31 = 8
 ;; @002a                               store.f32 user2 little region8 v2, v32
+;; @002a                               v35 = ireduce.i8 v3
 ;; @002a                               v33 = iconst.i64 12
 ;; @002a                               v34 = iadd v26, v33  ; v33 = 12
-;; @002a                               istore8.i32 user2 little region8 v3, v34
-;;                                     v38 = load.i32 notrap aligned region9 v39
-;; @002a                               v35 = iconst.i64 16
-;; @002a                               v36 = iadd v26, v35  ; v35 = 16
-;; @002a                               store user2 little region8 v38, v36
+;; @002a                               store user2 little region8 v35, v34
+;;                                     v39 = load.i32 notrap aligned region9 v40
+;; @002a                               v36 = iconst.i64 16
+;; @002a                               v37 = iadd v26, v36  ; v36 = 16
+;; @002a                               store user2 little region8 v39, v37
 ;; @002d                               jump block1
 ;;
 ;;                                 block3 cold:
@@ -76,6 +77,6 @@
 ;; @002a                               jump block2
 ;;
 ;;                                 block1:
-;;                                     v61 = band.i32 v13, v52  ; v52 = -8
-;; @002d                               return v61
+;;                                     v62 = band.i32 v13, v53  ; v53 = -8
+;; @002d                               return v62
 ;; }
diff --git a/tests/disas/gc/null/struct-set.wat b/tests/disas/gc/null/struct-set.wat
index 2731a51afa76..97db4172815c 100644
--- a/tests/disas/gc/null/struct-set.wat
+++ b/tests/disas/gc/null/struct-set.wat
@@ -58,13 +58,14 @@
 ;;
 ;;                                 block0(v0: i64, v1: i64, v2: i32, v3: i32):
 ;; @003f                               trapz v2, user16
+;; @003f                               v10 = ireduce.i8 v3
 ;; @003f                               v5 = load.i64 notrap aligned readonly can_move region0 v0+8
 ;; @003f                               v6 = load.i64 notrap aligned readonly can_move region2 v5+32
 ;; @003f                               v4 = uextend.i64 v2
 ;; @003f                               v7 = iadd v6, v4
 ;; @003f                               v8 = iconst.i64 12
 ;; @003f                               v9 = iadd v7, v8  ; v8 = 12
-;; @003f                               istore8 user2 little region4 v3, v9
+;; @003f                               store user2 little region4 v10, v9
 ;; @0043                               jump block1
 ;;
 ;;                                 block1:
diff --git a/tests/disas/gc/struct-new-default.wat b/tests/disas/gc/struct-new-default.wat
index da7731d5446e..c429ab02a44b 100644
--- a/tests/disas/gc/struct-new-default.wat
+++ b/tests/disas/gc/struct-new-default.wat
@@ -35,26 +35,25 @@
 ;; @0023                               v8 = load.i32 notrap aligned region3 v7
 ;; @0023                               v9 = load.i32 notrap aligned region4 v7+4
 ;; @0023                               v15 = uextend.i64 v8
-;;                                     v46 = iconst.i64 48
-;; @0023                               v16 = iadd v15, v46  ; v46 = 48
+;;                                     v48 = iconst.i64 48
+;; @0023                               v16 = iadd v15, v48  ; v48 = 48
 ;; @0023                               v17 = uextend.i64 v9
 ;; @0023                               v18 = icmp ule v16, v17
 ;; @0023                               brif v18, block2, block3
 ;;
 ;;                                 block2:
-;;                                     v62 = iconst.i32 48
-;;                                     v60 = iadd.i32 v8, v62  ; v62 = 48
-;; @0023                               store notrap aligned region3 v60, v7
-;;                                     v63 = iconst.i32 -1342177246
-;;                                     v64 = load.i64 notrap aligned readonly can_move region0 v0+8
-;;                                     v65 = load.i64 notrap aligned readonly can_move region7 v64+32
-;; @0023                               v32 = iadd v65, v15
-;; @0023                               store user2 region8 v63, v32  ; v63 = -1342177246
-;;                                     v66 = load.i64 notrap aligned readonly can_move region5 v0+40
-;;                                     v67 = load.i32 notrap aligned readonly can_move region6 v66
-;; @0023                               store user2 region8 v67, v32+4
-;;                                     v68 = iconst.i64 48
-;; @0023                               istore32 user2 region8 v68, v32+8  ; v68 = 48
+;;                                     v65 = iconst.i32 48
+;;                                     v62 = iadd.i32 v8, v65  ; v65 = 48
+;; @0023                               store notrap aligned region3 v62, v7
+;;                                     v66 = iconst.i32 -1342177246
+;;                                     v67 = load.i64 notrap aligned readonly can_move region0 v0+8
+;;                                     v68 = load.i64 notrap aligned readonly can_move region7 v67+32
+;; @0023                               v32 = iadd v68, v15
+;; @0023                               store user2 region8 v66, v32  ; v66 = -1342177246
+;;                                     v69 = load.i64 notrap aligned readonly can_move region5 v0+40
+;;                                     v70 = load.i32 notrap aligned readonly can_move region6 v69
+;; @0023                               store user2 region8 v70, v32+4
+;; @0023                               store user2 region8 v65, v32+8  ; v65 = 48
 ;; @0023                               jump block4(v8, v32)
 ;;
 ;;                                 block3 cold:
@@ -70,24 +69,25 @@
 ;; @0023                               v27 = iadd v25, v26
 ;; @0023                               jump block4(v23, v27)
 ;;
-;;                                 block4(v36: i32, v37: i64):
+;;                                 block4(v37: i32, v38: i64):
 ;; @0023                               v2 = f32const 0.0
-;; @0023                               v38 = iconst.i64 16
-;; @0023                               v39 = iadd v37, v38  ; v38 = 16
-;; @0023                               store user2 little region8 v2, v39  ; v2 = 0.0
+;; @0023                               v39 = iconst.i64 16
+;; @0023                               v40 = iadd v38, v39  ; v39 = 16
+;; @0023                               store user2 little region8 v2, v40  ; v2 = 0.0
+;;                                     v64 = iconst.i8 0
+;; @0023                               v41 = iconst.i64 20
+;; @0023                               v42 = iadd v38, v41  ; v41 = 20
+;; @0023                               store user2 little region8 v64, v42  ; v64 = 0
 ;; @0023                               v3 = iconst.i32 0
-;; @0023                               v40 = iconst.i64 20
-;; @0023                               v41 = iadd v37, v40  ; v40 = 20
-;; @0023                               istore8 user2 little region8 v3, v41  ; v3 = 0
-;; @0023                               v42 = iconst.i64 24
-;; @0023                               v43 = iadd v37, v42  ; v42 = 24
-;; @0023                               store user2 little region8 v3, v43  ; v3 = 0
+;; @0023                               v44 = iconst.i64 24
+;; @0023                               v45 = iadd v38, v44  ; v44 = 24
+;; @0023                               store user2 little region8 v3, v45  ; v3 = 0
 ;; @0023                               v5 = vconst.i8x16 const0
-;; @0023                               v44 = iconst.i64 32
-;; @0023                               v45 = iadd v37, v44  ; v44 = 32
-;; @0023                               store user2 little region8 v5, v45  ; v5 = const0
+;; @0023                               v46 = iconst.i64 32
+;; @0023                               v47 = iadd v38, v46  ; v46 = 32
+;; @0023                               store user2 little region8 v5, v47  ; v5 = const0
 ;; @0026                               jump block1
 ;;
 ;;                                 block1:
-;; @0026                               return v36
+;; @0026                               return v37
 ;; }
diff --git a/tests/disas/gc/struct-new-stack-map.wat b/tests/disas/gc/struct-new-stack-map.wat
index d5806d55e7e5..38066430b38a 100644
--- a/tests/disas/gc/struct-new-stack-map.wat
+++ b/tests/disas/gc/struct-new-stack-map.wat
@@ -18,7 +18,7 @@
 ;;       movq    0x18(%r10), %r10
 ;;       addq    $0x40, %r10
 ;;       cmpq    %rsp, %r10
-;;       ja      0xd7
+;;       ja      0xd6
 ;;   19: subq    $0x30, %rsp
 ;;       movq    %rbx, 0x20(%rsp)
 ;;       movq    %r12, 0x28(%rsp)
@@ -31,7 +31,7 @@
 ;;       leaq    0x20(%rcx), %rsi
 ;;       movl    4(%rdx), %r8d
 ;;       cmpq    %r8, %rsi
-;;       ja      0xa4
+;;       ja      0xa3
 ;;   4c: movq    %rdi, %rbx
 ;;       leal    0x20(%rax), %esi
 ;;       movl    %esi, (%rdx)
@@ -42,8 +42,7 @@
 ;;       movq    0x28(%rbx), %rdi
 ;;       movl    (%rdi), %edi
 ;;       movl    %edi, 4(%rsi, %rcx)
-;;       movl    $0x20, %edi
-;;       movl    %edi, 8(%rsi, %rcx)
+;;       movl    $0x20, 8(%rsi, %rcx)
 ;;       movdqu  8(%rsp), %xmm0
 ;;       movss   %xmm0, 0x10(%rdx)
 ;;       movq    %r12, %rcx
@@ -56,17 +55,17 @@
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   a4: movl    $0xb0000022, %esi
-;;   a9: movq    0x28(%rdi), %rax
-;;   ad: movq    %rdi, %rbx
-;;   b0: movl    (%rax), %edx
-;;   b2: movl    $0x20, %ecx
-;;   b7: movl    $0x10, %r8d
-;;   bd: callq   0x14d
-;;   c2: movq    8(%rbx), %rcx
+;;   a3: movl    $0xb0000022, %esi
+;;   a8: movq    0x28(%rdi), %rax
+;;   ac: movq    %rdi, %rbx
+;;   af: movl    (%rax), %edx
+;;   b1: movl    $0x20, %ecx
+;;   b6: movl    $0x10, %r8d
+;;   bc: callq   0x14c
+;;   c1: movq    8(%rbx), %rcx
 ;;       ╰─╼ stack_map: frame_size=48, frame_offsets=[0]
-;;   c6: movl    %eax, %edx
-;;   c8: addq    0x20(%rcx), %rdx
-;;   cc: movdqu  8(%rsp), %xmm0
-;;   d2: jmp     0x80
-;;   d7: ud2
+;;   c5: movl    %eax, %edx
+;;   c7: addq    0x20(%rcx), %rdx
+;;   cb: movdqu  8(%rsp), %xmm0
+;;   d1: jmp     0x7f
+;;   d6: ud2
diff --git a/tests/disas/gc/struct-new.wat b/tests/disas/gc/struct-new.wat
index 13979f7f80ba..a95ba1d0e531 100644
--- a/tests/disas/gc/struct-new.wat
+++ b/tests/disas/gc/struct-new.wat
@@ -31,32 +31,31 @@
 ;;     stack_limit = gv2
 ;;
 ;;                                 block0(v0: i64, v1: i64, v2: f32, v3: i32, v4: i32):
-;;                                     v45 = stack_addr.i64 ss0
-;;                                     store notrap aligned region9 v4, v45
+;;                                     v47 = stack_addr.i64 ss0
+;;                                     store notrap aligned region9 v4, v47
 ;; @002a                               v6 = load.i64 notrap aligned readonly can_move region2 v0+32
 ;; @002a                               v7 = load.i32 notrap aligned region3 v6
 ;; @002a                               v8 = load.i32 notrap aligned region4 v6+4
 ;; @002a                               v14 = uextend.i64 v7
-;;                                     v46 = iconst.i64 32
-;; @002a                               v15 = iadd v14, v46  ; v46 = 32
+;;                                     v48 = iconst.i64 32
+;; @002a                               v15 = iadd v14, v48  ; v48 = 32
 ;; @002a                               v16 = uextend.i64 v8
 ;; @002a                               v17 = icmp ule v15, v16
 ;; @002a                               brif v17, block2, block3
 ;;
 ;;                                 block2:
-;;                                     v62 = iconst.i32 32
-;;                                     v60 = iadd.i32 v7, v62  ; v62 = 32
-;; @002a                               store notrap aligned region3 v60, v6
-;;                                     v63 = iconst.i32 -1342177246
-;;                                     v64 = load.i64 notrap aligned readonly can_move region0 v0+8
-;;                                     v65 = load.i64 notrap aligned readonly can_move region7 v64+32
-;; @002a                               v31 = iadd v65, v14
-;; @002a                               store user2 region8 v63, v31  ; v63 = -1342177246
-;;                                     v66 = load.i64 notrap aligned readonly can_move region5 v0+40
-;;                                     v67 = load.i32 notrap aligned readonly can_move region6 v66
-;; @002a                               store user2 region8 v67, v31+4
-;;                                     v68 = iconst.i64 32
-;; @002a                               istore32 user2 region8 v68, v31+8  ; v68 = 32
+;;                                     v64 = iconst.i32 32
+;;                                     v62 = iadd.i32 v7, v64  ; v64 = 32
+;; @002a                               store notrap aligned region3 v62, v6
+;;                                     v65 = iconst.i32 -1342177246
+;;                                     v66 = load.i64 notrap aligned readonly can_move region0 v0+8
+;;                                     v67 = load.i64 notrap aligned readonly can_move region7 v66+32
+;; @002a                               v31 = iadd v67, v14
+;; @002a                               store user2 region8 v65, v31  ; v65 = -1342177246
+;;                                     v68 = load.i64 notrap aligned readonly can_move region5 v0+40
+;;                                     v69 = load.i32 notrap aligned readonly can_move region6 v68
+;; @002a                               store user2 region8 v69, v31+4
+;; @002a                               store user2 region8 v64, v31+8  ; v64 = 32
 ;; @002a                               jump block4(v7, v31)
 ;;
 ;;                                 block3 cold:
@@ -72,19 +71,20 @@
 ;; @002a                               v26 = iadd v24, v25
 ;; @002a                               jump block4(v22, v26)
 ;;
-;;                                 block4(v35: i32, v36: i64):
-;; @002a                               v37 = iconst.i64 16
-;; @002a                               v38 = iadd v36, v37  ; v37 = 16
-;; @002a                               store.f32 user2 little region8 v2, v38
-;; @002a                               v39 = iconst.i64 20
-;; @002a                               v40 = iadd v36, v39  ; v39 = 20
-;; @002a                               istore8.i32 user2 little region8 v3, v40
-;;                                     v44 = load.i32 notrap aligned region9 v45
-;; @002a                               v41 = iconst.i64 24
-;; @002a                               v42 = iadd v36, v41  ; v41 = 24
-;; @002a                               store user2 little region8 v44, v42
+;;                                 block4(v36: i32, v37: i64):
+;; @002a                               v38 = iconst.i64 16
+;; @002a                               v39 = iadd v37, v38  ; v38 = 16
+;; @002a                               store.f32 user2 little region8 v2, v39
+;; @002a                               v42 = ireduce.i8 v3
+;; @002a                               v40 = iconst.i64 20
+;; @002a                               v41 = iadd v37, v40  ; v40 = 20
+;; @002a                               store user2 little region8 v42, v41
+;;                                     v46 = load.i32 notrap aligned region9 v47
+;; @002a                               v43 = iconst.i64 24
+;; @002a                               v44 = iadd v37, v43  ; v43 = 24
+;; @002a                               store user2 little region8 v46, v44
 ;; @002d                               jump block1
 ;;
 ;;                                 block1:
-;; @002d                               return v35
+;; @002d                               return v36
 ;; }
diff --git a/tests/disas/i32-load16-s.wat b/tests/disas/i32-load16-s.wat
index e00f4e0c5983..68aa7aa6313e 100644
--- a/tests/disas/i32-load16-s.wat
+++ b/tests/disas/i32-load16-s.wat
@@ -23,9 +23,10 @@
 ;; @0032                               v3 = uextend.i64 v2
 ;; @0032                               v4 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0032                               v5 = iadd v4, v3
-;; @0032                               v6 = sload16.i32 little region4 v5
+;; @0032                               v6 = load.i16 little region4 v5
+;; @0032                               v7 = sextend.i32 v6
 ;; @0035                               jump block1
 ;;
 ;;                                 block1:
-;; @0035                               return v6
+;; @0035                               return v7
 ;; }
diff --git a/tests/disas/i32-load16-u.wat b/tests/disas/i32-load16-u.wat
index f0dffb1e7d29..3251718e2326 100644
--- a/tests/disas/i32-load16-u.wat
+++ b/tests/disas/i32-load16-u.wat
@@ -23,9 +23,10 @@
 ;; @0032                               v3 = uextend.i64 v2
 ;; @0032                               v4 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0032                               v5 = iadd v4, v3
-;; @0032                               v6 = uload16.i32 little region4 v5
+;; @0032                               v6 = load.i16 little region4 v5
+;; @0032                               v7 = uextend.i32 v6
 ;; @0035                               jump block1
 ;;
 ;;                                 block1:
-;; @0035                               return v6
+;; @0035                               return v7
 ;; }
diff --git a/tests/disas/i32-load8-s.wat b/tests/disas/i32-load8-s.wat
index 28849cd15455..483fd857e0ab 100644
--- a/tests/disas/i32-load8-s.wat
+++ b/tests/disas/i32-load8-s.wat
@@ -23,9 +23,10 @@
 ;; @0031                               v3 = uextend.i64 v2
 ;; @0031                               v4 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0031                               v5 = iadd v4, v3
-;; @0031                               v6 = sload8.i32 little region4 v5
+;; @0031                               v6 = load.i8 little region4 v5
+;; @0031                               v7 = sextend.i32 v6
 ;; @0034                               jump block1
 ;;
 ;;                                 block1:
-;; @0034                               return v6
+;; @0034                               return v7
 ;; }
diff --git a/tests/disas/i32-load8-u.wat b/tests/disas/i32-load8-u.wat
index 4764d4ddcf9a..28546acdc836 100644
--- a/tests/disas/i32-load8-u.wat
+++ b/tests/disas/i32-load8-u.wat
@@ -23,9 +23,10 @@
 ;; @0031                               v3 = uextend.i64 v2
 ;; @0031                               v4 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0031                               v5 = iadd v4, v3
-;; @0031                               v6 = uload8.i32 little region4 v5
+;; @0031                               v6 = load.i8 little region4 v5
+;; @0031                               v7 = uextend.i32 v6
 ;; @0034                               jump block1
 ;;
 ;;                                 block1:
-;; @0034                               return v6
+;; @0034                               return v7
 ;; }
diff --git a/tests/disas/i32-store16.wat b/tests/disas/i32-store16.wat
index 6c78b6ceae75..31358801e6ab 100644
--- a/tests/disas/i32-store16.wat
+++ b/tests/disas/i32-store16.wat
@@ -24,7 +24,8 @@
 ;; @0033                               v4 = uextend.i64 v2
 ;; @0033                               v5 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0033                               v6 = iadd v5, v4
-;; @0033                               istore16 little region4 v3, v6
+;; @0033                               v7 = ireduce.i16 v3
+;; @0033                               store little region4 v7, v6
 ;; @0036                               jump block1
 ;;
 ;;                                 block1:
diff --git a/tests/disas/i32-store8.wat b/tests/disas/i32-store8.wat
index 52aac2f740cd..54ded0d2b563 100644
--- a/tests/disas/i32-store8.wat
+++ b/tests/disas/i32-store8.wat
@@ -24,7 +24,8 @@
 ;; @0032                               v4 = uextend.i64 v2
 ;; @0032                               v5 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0032                               v6 = iadd v5, v4
-;; @0032                               istore8 little region4 v3, v6
+;; @0032                               v7 = ireduce.i8 v3
+;; @0032                               store little region4 v7, v6
 ;; @0035                               jump block1
 ;;
 ;;                                 block1:
diff --git a/tests/disas/i64-load16-s.wat b/tests/disas/i64-load16-s.wat
index 2a8ce1316837..3b30db8c7a66 100644
--- a/tests/disas/i64-load16-s.wat
+++ b/tests/disas/i64-load16-s.wat
@@ -23,9 +23,10 @@
 ;; @0032                               v3 = uextend.i64 v2
 ;; @0032                               v4 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0032                               v5 = iadd v4, v3
-;; @0032                               v6 = sload16.i64 little region4 v5
+;; @0032                               v6 = load.i16 little region4 v5
+;; @0032                               v7 = sextend.i64 v6
 ;; @0035                               jump block1
 ;;
 ;;                                 block1:
-;; @0035                               return v6
+;; @0035                               return v7
 ;; }
diff --git a/tests/disas/i64-load16-u.wat b/tests/disas/i64-load16-u.wat
index 9170210cbd05..6f092b2c580a 100644
--- a/tests/disas/i64-load16-u.wat
+++ b/tests/disas/i64-load16-u.wat
@@ -23,9 +23,10 @@
 ;; @0032                               v3 = uextend.i64 v2
 ;; @0032                               v4 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0032                               v5 = iadd v4, v3
-;; @0032                               v6 = uload16.i64 little region4 v5
+;; @0032                               v6 = load.i16 little region4 v5
+;; @0032                               v7 = uextend.i64 v6
 ;; @0035                               jump block1
 ;;
 ;;                                 block1:
-;; @0035                               return v6
+;; @0035                               return v7
 ;; }
diff --git a/tests/disas/i64-load8-s.wat b/tests/disas/i64-load8-s.wat
index 9027f8d02c26..a51db5a6f47a 100644
--- a/tests/disas/i64-load8-s.wat
+++ b/tests/disas/i64-load8-s.wat
@@ -23,9 +23,10 @@
 ;; @0031                               v3 = uextend.i64 v2
 ;; @0031                               v4 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0031                               v5 = iadd v4, v3
-;; @0031                               v6 = sload8.i64 little region4 v5
+;; @0031                               v6 = load.i8 little region4 v5
+;; @0031                               v7 = sextend.i64 v6
 ;; @0034                               jump block1
 ;;
 ;;                                 block1:
-;; @0034                               return v6
+;; @0034                               return v7
 ;; }
diff --git a/tests/disas/i64-load8-u.wat b/tests/disas/i64-load8-u.wat
index 3d028d97d719..110e0dd0f4d1 100644
--- a/tests/disas/i64-load8-u.wat
+++ b/tests/disas/i64-load8-u.wat
@@ -23,9 +23,10 @@
 ;; @0031                               v3 = uextend.i64 v2
 ;; @0031                               v4 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0031                               v5 = iadd v4, v3
-;; @0031                               v6 = uload8.i64 little region4 v5
+;; @0031                               v6 = load.i8 little region4 v5
+;; @0031                               v7 = uextend.i64 v6
 ;; @0034                               jump block1
 ;;
 ;;                                 block1:
-;; @0034                               return v6
+;; @0034                               return v7
 ;; }
diff --git a/tests/disas/i64-store16.wat b/tests/disas/i64-store16.wat
index bc655f5c0e24..1dfb77efd7a0 100644
--- a/tests/disas/i64-store16.wat
+++ b/tests/disas/i64-store16.wat
@@ -24,7 +24,8 @@
 ;; @0033                               v4 = uextend.i64 v2
 ;; @0033                               v5 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0033                               v6 = iadd v5, v4
-;; @0033                               istore16 little region4 v3, v6
+;; @0033                               v7 = ireduce.i16 v3
+;; @0033                               store little region4 v7, v6
 ;; @0036                               jump block1
 ;;
 ;;                                 block1:
diff --git a/tests/disas/i64-store32.wat b/tests/disas/i64-store32.wat
index 35b994316519..c2c65a64267f 100644
--- a/tests/disas/i64-store32.wat
+++ b/tests/disas/i64-store32.wat
@@ -24,7 +24,8 @@
 ;; @0033                               v4 = uextend.i64 v2
 ;; @0033                               v5 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0033                               v6 = iadd v5, v4
-;; @0033                               istore32 little region4 v3, v6
+;; @0033                               v7 = ireduce.i32 v3
+;; @0033                               store little region4 v7, v6
 ;; @0036                               jump block1
 ;;
 ;;                                 block1:
diff --git a/tests/disas/i64-store8.wat b/tests/disas/i64-store8.wat
index c6f784379bd8..d5a396ef3b03 100644
--- a/tests/disas/i64-store8.wat
+++ b/tests/disas/i64-store8.wat
@@ -24,7 +24,8 @@
 ;; @0032                               v4 = uextend.i64 v2
 ;; @0032                               v5 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0032                               v6 = iadd v5, v4
-;; @0032                               istore8 little region4 v3, v6
+;; @0032                               v7 = ireduce.i8 v3
+;; @0032                               store little region4 v7, v6
 ;; @0035                               jump block1
 ;;
 ;;                                 block1:
diff --git a/tests/disas/if-unreachable-else-params-2.wat b/tests/disas/if-unreachable-else-params-2.wat
index 85dd980ea358..5647772132f4 100644
--- a/tests/disas/if-unreachable-else-params-2.wat
+++ b/tests/disas/if-unreachable-else-params-2.wat
@@ -38,7 +38,8 @@
 ;; @0058                               v5 = uextend.i64 v2
 ;; @0058                               v6 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0058                               v7 = iadd v6, v5
-;; @0058                               v8 = sload16.i64 little region4 v7
+;; @0058                               v8 = load.i16 little region4 v7
+;; @0058                               v9 = sextend.i64 v8
 ;; @005c                               jump block3
 ;;
 ;;                                 block4:
diff --git a/tests/disas/if-unreachable-else-params.wat b/tests/disas/if-unreachable-else-params.wat
index 51e7fdc63cee..bc9501a73337 100644
--- a/tests/disas/if-unreachable-else-params.wat
+++ b/tests/disas/if-unreachable-else-params.wat
@@ -64,10 +64,11 @@
 ;; @004b                               v6 = uextend.i64 v3  ; v3 = 35
 ;; @004b                               v7 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @004b                               v8 = iadd v7, v6
-;; @004b                               v9 = sload16.i64 little region4 v8
+;; @004b                               v9 = load.i16 little region4 v8
+;; @004b                               v10 = sextend.i64 v9
 ;; @004e                               trap user12
 ;;
 ;;                                 block6:
-;; @005d                               v10 = popcnt.i32 v3  ; v3 = 35
+;; @005d                               v11 = popcnt.i32 v3  ; v3 = 35
 ;; @0060                               return
 ;; }
diff --git a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
index 59ca62ae2059..7e780fc8312e 100644
--- a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
@@ -34,12 +34,13 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       ldr     x6, [x2, #0x40]
-;;       mov     w7, w4
-;;       cmp     x7, x6
-;;       b.hs    #0x68
-;;   58: ldr     x8, [x2, #0x38]
-;;       ldrb    w2, [x8, w4, uxtw]
+;;       ldr     x7, [x2, #0x40]
+;;       mov     w8, w4
+;;       cmp     x8, x7
+;;       b.hs    #0x6c
+;;   58: ldr     x9, [x2, #0x38]
+;;       ldrb    w9, [x9, w4, uxtw]
+;;       uxtb    w2, w9
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
-;;   68: udf     #0xc11f
+;;   6c: udf     #0xc11f
diff --git a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
index be4494771df2..2e8999f9c642 100644
--- a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -37,15 +37,16 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       ldr     x9, [x2, #0x40]
-;;       mov     w10, w4
-;;       mov     x11, #0x1001
-;;       sub     x9, x9, x11
-;;       cmp     x10, x9
-;;       b.hi    #0x74
-;;   60: ldr     x11, [x2, #0x38]
-;;       add     x10, x11, #1, lsl #12
-;;       ldrb    w2, [x10, w4, uxtw]
+;;       ldr     x10, [x2, #0x40]
+;;       mov     w11, w4
+;;       mov     x12, #0x1001
+;;       sub     x10, x10, x12
+;;       cmp     x11, x10
+;;       b.hi    #0x78
+;;   60: ldr     x12, [x2, #0x38]
+;;       add     x11, x12, #1, lsl #12
+;;       ldrb    w13, [x11, w4, uxtw]
+;;       uxtb    w2, w13
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
-;;   74: udf     #0xc11f
+;;   78: udf     #0xc11f
diff --git a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index f9b42bf4545b..6732c7ff8394 100644
--- a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -40,18 +40,19 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       mov     w10, w4
-;;       mov     w11, #-0xffff
-;;       adds    x10, x10, x11
-;;       b.hs    #0x9c
-;;   78: ldr     x11, [x2, #0x40]
-;;       cmp     x10, x11
-;;       b.hi    #0xa0
-;;   84: ldr     x13, [x2, #0x38]
-;;       add     x13, x13, w4, uxtw
-;;       mov     x14, #0xffff0000
-;;       ldrb    w2, [x13, x14]
+;;       mov     w11, w4
+;;       mov     w12, #-0xffff
+;;       adds    x11, x11, x12
+;;       b.hs    #0xa0
+;;   78: ldr     x12, [x2, #0x40]
+;;       cmp     x11, x12
+;;       b.hi    #0xa4
+;;   84: ldr     x14, [x2, #0x38]
+;;       add     x14, x14, w4, uxtw
+;;       mov     x15, #0xffff0000
+;;       ldrb    w14, [x14, x15]
+;;       uxtb    w2, w14
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
-;;   9c: udf     #0xc11f
 ;;   a0: udf     #0xc11f
+;;   a4: udf     #0xc11f
diff --git a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 17f3f1c07470..2d02e46daaef 100644
--- a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -35,13 +35,14 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       ldr     x9, [x2, #0x40]
-;;       ldr     x10, [x2, #0x38]
-;;       mov     w11, w4
-;;       mov     x12, #0
-;;       add     x10, x10, w4, uxtw
-;;       cmp     x11, x9
-;;       csel    x10, x12, x10, hs
-;;       ldrb    w2, [x10]
+;;       ldr     x10, [x2, #0x40]
+;;       ldr     x11, [x2, #0x38]
+;;       mov     w12, w4
+;;       mov     x13, #0
+;;       add     x11, x11, w4, uxtw
+;;       cmp     x12, x10
+;;       csel    x11, x13, x11, hs
+;;       ldrb    w11, [x11]
+;;       uxtb    w2, w11
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index f141fa08f4bf..f40aac455b9b 100644
--- a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -38,16 +38,17 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       ldr     x14, [x2, #0x40]
-;;       ldr     x13, [x2, #0x38]
-;;       mov     w12, w4
-;;       mov     x15, #0x1001
-;;       sub     x14, x14, x15
-;;       mov     x15, #0
-;;       add     x13, x13, w4, uxtw
-;;       add     x13, x13, #1, lsl #12
-;;       cmp     x12, x14
-;;       csel    x13, x15, x13, hi
-;;       ldrb    w2, [x13]
+;;       ldr     x15, [x2, #0x40]
+;;       ldr     x14, [x2, #0x38]
+;;       mov     w13, w4
+;;       mov     x0, #0x1001
+;;       sub     x15, x15, x0
+;;       mov     x0, #0
+;;       add     x14, x14, w4, uxtw
+;;       add     x14, x14, #1, lsl #12
+;;       cmp     x13, x15
+;;       csel    x14, x0, x14, hi
+;;       ldrb    w14, [x14]
+;;       uxtb    w2, w14
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 65b4b09c8bb7..c59b3dc1686c 100644
--- a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -41,19 +41,20 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       mov     w13, w4
-;;       mov     w14, #-0xffff
-;;       adds    x13, x13, x14
-;;       b.hs    #0xa4
-;;   78: ldr     x14, [x2, #0x40]
-;;       ldr     x0, [x2, #0x38]
-;;       mov     x15, #0
-;;       add     x0, x0, w4, uxtw
-;;       mov     x1, #0xffff0000
-;;       add     x0, x0, x1
-;;       cmp     x13, x14
-;;       csel    x15, x15, x0, hi
-;;       ldrb    w2, [x15]
+;;       mov     w14, w4
+;;       mov     w15, #-0xffff
+;;       adds    x14, x14, x15
+;;       b.hs    #0xa8
+;;   78: ldr     x15, [x2, #0x40]
+;;       ldr     x1, [x2, #0x38]
+;;       mov     x0, #0
+;;       add     x1, x1, w4, uxtw
+;;       mov     x2, #0xffff0000
+;;       add     x1, x1, x2
+;;       cmp     x14, x15
+;;       csel    x0, x0, x1, hi
+;;       ldrb    w0, [x0]
+;;       uxtb    w2, w0
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
-;;   a4: udf     #0xc11f
+;;   a8: udf     #0xc11f
diff --git a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
index 8a8c9901ca5e..6ddcb60dce4d 100644
--- a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
@@ -34,12 +34,13 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       ldr     x6, [x2, #0x40]
-;;       mov     w7, w4
-;;       cmp     x7, x6
-;;       b.hs    #0x68
-;;   58: ldr     x8, [x2, #0x38]
-;;       ldrb    w2, [x8, w4, uxtw]
+;;       ldr     x7, [x2, #0x40]
+;;       mov     w8, w4
+;;       cmp     x8, x7
+;;       b.hs    #0x6c
+;;   58: ldr     x9, [x2, #0x38]
+;;       ldrb    w9, [x9, w4, uxtw]
+;;       uxtb    w2, w9
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
-;;   68: udf     #0xc11f
+;;   6c: udf     #0xc11f
diff --git a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
index a27e5f063e2c..329decb74597 100644
--- a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -35,13 +35,14 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       ldr     x7, [x2, #0x40]
-;;       mov     w8, w4
-;;       cmp     x8, x7
-;;       b.hi    #0x6c
-;;   58: ldr     x9, [x2, #0x38]
-;;       add     x8, x9, #1, lsl #12
-;;       ldrb    w2, [x8, w4, uxtw]
+;;       ldr     x8, [x2, #0x40]
+;;       mov     w9, w4
+;;       cmp     x9, x8
+;;       b.hi    #0x70
+;;   58: ldr     x10, [x2, #0x38]
+;;       add     x9, x10, #1, lsl #12
+;;       ldrb    w11, [x9, w4, uxtw]
+;;       uxtb    w2, w11
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
-;;   6c: udf     #0xc11f
+;;   70: udf     #0xc11f
diff --git a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index a24e3cd30943..f6962f0aea92 100644
--- a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -36,14 +36,15 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       ldr     x8, [x2, #0x40]
-;;       mov     w9, w4
-;;       cmp     x9, x8
-;;       b.hi    #0x70
-;;   58: ldr     x10, [x2, #0x38]
-;;       add     x10, x10, w4, uxtw
-;;       mov     x11, #0xffff0000
-;;       ldrb    w2, [x10, x11]
+;;       ldr     x9, [x2, #0x40]
+;;       mov     w10, w4
+;;       cmp     x10, x9
+;;       b.hi    #0x74
+;;   58: ldr     x11, [x2, #0x38]
+;;       add     x11, x11, w4, uxtw
+;;       mov     x12, #0xffff0000
+;;       ldrb    w11, [x11, x12]
+;;       uxtb    w2, w11
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
-;;   70: udf     #0xc11f
+;;   74: udf     #0xc11f
diff --git a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index b9546ed02d78..7b4f095e6a9f 100644
--- a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -35,13 +35,14 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       ldr     x9, [x2, #0x40]
-;;       ldr     x10, [x2, #0x38]
-;;       mov     w11, w4
-;;       mov     x12, #0
-;;       add     x10, x10, w4, uxtw
-;;       cmp     x11, x9
-;;       csel    x10, x12, x10, hs
-;;       ldrb    w2, [x10]
+;;       ldr     x10, [x2, #0x40]
+;;       ldr     x11, [x2, #0x38]
+;;       mov     w12, w4
+;;       mov     x13, #0
+;;       add     x11, x11, w4, uxtw
+;;       cmp     x12, x10
+;;       csel    x11, x13, x11, hs
+;;       ldrb    w11, [x11]
+;;       uxtb    w2, w11
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index 375341e89818..e6f9f34e0079 100644
--- a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -36,14 +36,15 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       ldr     x10, [x2, #0x40]
-;;       ldr     x13, [x2, #0x38]
-;;       mov     w11, w4
-;;       mov     x12, #0
-;;       add     x13, x13, w4, uxtw
-;;       add     x13, x13, #1, lsl #12
-;;       cmp     x11, x10
-;;       csel    x11, x12, x13, hi
-;;       ldrb    w2, [x11]
+;;       ldr     x11, [x2, #0x40]
+;;       ldr     x14, [x2, #0x38]
+;;       mov     w12, w4
+;;       mov     x13, #0
+;;       add     x14, x14, w4, uxtw
+;;       add     x14, x14, #1, lsl #12
+;;       cmp     x12, x11
+;;       csel    x12, x13, x14, hi
+;;       ldrb    w12, [x12]
+;;       uxtb    w2, w12
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index a82d8d3a1ea2..6bb7a50370b7 100644
--- a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -37,15 +37,16 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       ldr     x11, [x2, #0x40]
-;;       ldr     x14, [x2, #0x38]
-;;       mov     w12, w4
-;;       mov     x13, #0
-;;       add     x14, x14, w4, uxtw
-;;       mov     x15, #0xffff0000
-;;       add     x14, x14, x15
-;;       cmp     x12, x11
-;;       csel    x12, x13, x14, hi
-;;       ldrb    w2, [x12]
+;;       ldr     x12, [x2, #0x40]
+;;       ldr     x15, [x2, #0x38]
+;;       mov     w13, w4
+;;       mov     x14, #0
+;;       add     x15, x15, w4, uxtw
+;;       mov     x0, #0xffff0000
+;;       add     x15, x15, x0
+;;       cmp     x13, x12
+;;       csel    x13, x14, x15, hi
+;;       ldrb    w13, [x13]
+;;       uxtb    w2, w13
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
index deb4ebd3e2b9..41ab9ef5a577 100644
--- a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
@@ -33,11 +33,12 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       ldr     x5, [x2, #0x40]
-;;       cmp     x4, x5
-;;       b.hs    #0x64
-;;   54: ldr     x7, [x2, #0x38]
-;;       ldrb    w2, [x7, x4]
+;;       ldr     x6, [x2, #0x40]
+;;       cmp     x4, x6
+;;       b.hs    #0x68
+;;   54: ldr     x8, [x2, #0x38]
+;;       ldrb    w8, [x8, x4]
+;;       uxtb    w2, w8
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
-;;   64: udf     #0xc11f
+;;   68: udf     #0xc11f
diff --git a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
index 08ab67fd3f76..0a0c13642b9f 100644
--- a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -36,14 +36,15 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       ldr     x8, [x2, #0x40]
-;;       mov     x9, #0x1001
-;;       sub     x8, x8, x9
-;;       cmp     x4, x8
-;;       b.hi    #0x70
-;;   5c: ldr     x10, [x2, #0x38]
-;;       add     x9, x10, #1, lsl #12
-;;       ldrb    w2, [x9, x4]
+;;       ldr     x9, [x2, #0x40]
+;;       mov     x10, #0x1001
+;;       sub     x9, x9, x10
+;;       cmp     x4, x9
+;;       b.hi    #0x74
+;;   5c: ldr     x11, [x2, #0x38]
+;;       add     x10, x11, #1, lsl #12
+;;       ldrb    w12, [x10, x4]
+;;       uxtb    w2, w12
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
-;;   70: udf     #0xc11f
+;;   74: udf     #0xc11f
diff --git a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 6857e4bc5844..df9138bcfda2 100644
--- a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -39,17 +39,18 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       mov     w9, #-0xffff
-;;       adds    x9, x4, x9
-;;       b.hs    #0x78
-;;   54: ldr     x10, [x2, #0x40]
-;;       cmp     x9, x10
-;;       b.hi    #0x7c
-;;   60: ldr     x12, [x2, #0x38]
-;;       add     x12, x12, x4
-;;       mov     x13, #0xffff0000
-;;       ldrb    w2, [x12, x13]
+;;       mov     w10, #-0xffff
+;;       adds    x10, x4, x10
+;;       b.hs    #0x7c
+;;   54: ldr     x11, [x2, #0x40]
+;;       cmp     x10, x11
+;;       b.hi    #0x80
+;;   60: ldr     x13, [x2, #0x38]
+;;       add     x13, x13, x4
+;;       mov     x14, #0xffff0000
+;;       ldrb    w13, [x13, x14]
+;;       uxtb    w2, w13
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
-;;   78: udf     #0xc11f
 ;;   7c: udf     #0xc11f
+;;   80: udf     #0xc11f
diff --git a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 9495b09c9c0e..de014d5bd376 100644
--- a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -34,12 +34,13 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       ldr     x8, [x2, #0x40]
-;;       ldr     x10, [x2, #0x38]
-;;       mov     x9, #0
-;;       add     x10, x10, x4
-;;       cmp     x4, x8
-;;       csel    x9, x9, x10, hs
-;;       ldrb    w2, [x9]
+;;       ldr     x9, [x2, #0x40]
+;;       ldr     x11, [x2, #0x38]
+;;       mov     x10, #0
+;;       add     x11, x11, x4
+;;       cmp     x4, x9
+;;       csel    x10, x10, x11, hs
+;;       ldrb    w10, [x10]
+;;       uxtb    w2, w10
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 58fee0976d96..8b42ced6a97e 100644
--- a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -37,15 +37,16 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       ldr     x12, [x2, #0x40]
-;;       ldr     x11, [x2, #0x38]
-;;       mov     x13, #0x1001
-;;       sub     x12, x12, x13
-;;       mov     x13, #0
-;;       add     x11, x11, x4
-;;       add     x11, x11, #1, lsl #12
-;;       cmp     x4, x12
-;;       csel    x12, x13, x11, hi
-;;       ldrb    w2, [x12]
+;;       ldr     x13, [x2, #0x40]
+;;       ldr     x12, [x2, #0x38]
+;;       mov     x14, #0x1001
+;;       sub     x13, x13, x14
+;;       mov     x14, #0
+;;       add     x12, x12, x4
+;;       add     x12, x12, #1, lsl #12
+;;       cmp     x4, x13
+;;       csel    x13, x14, x12, hi
+;;       ldrb    w13, [x13]
+;;       uxtb    w2, w13
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 6ad974e65602..e10e4ba85c33 100644
--- a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -40,18 +40,19 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       mov     w12, #-0xffff
-;;       adds    x12, x4, x12
-;;       b.hs    #0xa0
-;;   74: ldr     x13, [x2, #0x40]
-;;       ldr     x15, [x2, #0x38]
-;;       mov     x14, #0
-;;       add     x15, x15, x4
-;;       mov     x0, #0xffff0000
-;;       add     x15, x15, x0
-;;       cmp     x12, x13
-;;       csel    x14, x14, x15, hi
-;;       ldrb    w2, [x14]
+;;       mov     w13, #-0xffff
+;;       adds    x13, x4, x13
+;;       b.hs    #0xa4
+;;   74: ldr     x14, [x2, #0x40]
+;;       ldr     x0, [x2, #0x38]
+;;       mov     x15, #0
+;;       add     x0, x0, x4
+;;       mov     x1, #0xffff0000
+;;       add     x0, x0, x1
+;;       cmp     x13, x14
+;;       csel    x15, x15, x0, hi
+;;       ldrb    w15, [x15]
+;;       uxtb    w2, w15
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
-;;   a0: udf     #0xc11f
+;;   a4: udf     #0xc11f
diff --git a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
index 6eb814e57d04..b1dd7d8727a3 100644
--- a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
@@ -33,11 +33,12 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       ldr     x5, [x2, #0x40]
-;;       cmp     x4, x5
-;;       b.hs    #0x64
-;;   54: ldr     x7, [x2, #0x38]
-;;       ldrb    w2, [x7, x4]
+;;       ldr     x6, [x2, #0x40]
+;;       cmp     x4, x6
+;;       b.hs    #0x68
+;;   54: ldr     x8, [x2, #0x38]
+;;       ldrb    w8, [x8, x4]
+;;       uxtb    w2, w8
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
-;;   64: udf     #0xc11f
+;;   68: udf     #0xc11f
diff --git a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
index cc6498872c87..009105f15fe8 100644
--- a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -34,12 +34,13 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       ldr     x6, [x2, #0x40]
-;;       cmp     x4, x6
-;;       b.hi    #0x68
-;;   54: ldr     x8, [x2, #0x38]
-;;       add     x7, x8, #1, lsl #12
-;;       ldrb    w2, [x7, x4]
+;;       ldr     x7, [x2, #0x40]
+;;       cmp     x4, x7
+;;       b.hi    #0x6c
+;;   54: ldr     x9, [x2, #0x38]
+;;       add     x8, x9, #1, lsl #12
+;;       ldrb    w10, [x8, x4]
+;;       uxtb    w2, w10
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
-;;   68: udf     #0xc11f
+;;   6c: udf     #0xc11f
diff --git a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index be18c1f2d274..bb4bbfa700e2 100644
--- a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -35,13 +35,14 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       ldr     x7, [x2, #0x40]
-;;       cmp     x4, x7
-;;       b.hi    #0x6c
-;;   54: ldr     x9, [x2, #0x38]
-;;       add     x9, x9, x4
-;;       mov     x10, #0xffff0000
-;;       ldrb    w2, [x9, x10]
+;;       ldr     x8, [x2, #0x40]
+;;       cmp     x4, x8
+;;       b.hi    #0x70
+;;   54: ldr     x10, [x2, #0x38]
+;;       add     x10, x10, x4
+;;       mov     x11, #0xffff0000
+;;       ldrb    w10, [x10, x11]
+;;       uxtb    w2, w10
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
-;;   6c: udf     #0xc11f
+;;   70: udf     #0xc11f
diff --git a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index 03d19995a964..c465a0de7cf5 100644
--- a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -34,12 +34,13 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       ldr     x8, [x2, #0x40]
-;;       ldr     x10, [x2, #0x38]
-;;       mov     x9, #0
-;;       add     x10, x10, x4
-;;       cmp     x4, x8
-;;       csel    x9, x9, x10, hs
-;;       ldrb    w2, [x9]
+;;       ldr     x9, [x2, #0x40]
+;;       ldr     x11, [x2, #0x38]
+;;       mov     x10, #0
+;;       add     x11, x11, x4
+;;       cmp     x4, x9
+;;       csel    x10, x10, x11, hs
+;;       ldrb    w10, [x10]
+;;       uxtb    w2, w10
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index 526cfecde2e8..3f3539cedfe5 100644
--- a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -35,13 +35,14 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       ldr     x9, [x2, #0x40]
-;;       ldr     x11, [x2, #0x38]
-;;       mov     x10, #0
-;;       add     x11, x11, x4
-;;       add     x11, x11, #1, lsl #12
-;;       cmp     x4, x9
-;;       csel    x10, x10, x11, hi
-;;       ldrb    w2, [x10]
+;;       ldr     x10, [x2, #0x40]
+;;       ldr     x12, [x2, #0x38]
+;;       mov     x11, #0
+;;       add     x12, x12, x4
+;;       add     x12, x12, #1, lsl #12
+;;       cmp     x4, x10
+;;       csel    x11, x11, x12, hi
+;;       ldrb    w11, [x11]
+;;       uxtb    w2, w11
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 1037dc48a078..0180fe3b2e7e 100644
--- a/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -36,14 +36,15 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       ldr     x10, [x2, #0x40]
-;;       ldr     x12, [x2, #0x38]
-;;       mov     x11, #0
-;;       add     x12, x12, x4
-;;       mov     x13, #0xffff0000
-;;       add     x12, x12, x13
-;;       cmp     x4, x10
-;;       csel    x11, x11, x12, hi
-;;       ldrb    w2, [x11]
+;;       ldr     x11, [x2, #0x40]
+;;       ldr     x13, [x2, #0x38]
+;;       mov     x12, #0
+;;       add     x13, x13, x4
+;;       mov     x14, #0xffff0000
+;;       add     x13, x13, x14
+;;       cmp     x4, x11
+;;       csel    x12, x12, x13, hi
+;;       ldrb    w12, [x12]
+;;       uxtb    w2, w12
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
index 7b321a3d1a0f..5a9370635654 100644
--- a/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
@@ -30,6 +30,7 @@
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
 ;;       ldr     x5, [x2, #0x38]
-;;       ldrb    w2, [x5, w4, uxtw]
+;;       ldrb    w5, [x5, w4, uxtw]
+;;       uxtb    w2, w5
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
index 2248a7e11298..cf8c67d494d5 100644
--- a/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -35,13 +35,14 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       mov     w7, w4
-;;       mov     w8, #-0x1001
-;;       cmp     x7, x8
-;;       b.hi    #0x6c
-;;   58: ldr     x9, [x2, #0x38]
-;;       add     x8, x9, #1, lsl #12
-;;       ldrb    w2, [x8, w4, uxtw]
+;;       mov     w8, w4
+;;       mov     w9, #-0x1001
+;;       cmp     x8, x9
+;;       b.hi    #0x70
+;;   58: ldr     x10, [x2, #0x38]
+;;       add     x9, x10, #1, lsl #12
+;;       ldrb    w11, [x9, w4, uxtw]
+;;       uxtb    w2, w11
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
-;;   6c: udf     #0xc11f
+;;   70: udf     #0xc11f
diff --git a/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 20e2c6f5c244..e7bfc4f6e5d4 100644
--- a/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -36,14 +36,15 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       mov     w8, w4
-;;       mov     x9, #0xffff
-;;       cmp     x8, x9
-;;       b.hi    #0x70
-;;   58: ldr     x10, [x2, #0x38]
-;;       add     x10, x10, w4, uxtw
-;;       mov     x11, #0xffff0000
-;;       ldrb    w2, [x10, x11]
+;;       mov     w9, w4
+;;       mov     x10, #0xffff
+;;       cmp     x9, x10
+;;       b.hi    #0x74
+;;   58: ldr     x11, [x2, #0x38]
+;;       add     x11, x11, w4, uxtw
+;;       mov     x12, #0xffff0000
+;;       ldrb    w11, [x11, x12]
+;;       uxtb    w2, w11
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
-;;   70: udf     #0xc11f
+;;   74: udf     #0xc11f
diff --git a/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 1e5e8245d3fe..ff205449da86 100644
--- a/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -30,6 +30,7 @@
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
 ;;       ldr     x5, [x2, #0x38]
-;;       ldrb    w2, [x5, w4, uxtw]
+;;       ldrb    w5, [x5, w4, uxtw]
+;;       uxtb    w2, w5
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 0d7b4dd00f4a..2dab82de1940 100644
--- a/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -36,14 +36,15 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       mov     w10, w4
-;;       mov     w11, #-0x1001
-;;       mov     x12, #0
-;;       ldr     x13, [x2, #0x38]
-;;       add     x13, x13, w4, uxtw
-;;       add     x13, x13, #1, lsl #12
-;;       cmp     x10, x11
-;;       csel    x11, x12, x13, hi
-;;       ldrb    w2, [x11]
+;;       mov     w11, w4
+;;       mov     w12, #-0x1001
+;;       mov     x13, #0
+;;       ldr     x14, [x2, #0x38]
+;;       add     x14, x14, w4, uxtw
+;;       add     x14, x14, #1, lsl #12
+;;       cmp     x11, x12
+;;       csel    x12, x13, x14, hi
+;;       ldrb    w12, [x12]
+;;       uxtb    w2, w12
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 79ddac44d0e9..76e84413497a 100644
--- a/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -37,15 +37,16 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       mov     w11, w4
-;;       mov     x12, #0xffff
-;;       mov     x13, #0
-;;       ldr     x14, [x2, #0x38]
-;;       add     x14, x14, w4, uxtw
-;;       mov     x15, #0xffff0000
-;;       add     x14, x14, x15
-;;       cmp     x11, x12
-;;       csel    x12, x13, x14, hi
-;;       ldrb    w2, [x12]
+;;       mov     w12, w4
+;;       mov     x13, #0xffff
+;;       mov     x14, #0
+;;       ldr     x15, [x2, #0x38]
+;;       add     x15, x15, w4, uxtw
+;;       mov     x0, #0xffff0000
+;;       add     x15, x15, x0
+;;       cmp     x12, x13
+;;       csel    x13, x14, x15, hi
+;;       ldrb    w13, [x13]
+;;       uxtb    w2, w13
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
index 15e732b9855b..aec9e930cac1 100644
--- a/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
@@ -30,6 +30,7 @@
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
 ;;       ldr     x5, [x2, #0x38]
-;;       ldrb    w2, [x5, w4, uxtw]
+;;       ldrb    w5, [x5, w4, uxtw]
+;;       uxtb    w2, w5
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
index 585af20cb4e0..a66b8d7d9b8d 100644
--- a/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -30,8 +30,9 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       ldr     x5, [x2, #0x38]
-;;       add     x5, x5, #1, lsl #12
-;;       ldrb    w2, [x5, w4, uxtw]
+;;       ldr     x6, [x2, #0x38]
+;;       add     x5, x6, #1, lsl #12
+;;       ldrb    w7, [x5, w4, uxtw]
+;;       uxtb    w2, w7
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index aee771636f64..594255900b53 100644
--- a/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -31,9 +31,10 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       ldr     x6, [x2, #0x38]
-;;       add     x6, x6, w4, uxtw
-;;       mov     x7, #0xffff0000
-;;       ldrb    w2, [x6, x7]
+;;       ldr     x7, [x2, #0x38]
+;;       add     x7, x7, w4, uxtw
+;;       mov     x8, #0xffff0000
+;;       ldrb    w7, [x7, x8]
+;;       uxtb    w2, w7
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index be7c1779b502..37d5cff96eac 100644
--- a/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -30,6 +30,7 @@
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
 ;;       ldr     x5, [x2, #0x38]
-;;       ldrb    w2, [x5, w4, uxtw]
+;;       ldrb    w5, [x5, w4, uxtw]
+;;       uxtb    w2, w5
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index f2cb9205129a..6f468ce2c17e 100644
--- a/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -30,8 +30,9 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       ldr     x5, [x2, #0x38]
-;;       add     x5, x5, #1, lsl #12
-;;       ldrb    w2, [x5, w4, uxtw]
+;;       ldr     x6, [x2, #0x38]
+;;       add     x5, x6, #1, lsl #12
+;;       ldrb    w7, [x5, w4, uxtw]
+;;       uxtb    w2, w7
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 791cae021040..653fd1faab06 100644
--- a/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -31,9 +31,10 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       ldr     x6, [x2, #0x38]
-;;       add     x6, x6, w4, uxtw
-;;       mov     x7, #0xffff0000
-;;       ldrb    w2, [x6, x7]
+;;       ldr     x7, [x2, #0x38]
+;;       add     x7, x7, w4, uxtw
+;;       mov     x8, #0xffff0000
+;;       ldrb    w7, [x7, x8]
+;;       uxtb    w2, w7
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
index 7a10b758d125..5e2fecb73226 100644
--- a/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
@@ -33,11 +33,12 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       mov     x5, #0xffffffff
-;;       cmp     x4, x5
-;;       b.hi    #0x64
-;;   54: ldr     x7, [x2, #0x38]
-;;       ldrb    w2, [x7, x4]
+;;       mov     x6, #0xffffffff
+;;       cmp     x4, x6
+;;       b.hi    #0x68
+;;   54: ldr     x8, [x2, #0x38]
+;;       ldrb    w8, [x8, x4]
+;;       uxtb    w2, w8
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
-;;   64: udf     #0xc11f
+;;   68: udf     #0xc11f
diff --git a/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
index 3fc5b430fa02..b7540514ab66 100644
--- a/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -34,12 +34,13 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       mov     w6, #-0x1001
-;;       cmp     x4, x6
-;;       b.hi    #0x68
-;;   54: ldr     x8, [x2, #0x38]
-;;       add     x7, x8, #1, lsl #12
-;;       ldrb    w2, [x7, x4]
+;;       mov     w7, #-0x1001
+;;       cmp     x4, x7
+;;       b.hi    #0x6c
+;;   54: ldr     x9, [x2, #0x38]
+;;       add     x8, x9, #1, lsl #12
+;;       ldrb    w10, [x8, x4]
+;;       uxtb    w2, w10
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
-;;   68: udf     #0xc11f
+;;   6c: udf     #0xc11f
diff --git a/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index aa1550b2a2ed..221db39901cf 100644
--- a/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -35,13 +35,14 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       mov     x7, #0xffff
-;;       cmp     x4, x7
-;;       b.hi    #0x6c
-;;   54: ldr     x9, [x2, #0x38]
-;;       add     x9, x9, x4
-;;       mov     x10, #0xffff0000
-;;       ldrb    w2, [x9, x10]
+;;       mov     x8, #0xffff
+;;       cmp     x4, x8
+;;       b.hi    #0x70
+;;   54: ldr     x10, [x2, #0x38]
+;;       add     x10, x10, x4
+;;       mov     x11, #0xffff0000
+;;       ldrb    w10, [x10, x11]
+;;       uxtb    w2, w10
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
-;;   6c: udf     #0xc11f
+;;   70: udf     #0xc11f
diff --git a/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 76cd556a9b1e..bc9c52054b45 100644
--- a/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -34,12 +34,13 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       mov     x8, #0xffffffff
-;;       mov     x9, #0
-;;       ldr     x10, [x2, #0x38]
-;;       add     x10, x10, x4
-;;       cmp     x4, x8
-;;       csel    x9, x9, x10, hi
-;;       ldrb    w2, [x9]
+;;       mov     x9, #0xffffffff
+;;       mov     x10, #0
+;;       ldr     x11, [x2, #0x38]
+;;       add     x11, x11, x4
+;;       cmp     x4, x9
+;;       csel    x10, x10, x11, hi
+;;       ldrb    w10, [x10]
+;;       uxtb    w2, w10
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 79118a352f1a..7dd086595a30 100644
--- a/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -35,13 +35,14 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       mov     w9, #-0x1001
-;;       mov     x10, #0
-;;       ldr     x11, [x2, #0x38]
-;;       add     x11, x11, x4
-;;       add     x11, x11, #1, lsl #12
-;;       cmp     x4, x9
-;;       csel    x10, x10, x11, hi
-;;       ldrb    w2, [x10]
+;;       mov     w10, #-0x1001
+;;       mov     x11, #0
+;;       ldr     x12, [x2, #0x38]
+;;       add     x12, x12, x4
+;;       add     x12, x12, #1, lsl #12
+;;       cmp     x4, x10
+;;       csel    x11, x11, x12, hi
+;;       ldrb    w11, [x11]
+;;       uxtb    w2, w11
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 799a6f85bb4f..28868ad19865 100644
--- a/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -36,14 +36,15 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       mov     x10, #0xffff
-;;       mov     x11, #0
-;;       ldr     x12, [x2, #0x38]
-;;       add     x12, x12, x4
-;;       mov     x13, #0xffff0000
-;;       add     x12, x12, x13
-;;       cmp     x4, x10
-;;       csel    x11, x11, x12, hi
-;;       ldrb    w2, [x11]
+;;       mov     x11, #0xffff
+;;       mov     x12, #0
+;;       ldr     x13, [x2, #0x38]
+;;       add     x13, x13, x4
+;;       mov     x14, #0xffff0000
+;;       add     x13, x13, x14
+;;       cmp     x4, x11
+;;       csel    x12, x12, x13, hi
+;;       ldrb    w12, [x12]
+;;       uxtb    w2, w12
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
index bc8a27bca72b..03489657e63f 100644
--- a/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
@@ -33,11 +33,12 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       mov     x5, #0xffffffff
-;;       cmp     x4, x5
-;;       b.hi    #0x64
-;;   54: ldr     x7, [x2, #0x38]
-;;       ldrb    w2, [x7, x4]
+;;       mov     x6, #0xffffffff
+;;       cmp     x4, x6
+;;       b.hi    #0x68
+;;   54: ldr     x8, [x2, #0x38]
+;;       ldrb    w8, [x8, x4]
+;;       uxtb    w2, w8
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
-;;   64: udf     #0xc11f
+;;   68: udf     #0xc11f
diff --git a/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
index a121eac2a463..df5836d63f30 100644
--- a/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -34,12 +34,13 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       mov     w6, #-0x1001
-;;       cmp     x4, x6
-;;       b.hi    #0x68
-;;   54: ldr     x8, [x2, #0x38]
-;;       add     x7, x8, #1, lsl #12
-;;       ldrb    w2, [x7, x4]
+;;       mov     w7, #-0x1001
+;;       cmp     x4, x7
+;;       b.hi    #0x6c
+;;   54: ldr     x9, [x2, #0x38]
+;;       add     x8, x9, #1, lsl #12
+;;       ldrb    w10, [x8, x4]
+;;       uxtb    w2, w10
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
-;;   68: udf     #0xc11f
+;;   6c: udf     #0xc11f
diff --git a/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 56a7e26f0729..4e57a94b5010 100644
--- a/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -35,13 +35,14 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       mov     x7, #0xffff
-;;       cmp     x4, x7
-;;       b.hi    #0x6c
-;;   54: ldr     x9, [x2, #0x38]
-;;       add     x9, x9, x4
-;;       mov     x10, #0xffff0000
-;;       ldrb    w2, [x9, x10]
+;;       mov     x8, #0xffff
+;;       cmp     x4, x8
+;;       b.hi    #0x70
+;;   54: ldr     x10, [x2, #0x38]
+;;       add     x10, x10, x4
+;;       mov     x11, #0xffff0000
+;;       ldrb    w10, [x10, x11]
+;;       uxtb    w2, w10
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
-;;   6c: udf     #0xc11f
+;;   70: udf     #0xc11f
diff --git a/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index 766e2aaa1e25..1b6bd156b9a4 100644
--- a/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -34,12 +34,13 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       mov     x8, #0xffffffff
-;;       mov     x9, #0
-;;       ldr     x10, [x2, #0x38]
-;;       add     x10, x10, x4
-;;       cmp     x4, x8
-;;       csel    x9, x9, x10, hi
-;;       ldrb    w2, [x9]
+;;       mov     x9, #0xffffffff
+;;       mov     x10, #0
+;;       ldr     x11, [x2, #0x38]
+;;       add     x11, x11, x4
+;;       cmp     x4, x9
+;;       csel    x10, x10, x11, hi
+;;       ldrb    w10, [x10]
+;;       uxtb    w2, w10
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index a6453f4c3a64..34cd1d127b56 100644
--- a/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -35,13 +35,14 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       mov     w9, #-0x1001
-;;       mov     x10, #0
-;;       ldr     x11, [x2, #0x38]
-;;       add     x11, x11, x4
-;;       add     x11, x11, #1, lsl #12
-;;       cmp     x4, x9
-;;       csel    x10, x10, x11, hi
-;;       ldrb    w2, [x10]
+;;       mov     w10, #-0x1001
+;;       mov     x11, #0
+;;       ldr     x12, [x2, #0x38]
+;;       add     x12, x12, x4
+;;       add     x12, x12, #1, lsl #12
+;;       cmp     x4, x10
+;;       csel    x11, x11, x12, hi
+;;       ldrb    w11, [x11]
+;;       uxtb    w2, w11
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index c186e4e0b59d..77194fdb42d2 100644
--- a/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/aarch64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -36,14 +36,15 @@
 ;; wasm[0]::function[1]:
 ;;       stp     x29, x30, [sp, #-0x10]!
 ;;       mov     x29, sp
-;;       mov     x10, #0xffff
-;;       mov     x11, #0
-;;       ldr     x12, [x2, #0x38]
-;;       add     x12, x12, x4
-;;       mov     x13, #0xffff0000
-;;       add     x12, x12, x13
-;;       cmp     x4, x10
-;;       csel    x11, x11, x12, hi
-;;       ldrb    w2, [x11]
+;;       mov     x11, #0xffff
+;;       mov     x12, #0
+;;       ldr     x13, [x2, #0x38]
+;;       add     x13, x13, x4
+;;       mov     x14, #0xffff0000
+;;       add     x13, x13, x14
+;;       cmp     x4, x11
+;;       csel    x12, x12, x13, hi
+;;       ldrb    w12, [x12]
+;;       uxtb    w2, w12
 ;;       ldp     x29, x30, [sp], #0x10
 ;;       ret
diff --git a/tests/disas/load-store/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
index 4b2d8fa36c12..347543b86999 100644
--- a/tests/disas/load-store/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
@@ -36,7 +36,8 @@
 ;; @0040                               trapnz v6, heap_oob
 ;; @0040                               v7 = load.i64 notrap aligned can_move region2 v0+56
 ;; @0040                               v8 = iadd v7, v4
-;; @0040                               istore8 little region4 v3, v8
+;; @0040                               v9 = ireduce.i8 v3
+;; @0040                               store little region4 v9, v8
 ;; @0043                               jump block1
 ;;
 ;;                                 block1:
@@ -61,9 +62,10 @@
 ;; @0048                               trapnz v5, heap_oob
 ;; @0048                               v6 = load.i64 notrap aligned can_move region2 v0+56
 ;; @0048                               v7 = iadd v6, v3
-;; @0048                               v8 = uload8.i32 little region4 v7
+;; @0048                               v8 = load.i8 little region4 v7
+;; @0048                               v9 = uextend.i32 v8
 ;; @004b                               jump block1
 ;;
 ;;                                 block1:
-;; @004b                               return v8
+;; @004b                               return v9
 ;; }
diff --git a/tests/disas/load-store/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
index 790a376240f0..edff84155396 100644
--- a/tests/disas/load-store/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -40,7 +40,8 @@
 ;; @0040                               v10 = iadd v9, v4
 ;; @0040                               v11 = iconst.i64 4096
 ;; @0040                               v12 = iadd v10, v11  ; v11 = 4096
-;; @0040                               istore8 little region4 v3, v12
+;; @0040                               v13 = ireduce.i8 v3
+;; @0040                               store little region4 v13, v12
 ;; @0044                               jump block1
 ;;
 ;;                                 block1:
@@ -69,9 +70,10 @@
 ;; @0049                               v9 = iadd v8, v3
 ;; @0049                               v10 = iconst.i64 4096
 ;; @0049                               v11 = iadd v9, v10  ; v10 = 4096
-;; @0049                               v12 = uload8.i32 little region4 v11
+;; @0049                               v12 = load.i8 little region4 v11
+;; @0049                               v13 = uextend.i32 v12
 ;; @004d                               jump block1
 ;;
 ;;                                 block1:
-;; @004d                               return v12
+;; @004d                               return v13
 ;; }
diff --git a/tests/disas/load-store/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 6162b34de48b..c2261441b267 100644
--- a/tests/disas/load-store/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -40,7 +40,8 @@
 ;; @0040                               v10 = iadd v9, v4
 ;; @0040                               v11 = iconst.i64 0xffff_0000
 ;; @0040                               v12 = iadd v10, v11  ; v11 = 0xffff_0000
-;; @0040                               istore8 little region4 v3, v12
+;; @0040                               v13 = ireduce.i8 v3
+;; @0040                               store little region4 v13, v12
 ;; @0047                               jump block1
 ;;
 ;;                                 block1:
@@ -69,9 +70,10 @@
 ;; @004c                               v9 = iadd v8, v3
 ;; @004c                               v10 = iconst.i64 0xffff_0000
 ;; @004c                               v11 = iadd v9, v10  ; v10 = 0xffff_0000
-;; @004c                               v12 = uload8.i32 little region4 v11
+;; @004c                               v12 = load.i8 little region4 v11
+;; @004c                               v13 = uextend.i32 v12
 ;; @0053                               jump block1
 ;;
 ;;                                 block1:
-;; @0053                               return v12
+;; @0053                               return v13
 ;; }
diff --git a/tests/disas/load-store/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 307902c2fdc1..04db961ca96a 100644
--- a/tests/disas/load-store/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -37,7 +37,8 @@
 ;; @0040                               v8 = iadd v7, v4
 ;; @0040                               v9 = iconst.i64 0
 ;; @0040                               v10 = select_spectre_guard v6, v9, v8  ; v9 = 0
-;; @0040                               istore8 little region4 v3, v10
+;; @0040                               v11 = ireduce.i8 v3
+;; @0040                               store little region4 v11, v10
 ;; @0043                               jump block1
 ;;
 ;;                                 block1:
@@ -63,9 +64,10 @@
 ;; @0048                               v7 = iadd v6, v3
 ;; @0048                               v8 = iconst.i64 0
 ;; @0048                               v9 = select_spectre_guard v5, v8, v7  ; v8 = 0
-;; @0048                               v10 = uload8.i32 little region4 v9
+;; @0048                               v10 = load.i8 little region4 v9
+;; @0048                               v11 = uextend.i32 v10
 ;; @004b                               jump block1
 ;;
 ;;                                 block1:
-;; @004b                               return v10
+;; @004b                               return v11
 ;; }
diff --git a/tests/disas/load-store/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 984b8504c781..4241939a2b7f 100644
--- a/tests/disas/load-store/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -41,7 +41,8 @@
 ;; @0040                               v12 = iadd v10, v11  ; v11 = 4096
 ;; @0040                               v13 = iconst.i64 0
 ;; @0040                               v14 = select_spectre_guard v8, v13, v12  ; v13 = 0
-;; @0040                               istore8 little region4 v3, v14
+;; @0040                               v15 = ireduce.i8 v3
+;; @0040                               store little region4 v15, v14
 ;; @0044                               jump block1
 ;;
 ;;                                 block1:
@@ -71,9 +72,10 @@
 ;; @0049                               v11 = iadd v9, v10  ; v10 = 4096
 ;; @0049                               v12 = iconst.i64 0
 ;; @0049                               v13 = select_spectre_guard v7, v12, v11  ; v12 = 0
-;; @0049                               v14 = uload8.i32 little region4 v13
+;; @0049                               v14 = load.i8 little region4 v13
+;; @0049                               v15 = uextend.i32 v14
 ;; @004d                               jump block1
 ;;
 ;;                                 block1:
-;; @004d                               return v14
+;; @004d                               return v15
 ;; }
diff --git a/tests/disas/load-store/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 7825e6dbc195..aba5580eda56 100644
--- a/tests/disas/load-store/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -41,7 +41,8 @@
 ;; @0040                               v12 = iadd v10, v11  ; v11 = 0xffff_0000
 ;; @0040                               v13 = iconst.i64 0
 ;; @0040                               v14 = select_spectre_guard v8, v13, v12  ; v13 = 0
-;; @0040                               istore8 little region4 v3, v14
+;; @0040                               v15 = ireduce.i8 v3
+;; @0040                               store little region4 v15, v14
 ;; @0047                               jump block1
 ;;
 ;;                                 block1:
@@ -71,9 +72,10 @@
 ;; @004c                               v11 = iadd v9, v10  ; v10 = 0xffff_0000
 ;; @004c                               v12 = iconst.i64 0
 ;; @004c                               v13 = select_spectre_guard v7, v12, v11  ; v12 = 0
-;; @004c                               v14 = uload8.i32 little region4 v13
+;; @004c                               v14 = load.i8 little region4 v13
+;; @004c                               v15 = uextend.i32 v14
 ;; @0053                               jump block1
 ;;
 ;;                                 block1:
-;; @0053                               return v14
+;; @0053                               return v15
 ;; }
diff --git a/tests/disas/load-store/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
index 8f59f5d29620..13d899347def 100644
--- a/tests/disas/load-store/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
@@ -36,7 +36,8 @@
 ;; @0040                               trapnz v6, heap_oob
 ;; @0040                               v7 = load.i64 notrap aligned can_move region2 v0+56
 ;; @0040                               v8 = iadd v7, v4
-;; @0040                               istore8 little region4 v3, v8
+;; @0040                               v9 = ireduce.i8 v3
+;; @0040                               store little region4 v9, v8
 ;; @0043                               jump block1
 ;;
 ;;                                 block1:
@@ -61,9 +62,10 @@
 ;; @0048                               trapnz v5, heap_oob
 ;; @0048                               v6 = load.i64 notrap aligned can_move region2 v0+56
 ;; @0048                               v7 = iadd v6, v3
-;; @0048                               v8 = uload8.i32 little region4 v7
+;; @0048                               v8 = load.i8 little region4 v7
+;; @0048                               v9 = uextend.i32 v8
 ;; @004b                               jump block1
 ;;
 ;;                                 block1:
-;; @004b                               return v8
+;; @004b                               return v9
 ;; }
diff --git a/tests/disas/load-store/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
index 246bbbd498b5..a3c2a4f6fbcc 100644
--- a/tests/disas/load-store/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -38,7 +38,8 @@
 ;; @0040                               v8 = iadd v7, v4
 ;; @0040                               v9 = iconst.i64 4096
 ;; @0040                               v10 = iadd v8, v9  ; v9 = 4096
-;; @0040                               istore8 little region4 v3, v10
+;; @0040                               v11 = ireduce.i8 v3
+;; @0040                               store little region4 v11, v10
 ;; @0044                               jump block1
 ;;
 ;;                                 block1:
@@ -65,9 +66,10 @@
 ;; @0049                               v7 = iadd v6, v3
 ;; @0049                               v8 = iconst.i64 4096
 ;; @0049                               v9 = iadd v7, v8  ; v8 = 4096
-;; @0049                               v10 = uload8.i32 little region4 v9
+;; @0049                               v10 = load.i8 little region4 v9
+;; @0049                               v11 = uextend.i32 v10
 ;; @004d                               jump block1
 ;;
 ;;                                 block1:
-;; @004d                               return v10
+;; @004d                               return v11
 ;; }
diff --git a/tests/disas/load-store/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 3563721b32cb..0e821ec52bb8 100644
--- a/tests/disas/load-store/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -38,7 +38,8 @@
 ;; @0040                               v8 = iadd v7, v4
 ;; @0040                               v9 = iconst.i64 0xffff_0000
 ;; @0040                               v10 = iadd v8, v9  ; v9 = 0xffff_0000
-;; @0040                               istore8 little region4 v3, v10
+;; @0040                               v11 = ireduce.i8 v3
+;; @0040                               store little region4 v11, v10
 ;; @0047                               jump block1
 ;;
 ;;                                 block1:
@@ -65,9 +66,10 @@
 ;; @004c                               v7 = iadd v6, v3
 ;; @004c                               v8 = iconst.i64 0xffff_0000
 ;; @004c                               v9 = iadd v7, v8  ; v8 = 0xffff_0000
-;; @004c                               v10 = uload8.i32 little region4 v9
+;; @004c                               v10 = load.i8 little region4 v9
+;; @004c                               v11 = uextend.i32 v10
 ;; @0053                               jump block1
 ;;
 ;;                                 block1:
-;; @0053                               return v10
+;; @0053                               return v11
 ;; }
diff --git a/tests/disas/load-store/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index 8398a318a63a..fb8550a21ee4 100644
--- a/tests/disas/load-store/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -37,7 +37,8 @@
 ;; @0040                               v8 = iadd v7, v4
 ;; @0040                               v9 = iconst.i64 0
 ;; @0040                               v10 = select_spectre_guard v6, v9, v8  ; v9 = 0
-;; @0040                               istore8 little region4 v3, v10
+;; @0040                               v11 = ireduce.i8 v3
+;; @0040                               store little region4 v11, v10
 ;; @0043                               jump block1
 ;;
 ;;                                 block1:
@@ -63,9 +64,10 @@
 ;; @0048                               v7 = iadd v6, v3
 ;; @0048                               v8 = iconst.i64 0
 ;; @0048                               v9 = select_spectre_guard v5, v8, v7  ; v8 = 0
-;; @0048                               v10 = uload8.i32 little region4 v9
+;; @0048                               v10 = load.i8 little region4 v9
+;; @0048                               v11 = uextend.i32 v10
 ;; @004b                               jump block1
 ;;
 ;;                                 block1:
-;; @004b                               return v10
+;; @004b                               return v11
 ;; }
diff --git a/tests/disas/load-store/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index 485ed12f6150..7ff71de23d2f 100644
--- a/tests/disas/load-store/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -39,7 +39,8 @@
 ;; @0040                               v10 = iadd v8, v9  ; v9 = 4096
 ;; @0040                               v11 = iconst.i64 0
 ;; @0040                               v12 = select_spectre_guard v6, v11, v10  ; v11 = 0
-;; @0040                               istore8 little region4 v3, v12
+;; @0040                               v13 = ireduce.i8 v3
+;; @0040                               store little region4 v13, v12
 ;; @0044                               jump block1
 ;;
 ;;                                 block1:
@@ -67,9 +68,10 @@
 ;; @0049                               v9 = iadd v7, v8  ; v8 = 4096
 ;; @0049                               v10 = iconst.i64 0
 ;; @0049                               v11 = select_spectre_guard v5, v10, v9  ; v10 = 0
-;; @0049                               v12 = uload8.i32 little region4 v11
+;; @0049                               v12 = load.i8 little region4 v11
+;; @0049                               v13 = uextend.i32 v12
 ;; @004d                               jump block1
 ;;
 ;;                                 block1:
-;; @004d                               return v12
+;; @004d                               return v13
 ;; }
diff --git a/tests/disas/load-store/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index ebccfcc2376e..86da8c4187b8 100644
--- a/tests/disas/load-store/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -39,7 +39,8 @@
 ;; @0040                               v10 = iadd v8, v9  ; v9 = 0xffff_0000
 ;; @0040                               v11 = iconst.i64 0
 ;; @0040                               v12 = select_spectre_guard v6, v11, v10  ; v11 = 0
-;; @0040                               istore8 little region4 v3, v12
+;; @0040                               v13 = ireduce.i8 v3
+;; @0040                               store little region4 v13, v12
 ;; @0047                               jump block1
 ;;
 ;;                                 block1:
@@ -67,9 +68,10 @@
 ;; @004c                               v9 = iadd v7, v8  ; v8 = 0xffff_0000
 ;; @004c                               v10 = iconst.i64 0
 ;; @004c                               v11 = select_spectre_guard v5, v10, v9  ; v10 = 0
-;; @004c                               v12 = uload8.i32 little region4 v11
+;; @004c                               v12 = load.i8 little region4 v11
+;; @004c                               v13 = uextend.i32 v12
 ;; @0053                               jump block1
 ;;
 ;;                                 block1:
-;; @0053                               return v12
+;; @0053                               return v13
 ;; }
diff --git a/tests/disas/load-store/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
index a90dde2a9dc0..bbc20dada28a 100644
--- a/tests/disas/load-store/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
@@ -35,7 +35,8 @@
 ;; @0040                               trapnz v5, heap_oob
 ;; @0040                               v6 = load.i64 notrap aligned can_move region2 v0+56
 ;; @0040                               v7 = iadd v6, v2
-;; @0040                               istore8 little region4 v3, v7
+;; @0040                               v8 = ireduce.i8 v3
+;; @0040                               store little region4 v8, v7
 ;; @0043                               jump block1
 ;;
 ;;                                 block1:
@@ -59,9 +60,10 @@
 ;; @0048                               trapnz v4, heap_oob
 ;; @0048                               v5 = load.i64 notrap aligned can_move region2 v0+56
 ;; @0048                               v6 = iadd v5, v2
-;; @0048                               v7 = uload8.i32 little region4 v6
+;; @0048                               v7 = load.i8 little region4 v6
+;; @0048                               v8 = uextend.i32 v7
 ;; @004b                               jump block1
 ;;
 ;;                                 block1:
-;; @004b                               return v7
+;; @004b                               return v8
 ;; }
diff --git a/tests/disas/load-store/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
index d0e7cda5bfe7..697ae4f5aa61 100644
--- a/tests/disas/load-store/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -39,7 +39,8 @@
 ;; @0040                               v9 = iadd v8, v2
 ;; @0040                               v10 = iconst.i64 4096
 ;; @0040                               v11 = iadd v9, v10  ; v10 = 4096
-;; @0040                               istore8 little region4 v3, v11
+;; @0040                               v12 = ireduce.i8 v3
+;; @0040                               store little region4 v12, v11
 ;; @0044                               jump block1
 ;;
 ;;                                 block1:
@@ -67,9 +68,10 @@
 ;; @0049                               v8 = iadd v7, v2
 ;; @0049                               v9 = iconst.i64 4096
 ;; @0049                               v10 = iadd v8, v9  ; v9 = 4096
-;; @0049                               v11 = uload8.i32 little region4 v10
+;; @0049                               v11 = load.i8 little region4 v10
+;; @0049                               v12 = uextend.i32 v11
 ;; @004d                               jump block1
 ;;
 ;;                                 block1:
-;; @004d                               return v11
+;; @004d                               return v12
 ;; }
diff --git a/tests/disas/load-store/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 065be4b82f4a..9b884380be7f 100644
--- a/tests/disas/load-store/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -39,7 +39,8 @@
 ;; @0040                               v9 = iadd v8, v2
 ;; @0040                               v10 = iconst.i64 0xffff_0000
 ;; @0040                               v11 = iadd v9, v10  ; v10 = 0xffff_0000
-;; @0040                               istore8 little region4 v3, v11
+;; @0040                               v12 = ireduce.i8 v3
+;; @0040                               store little region4 v12, v11
 ;; @0047                               jump block1
 ;;
 ;;                                 block1:
@@ -67,9 +68,10 @@
 ;; @004c                               v8 = iadd v7, v2
 ;; @004c                               v9 = iconst.i64 0xffff_0000
 ;; @004c                               v10 = iadd v8, v9  ; v9 = 0xffff_0000
-;; @004c                               v11 = uload8.i32 little region4 v10
+;; @004c                               v11 = load.i8 little region4 v10
+;; @004c                               v12 = uextend.i32 v11
 ;; @0053                               jump block1
 ;;
 ;;                                 block1:
-;; @0053                               return v11
+;; @0053                               return v12
 ;; }
diff --git a/tests/disas/load-store/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
index bbaa1989012e..9765e19157a2 100644
--- a/tests/disas/load-store/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -36,7 +36,8 @@
 ;; @0040                               v7 = iadd v6, v2
 ;; @0040                               v8 = iconst.i64 0
 ;; @0040                               v9 = select_spectre_guard v5, v8, v7  ; v8 = 0
-;; @0040                               istore8 little region4 v3, v9
+;; @0040                               v10 = ireduce.i8 v3
+;; @0040                               store little region4 v10, v9
 ;; @0043                               jump block1
 ;;
 ;;                                 block1:
@@ -61,9 +62,10 @@
 ;; @0048                               v6 = iadd v5, v2
 ;; @0048                               v7 = iconst.i64 0
 ;; @0048                               v8 = select_spectre_guard v4, v7, v6  ; v7 = 0
-;; @0048                               v9 = uload8.i32 little region4 v8
+;; @0048                               v9 = load.i8 little region4 v8
+;; @0048                               v10 = uextend.i32 v9
 ;; @004b                               jump block1
 ;;
 ;;                                 block1:
-;; @004b                               return v9
+;; @004b                               return v10
 ;; }
diff --git a/tests/disas/load-store/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 05f297b32bc8..ea1a3950ab44 100644
--- a/tests/disas/load-store/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -40,7 +40,8 @@
 ;; @0040                               v11 = iadd v9, v10  ; v10 = 4096
 ;; @0040                               v12 = iconst.i64 0
 ;; @0040                               v13 = select_spectre_guard v7, v12, v11  ; v12 = 0
-;; @0040                               istore8 little region4 v3, v13
+;; @0040                               v14 = ireduce.i8 v3
+;; @0040                               store little region4 v14, v13
 ;; @0044                               jump block1
 ;;
 ;;                                 block1:
@@ -69,9 +70,10 @@
 ;; @0049                               v10 = iadd v8, v9  ; v9 = 4096
 ;; @0049                               v11 = iconst.i64 0
 ;; @0049                               v12 = select_spectre_guard v6, v11, v10  ; v11 = 0
-;; @0049                               v13 = uload8.i32 little region4 v12
+;; @0049                               v13 = load.i8 little region4 v12
+;; @0049                               v14 = uextend.i32 v13
 ;; @004d                               jump block1
 ;;
 ;;                                 block1:
-;; @004d                               return v13
+;; @004d                               return v14
 ;; }
diff --git a/tests/disas/load-store/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index ad0cb5594e2e..c6de9d7132ac 100644
--- a/tests/disas/load-store/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -40,7 +40,8 @@
 ;; @0040                               v11 = iadd v9, v10  ; v10 = 0xffff_0000
 ;; @0040                               v12 = iconst.i64 0
 ;; @0040                               v13 = select_spectre_guard v7, v12, v11  ; v12 = 0
-;; @0040                               istore8 little region4 v3, v13
+;; @0040                               v14 = ireduce.i8 v3
+;; @0040                               store little region4 v14, v13
 ;; @0047                               jump block1
 ;;
 ;;                                 block1:
@@ -69,9 +70,10 @@
 ;; @004c                               v10 = iadd v8, v9  ; v9 = 0xffff_0000
 ;; @004c                               v11 = iconst.i64 0
 ;; @004c                               v12 = select_spectre_guard v6, v11, v10  ; v11 = 0
-;; @004c                               v13 = uload8.i32 little region4 v12
+;; @004c                               v13 = load.i8 little region4 v12
+;; @004c                               v14 = uextend.i32 v13
 ;; @0053                               jump block1
 ;;
 ;;                                 block1:
-;; @0053                               return v13
+;; @0053                               return v14
 ;; }
diff --git a/tests/disas/load-store/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
index 3efd391cd213..6274130fd333 100644
--- a/tests/disas/load-store/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
@@ -35,7 +35,8 @@
 ;; @0040                               trapnz v5, heap_oob
 ;; @0040                               v6 = load.i64 notrap aligned can_move region2 v0+56
 ;; @0040                               v7 = iadd v6, v2
-;; @0040                               istore8 little region4 v3, v7
+;; @0040                               v8 = ireduce.i8 v3
+;; @0040                               store little region4 v8, v7
 ;; @0043                               jump block1
 ;;
 ;;                                 block1:
@@ -59,9 +60,10 @@
 ;; @0048                               trapnz v4, heap_oob
 ;; @0048                               v5 = load.i64 notrap aligned can_move region2 v0+56
 ;; @0048                               v6 = iadd v5, v2
-;; @0048                               v7 = uload8.i32 little region4 v6
+;; @0048                               v7 = load.i8 little region4 v6
+;; @0048                               v8 = uextend.i32 v7
 ;; @004b                               jump block1
 ;;
 ;;                                 block1:
-;; @004b                               return v7
+;; @004b                               return v8
 ;; }
diff --git a/tests/disas/load-store/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
index 507ede1c3ddf..0ed4be8d59eb 100644
--- a/tests/disas/load-store/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -37,7 +37,8 @@
 ;; @0040                               v7 = iadd v6, v2
 ;; @0040                               v8 = iconst.i64 4096
 ;; @0040                               v9 = iadd v7, v8  ; v8 = 4096
-;; @0040                               istore8 little region4 v3, v9
+;; @0040                               v10 = ireduce.i8 v3
+;; @0040                               store little region4 v10, v9
 ;; @0044                               jump block1
 ;;
 ;;                                 block1:
@@ -63,9 +64,10 @@
 ;; @0049                               v6 = iadd v5, v2
 ;; @0049                               v7 = iconst.i64 4096
 ;; @0049                               v8 = iadd v6, v7  ; v7 = 4096
-;; @0049                               v9 = uload8.i32 little region4 v8
+;; @0049                               v9 = load.i8 little region4 v8
+;; @0049                               v10 = uextend.i32 v9
 ;; @004d                               jump block1
 ;;
 ;;                                 block1:
-;; @004d                               return v9
+;; @004d                               return v10
 ;; }
diff --git a/tests/disas/load-store/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index ce7779c48c8d..85279b91caf5 100644
--- a/tests/disas/load-store/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -37,7 +37,8 @@
 ;; @0040                               v7 = iadd v6, v2
 ;; @0040                               v8 = iconst.i64 0xffff_0000
 ;; @0040                               v9 = iadd v7, v8  ; v8 = 0xffff_0000
-;; @0040                               istore8 little region4 v3, v9
+;; @0040                               v10 = ireduce.i8 v3
+;; @0040                               store little region4 v10, v9
 ;; @0047                               jump block1
 ;;
 ;;                                 block1:
@@ -63,9 +64,10 @@
 ;; @004c                               v6 = iadd v5, v2
 ;; @004c                               v7 = iconst.i64 0xffff_0000
 ;; @004c                               v8 = iadd v6, v7  ; v7 = 0xffff_0000
-;; @004c                               v9 = uload8.i32 little region4 v8
+;; @004c                               v9 = load.i8 little region4 v8
+;; @004c                               v10 = uextend.i32 v9
 ;; @0053                               jump block1
 ;;
 ;;                                 block1:
-;; @0053                               return v9
+;; @0053                               return v10
 ;; }
diff --git a/tests/disas/load-store/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index 2f31540c4433..9ca6f4440369 100644
--- a/tests/disas/load-store/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -36,7 +36,8 @@
 ;; @0040                               v7 = iadd v6, v2
 ;; @0040                               v8 = iconst.i64 0
 ;; @0040                               v9 = select_spectre_guard v5, v8, v7  ; v8 = 0
-;; @0040                               istore8 little region4 v3, v9
+;; @0040                               v10 = ireduce.i8 v3
+;; @0040                               store little region4 v10, v9
 ;; @0043                               jump block1
 ;;
 ;;                                 block1:
@@ -61,9 +62,10 @@
 ;; @0048                               v6 = iadd v5, v2
 ;; @0048                               v7 = iconst.i64 0
 ;; @0048                               v8 = select_spectre_guard v4, v7, v6  ; v7 = 0
-;; @0048                               v9 = uload8.i32 little region4 v8
+;; @0048                               v9 = load.i8 little region4 v8
+;; @0048                               v10 = uextend.i32 v9
 ;; @004b                               jump block1
 ;;
 ;;                                 block1:
-;; @004b                               return v9
+;; @004b                               return v10
 ;; }
diff --git a/tests/disas/load-store/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index 8713c6e348e7..4e14217be1a8 100644
--- a/tests/disas/load-store/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -38,7 +38,8 @@
 ;; @0040                               v9 = iadd v7, v8  ; v8 = 4096
 ;; @0040                               v10 = iconst.i64 0
 ;; @0040                               v11 = select_spectre_guard v5, v10, v9  ; v10 = 0
-;; @0040                               istore8 little region4 v3, v11
+;; @0040                               v12 = ireduce.i8 v3
+;; @0040                               store little region4 v12, v11
 ;; @0044                               jump block1
 ;;
 ;;                                 block1:
@@ -65,9 +66,10 @@
 ;; @0049                               v8 = iadd v6, v7  ; v7 = 4096
 ;; @0049                               v9 = iconst.i64 0
 ;; @0049                               v10 = select_spectre_guard v4, v9, v8  ; v9 = 0
-;; @0049                               v11 = uload8.i32 little region4 v10
+;; @0049                               v11 = load.i8 little region4 v10
+;; @0049                               v12 = uextend.i32 v11
 ;; @004d                               jump block1
 ;;
 ;;                                 block1:
-;; @004d                               return v11
+;; @004d                               return v12
 ;; }
diff --git a/tests/disas/load-store/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index ab05e756ad21..3cee1259b27e 100644
--- a/tests/disas/load-store/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -38,7 +38,8 @@
 ;; @0040                               v9 = iadd v7, v8  ; v8 = 0xffff_0000
 ;; @0040                               v10 = iconst.i64 0
 ;; @0040                               v11 = select_spectre_guard v5, v10, v9  ; v10 = 0
-;; @0040                               istore8 little region4 v3, v11
+;; @0040                               v12 = ireduce.i8 v3
+;; @0040                               store little region4 v12, v11
 ;; @0047                               jump block1
 ;;
 ;;                                 block1:
@@ -65,9 +66,10 @@
 ;; @004c                               v8 = iadd v6, v7  ; v7 = 0xffff_0000
 ;; @004c                               v9 = iconst.i64 0
 ;; @004c                               v10 = select_spectre_guard v4, v9, v8  ; v9 = 0
-;; @004c                               v11 = uload8.i32 little region4 v10
+;; @004c                               v11 = load.i8 little region4 v10
+;; @004c                               v12 = uextend.i32 v11
 ;; @0053                               jump block1
 ;;
 ;;                                 block1:
-;; @0053                               return v11
+;; @0053                               return v12
 ;; }
diff --git a/tests/disas/load-store/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
index 0f94b01c78b1..1c22d4dbd492 100644
--- a/tests/disas/load-store/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
@@ -33,7 +33,8 @@
 ;; @0040                               v4 = uextend.i64 v2
 ;; @0040                               v5 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0040                               v6 = iadd v5, v4
-;; @0040                               istore8 little region4 v3, v6
+;; @0040                               v7 = ireduce.i8 v3
+;; @0040                               store little region4 v7, v6
 ;; @0043                               jump block1
 ;;
 ;;                                 block1:
@@ -55,9 +56,10 @@
 ;; @0048                               v3 = uextend.i64 v2
 ;; @0048                               v4 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0048                               v5 = iadd v4, v3
-;; @0048                               v6 = uload8.i32 little region4 v5
+;; @0048                               v6 = load.i8 little region4 v5
+;; @0048                               v7 = uextend.i32 v6
 ;; @004b                               jump block1
 ;;
 ;;                                 block1:
-;; @004b                               return v6
+;; @004b                               return v7
 ;; }
diff --git a/tests/disas/load-store/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
index cb2a1f0d6b4d..15c40f2c51ab 100644
--- a/tests/disas/load-store/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -38,7 +38,8 @@
 ;; @0040                               v8 = iadd v7, v4
 ;; @0040                               v9 = iconst.i64 4096
 ;; @0040                               v10 = iadd v8, v9  ; v9 = 4096
-;; @0040                               istore8 little region4 v3, v10
+;; @0040                               v11 = ireduce.i8 v3
+;; @0040                               store little region4 v11, v10
 ;; @0044                               jump block1
 ;;
 ;;                                 block1:
@@ -65,9 +66,10 @@
 ;; @0049                               v7 = iadd v6, v3
 ;; @0049                               v8 = iconst.i64 4096
 ;; @0049                               v9 = iadd v7, v8  ; v8 = 4096
-;; @0049                               v10 = uload8.i32 little region4 v9
+;; @0049                               v10 = load.i8 little region4 v9
+;; @0049                               v11 = uextend.i32 v10
 ;; @004d                               jump block1
 ;;
 ;;                                 block1:
-;; @004d                               return v10
+;; @004d                               return v11
 ;; }
diff --git a/tests/disas/load-store/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index fcb393ad1b77..23209180d1b9 100644
--- a/tests/disas/load-store/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -38,7 +38,8 @@
 ;; @0040                               v8 = iadd v7, v4
 ;; @0040                               v9 = iconst.i64 0xffff_0000
 ;; @0040                               v10 = iadd v8, v9  ; v9 = 0xffff_0000
-;; @0040                               istore8 little region4 v3, v10
+;; @0040                               v11 = ireduce.i8 v3
+;; @0040                               store little region4 v11, v10
 ;; @0047                               jump block1
 ;;
 ;;                                 block1:
@@ -65,9 +66,10 @@
 ;; @004c                               v7 = iadd v6, v3
 ;; @004c                               v8 = iconst.i64 0xffff_0000
 ;; @004c                               v9 = iadd v7, v8  ; v8 = 0xffff_0000
-;; @004c                               v10 = uload8.i32 little region4 v9
+;; @004c                               v10 = load.i8 little region4 v9
+;; @004c                               v11 = uextend.i32 v10
 ;; @0053                               jump block1
 ;;
 ;;                                 block1:
-;; @0053                               return v10
+;; @0053                               return v11
 ;; }
diff --git a/tests/disas/load-store/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 8c4aee640bf6..62a8409b71c5 100644
--- a/tests/disas/load-store/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -33,7 +33,8 @@
 ;; @0040                               v4 = uextend.i64 v2
 ;; @0040                               v5 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0040                               v6 = iadd v5, v4
-;; @0040                               istore8 little region4 v3, v6
+;; @0040                               v7 = ireduce.i8 v3
+;; @0040                               store little region4 v7, v6
 ;; @0043                               jump block1
 ;;
 ;;                                 block1:
@@ -55,9 +56,10 @@
 ;; @0048                               v3 = uextend.i64 v2
 ;; @0048                               v4 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0048                               v5 = iadd v4, v3
-;; @0048                               v6 = uload8.i32 little region4 v5
+;; @0048                               v6 = load.i8 little region4 v5
+;; @0048                               v7 = uextend.i32 v6
 ;; @004b                               jump block1
 ;;
 ;;                                 block1:
-;; @004b                               return v6
+;; @004b                               return v7
 ;; }
diff --git a/tests/disas/load-store/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index a96c34c825c3..e84c4f7ef85a 100644
--- a/tests/disas/load-store/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -39,7 +39,8 @@
 ;; @0040                               v10 = iadd v8, v9  ; v9 = 4096
 ;; @0040                               v11 = iconst.i64 0
 ;; @0040                               v12 = select_spectre_guard v6, v11, v10  ; v11 = 0
-;; @0040                               istore8 little region4 v3, v12
+;; @0040                               v13 = ireduce.i8 v3
+;; @0040                               store little region4 v13, v12
 ;; @0044                               jump block1
 ;;
 ;;                                 block1:
@@ -67,9 +68,10 @@
 ;; @0049                               v9 = iadd v7, v8  ; v8 = 4096
 ;; @0049                               v10 = iconst.i64 0
 ;; @0049                               v11 = select_spectre_guard v5, v10, v9  ; v10 = 0
-;; @0049                               v12 = uload8.i32 little region4 v11
+;; @0049                               v12 = load.i8 little region4 v11
+;; @0049                               v13 = uextend.i32 v12
 ;; @004d                               jump block1
 ;;
 ;;                                 block1:
-;; @004d                               return v12
+;; @004d                               return v13
 ;; }
diff --git a/tests/disas/load-store/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 35d887fdcad7..691b6e04f8f2 100644
--- a/tests/disas/load-store/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -39,7 +39,8 @@
 ;; @0040                               v10 = iadd v8, v9  ; v9 = 0xffff_0000
 ;; @0040                               v11 = iconst.i64 0
 ;; @0040                               v12 = select_spectre_guard v6, v11, v10  ; v11 = 0
-;; @0040                               istore8 little region4 v3, v12
+;; @0040                               v13 = ireduce.i8 v3
+;; @0040                               store little region4 v13, v12
 ;; @0047                               jump block1
 ;;
 ;;                                 block1:
@@ -67,9 +68,10 @@
 ;; @004c                               v9 = iadd v7, v8  ; v8 = 0xffff_0000
 ;; @004c                               v10 = iconst.i64 0
 ;; @004c                               v11 = select_spectre_guard v5, v10, v9  ; v10 = 0
-;; @004c                               v12 = uload8.i32 little region4 v11
+;; @004c                               v12 = load.i8 little region4 v11
+;; @004c                               v13 = uextend.i32 v12
 ;; @0053                               jump block1
 ;;
 ;;                                 block1:
-;; @0053                               return v12
+;; @0053                               return v13
 ;; }
diff --git a/tests/disas/load-store/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
index 2e814f514d46..cfabb3bf3da1 100644
--- a/tests/disas/load-store/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
@@ -33,7 +33,8 @@
 ;; @0040                               v4 = uextend.i64 v2
 ;; @0040                               v5 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0040                               v6 = iadd v5, v4
-;; @0040                               istore8 little region4 v3, v6
+;; @0040                               v7 = ireduce.i8 v3
+;; @0040                               store little region4 v7, v6
 ;; @0043                               jump block1
 ;;
 ;;                                 block1:
@@ -55,9 +56,10 @@
 ;; @0048                               v3 = uextend.i64 v2
 ;; @0048                               v4 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0048                               v5 = iadd v4, v3
-;; @0048                               v6 = uload8.i32 little region4 v5
+;; @0048                               v6 = load.i8 little region4 v5
+;; @0048                               v7 = uextend.i32 v6
 ;; @004b                               jump block1
 ;;
 ;;                                 block1:
-;; @004b                               return v6
+;; @004b                               return v7
 ;; }
diff --git a/tests/disas/load-store/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
index 7be8641badaa..feb663c4f4bd 100644
--- a/tests/disas/load-store/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -35,7 +35,8 @@
 ;; @0040                               v6 = iadd v5, v4
 ;; @0040                               v7 = iconst.i64 4096
 ;; @0040                               v8 = iadd v6, v7  ; v7 = 4096
-;; @0040                               istore8 little region4 v3, v8
+;; @0040                               v9 = ireduce.i8 v3
+;; @0040                               store little region4 v9, v8
 ;; @0044                               jump block1
 ;;
 ;;                                 block1:
@@ -59,9 +60,10 @@
 ;; @0049                               v5 = iadd v4, v3
 ;; @0049                               v6 = iconst.i64 4096
 ;; @0049                               v7 = iadd v5, v6  ; v6 = 4096
-;; @0049                               v8 = uload8.i32 little region4 v7
+;; @0049                               v8 = load.i8 little region4 v7
+;; @0049                               v9 = uextend.i32 v8
 ;; @004d                               jump block1
 ;;
 ;;                                 block1:
-;; @004d                               return v8
+;; @004d                               return v9
 ;; }
diff --git a/tests/disas/load-store/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 17ed8a94b0e2..86c521212e59 100644
--- a/tests/disas/load-store/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -35,7 +35,8 @@
 ;; @0040                               v6 = iadd v5, v4
 ;; @0040                               v7 = iconst.i64 0xffff_0000
 ;; @0040                               v8 = iadd v6, v7  ; v7 = 0xffff_0000
-;; @0040                               istore8 little region4 v3, v8
+;; @0040                               v9 = ireduce.i8 v3
+;; @0040                               store little region4 v9, v8
 ;; @0047                               jump block1
 ;;
 ;;                                 block1:
@@ -59,9 +60,10 @@
 ;; @004c                               v5 = iadd v4, v3
 ;; @004c                               v6 = iconst.i64 0xffff_0000
 ;; @004c                               v7 = iadd v5, v6  ; v6 = 0xffff_0000
-;; @004c                               v8 = uload8.i32 little region4 v7
+;; @004c                               v8 = load.i8 little region4 v7
+;; @004c                               v9 = uextend.i32 v8
 ;; @0053                               jump block1
 ;;
 ;;                                 block1:
-;; @0053                               return v8
+;; @0053                               return v9
 ;; }
diff --git a/tests/disas/load-store/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index 5edc9f61f379..06bd5ebb1445 100644
--- a/tests/disas/load-store/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -33,7 +33,8 @@
 ;; @0040                               v4 = uextend.i64 v2
 ;; @0040                               v5 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0040                               v6 = iadd v5, v4
-;; @0040                               istore8 little region4 v3, v6
+;; @0040                               v7 = ireduce.i8 v3
+;; @0040                               store little region4 v7, v6
 ;; @0043                               jump block1
 ;;
 ;;                                 block1:
@@ -55,9 +56,10 @@
 ;; @0048                               v3 = uextend.i64 v2
 ;; @0048                               v4 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0048                               v5 = iadd v4, v3
-;; @0048                               v6 = uload8.i32 little region4 v5
+;; @0048                               v6 = load.i8 little region4 v5
+;; @0048                               v7 = uextend.i32 v6
 ;; @004b                               jump block1
 ;;
 ;;                                 block1:
-;; @004b                               return v6
+;; @004b                               return v7
 ;; }
diff --git a/tests/disas/load-store/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index 2a60284153fe..7350ab1bcab3 100644
--- a/tests/disas/load-store/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -35,7 +35,8 @@
 ;; @0040                               v6 = iadd v5, v4
 ;; @0040                               v7 = iconst.i64 4096
 ;; @0040                               v8 = iadd v6, v7  ; v7 = 4096
-;; @0040                               istore8 little region4 v3, v8
+;; @0040                               v9 = ireduce.i8 v3
+;; @0040                               store little region4 v9, v8
 ;; @0044                               jump block1
 ;;
 ;;                                 block1:
@@ -59,9 +60,10 @@
 ;; @0049                               v5 = iadd v4, v3
 ;; @0049                               v6 = iconst.i64 4096
 ;; @0049                               v7 = iadd v5, v6  ; v6 = 4096
-;; @0049                               v8 = uload8.i32 little region4 v7
+;; @0049                               v8 = load.i8 little region4 v7
+;; @0049                               v9 = uextend.i32 v8
 ;; @004d                               jump block1
 ;;
 ;;                                 block1:
-;; @004d                               return v8
+;; @004d                               return v9
 ;; }
diff --git a/tests/disas/load-store/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 3f00817b31be..65ae3a9ac067 100644
--- a/tests/disas/load-store/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -35,7 +35,8 @@
 ;; @0040                               v6 = iadd v5, v4
 ;; @0040                               v7 = iconst.i64 0xffff_0000
 ;; @0040                               v8 = iadd v6, v7  ; v7 = 0xffff_0000
-;; @0040                               istore8 little region4 v3, v8
+;; @0040                               v9 = ireduce.i8 v3
+;; @0040                               store little region4 v9, v8
 ;; @0047                               jump block1
 ;;
 ;;                                 block1:
@@ -59,9 +60,10 @@
 ;; @004c                               v5 = iadd v4, v3
 ;; @004c                               v6 = iconst.i64 0xffff_0000
 ;; @004c                               v7 = iadd v5, v6  ; v6 = 0xffff_0000
-;; @004c                               v8 = uload8.i32 little region4 v7
+;; @004c                               v8 = load.i8 little region4 v7
+;; @004c                               v9 = uextend.i32 v8
 ;; @0053                               jump block1
 ;;
 ;;                                 block1:
-;; @0053                               return v8
+;; @0053                               return v9
 ;; }
diff --git a/tests/disas/load-store/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
index de8517a79ecf..37005f7b82bb 100644
--- a/tests/disas/load-store/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
@@ -35,7 +35,8 @@
 ;; @0040                               trapnz v5, heap_oob
 ;; @0040                               v6 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0040                               v7 = iadd v6, v2
-;; @0040                               istore8 little region4 v3, v7
+;; @0040                               v8 = ireduce.i8 v3
+;; @0040                               store little region4 v8, v7
 ;; @0043                               jump block1
 ;;
 ;;                                 block1:
@@ -59,9 +60,10 @@
 ;; @0048                               trapnz v4, heap_oob
 ;; @0048                               v5 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0048                               v6 = iadd v5, v2
-;; @0048                               v7 = uload8.i32 little region4 v6
+;; @0048                               v7 = load.i8 little region4 v6
+;; @0048                               v8 = uextend.i32 v7
 ;; @004b                               jump block1
 ;;
 ;;                                 block1:
-;; @004b                               return v7
+;; @004b                               return v8
 ;; }
diff --git a/tests/disas/load-store/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
index 1aa7d20d51b7..0f08b2efc7a8 100644
--- a/tests/disas/load-store/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -37,7 +37,8 @@
 ;; @0040                               v7 = iadd v6, v2
 ;; @0040                               v8 = iconst.i64 4096
 ;; @0040                               v9 = iadd v7, v8  ; v8 = 4096
-;; @0040                               istore8 little region4 v3, v9
+;; @0040                               v10 = ireduce.i8 v3
+;; @0040                               store little region4 v10, v9
 ;; @0044                               jump block1
 ;;
 ;;                                 block1:
@@ -63,9 +64,10 @@
 ;; @0049                               v6 = iadd v5, v2
 ;; @0049                               v7 = iconst.i64 4096
 ;; @0049                               v8 = iadd v6, v7  ; v7 = 4096
-;; @0049                               v9 = uload8.i32 little region4 v8
+;; @0049                               v9 = load.i8 little region4 v8
+;; @0049                               v10 = uextend.i32 v9
 ;; @004d                               jump block1
 ;;
 ;;                                 block1:
-;; @004d                               return v9
+;; @004d                               return v10
 ;; }
diff --git a/tests/disas/load-store/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 589727148ec8..700daf54f5db 100644
--- a/tests/disas/load-store/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -37,7 +37,8 @@
 ;; @0040                               v7 = iadd v6, v2
 ;; @0040                               v8 = iconst.i64 0xffff_0000
 ;; @0040                               v9 = iadd v7, v8  ; v8 = 0xffff_0000
-;; @0040                               istore8 little region4 v3, v9
+;; @0040                               v10 = ireduce.i8 v3
+;; @0040                               store little region4 v10, v9
 ;; @0047                               jump block1
 ;;
 ;;                                 block1:
@@ -63,9 +64,10 @@
 ;; @004c                               v6 = iadd v5, v2
 ;; @004c                               v7 = iconst.i64 0xffff_0000
 ;; @004c                               v8 = iadd v6, v7  ; v7 = 0xffff_0000
-;; @004c                               v9 = uload8.i32 little region4 v8
+;; @004c                               v9 = load.i8 little region4 v8
+;; @004c                               v10 = uextend.i32 v9
 ;; @0053                               jump block1
 ;;
 ;;                                 block1:
-;; @0053                               return v9
+;; @0053                               return v10
 ;; }
diff --git a/tests/disas/load-store/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 86964227871b..0d078c27e530 100644
--- a/tests/disas/load-store/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -36,7 +36,8 @@
 ;; @0040                               v7 = iadd v6, v2
 ;; @0040                               v8 = iconst.i64 0
 ;; @0040                               v9 = select_spectre_guard v5, v8, v7  ; v8 = 0
-;; @0040                               istore8 little region4 v3, v9
+;; @0040                               v10 = ireduce.i8 v3
+;; @0040                               store little region4 v10, v9
 ;; @0043                               jump block1
 ;;
 ;;                                 block1:
@@ -61,9 +62,10 @@
 ;; @0048                               v6 = iadd v5, v2
 ;; @0048                               v7 = iconst.i64 0
 ;; @0048                               v8 = select_spectre_guard v4, v7, v6  ; v7 = 0
-;; @0048                               v9 = uload8.i32 little region4 v8
+;; @0048                               v9 = load.i8 little region4 v8
+;; @0048                               v10 = uextend.i32 v9
 ;; @004b                               jump block1
 ;;
 ;;                                 block1:
-;; @004b                               return v9
+;; @004b                               return v10
 ;; }
diff --git a/tests/disas/load-store/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 3c1efc83ad8e..16fa7de793b4 100644
--- a/tests/disas/load-store/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -38,7 +38,8 @@
 ;; @0040                               v9 = iadd v7, v8  ; v8 = 4096
 ;; @0040                               v10 = iconst.i64 0
 ;; @0040                               v11 = select_spectre_guard v5, v10, v9  ; v10 = 0
-;; @0040                               istore8 little region4 v3, v11
+;; @0040                               v12 = ireduce.i8 v3
+;; @0040                               store little region4 v12, v11
 ;; @0044                               jump block1
 ;;
 ;;                                 block1:
@@ -65,9 +66,10 @@
 ;; @0049                               v8 = iadd v6, v7  ; v7 = 4096
 ;; @0049                               v9 = iconst.i64 0
 ;; @0049                               v10 = select_spectre_guard v4, v9, v8  ; v9 = 0
-;; @0049                               v11 = uload8.i32 little region4 v10
+;; @0049                               v11 = load.i8 little region4 v10
+;; @0049                               v12 = uextend.i32 v11
 ;; @004d                               jump block1
 ;;
 ;;                                 block1:
-;; @004d                               return v11
+;; @004d                               return v12
 ;; }
diff --git a/tests/disas/load-store/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index c5b9a07671db..68a37d81a3b3 100644
--- a/tests/disas/load-store/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -38,7 +38,8 @@
 ;; @0040                               v9 = iadd v7, v8  ; v8 = 0xffff_0000
 ;; @0040                               v10 = iconst.i64 0
 ;; @0040                               v11 = select_spectre_guard v5, v10, v9  ; v10 = 0
-;; @0040                               istore8 little region4 v3, v11
+;; @0040                               v12 = ireduce.i8 v3
+;; @0040                               store little region4 v12, v11
 ;; @0047                               jump block1
 ;;
 ;;                                 block1:
@@ -65,9 +66,10 @@
 ;; @004c                               v8 = iadd v6, v7  ; v7 = 0xffff_0000
 ;; @004c                               v9 = iconst.i64 0
 ;; @004c                               v10 = select_spectre_guard v4, v9, v8  ; v9 = 0
-;; @004c                               v11 = uload8.i32 little region4 v10
+;; @004c                               v11 = load.i8 little region4 v10
+;; @004c                               v12 = uextend.i32 v11
 ;; @0053                               jump block1
 ;;
 ;;                                 block1:
-;; @0053                               return v11
+;; @0053                               return v12
 ;; }
diff --git a/tests/disas/load-store/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
index 1ae5ed273b9c..1c00c8ebe152 100644
--- a/tests/disas/load-store/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
@@ -35,7 +35,8 @@
 ;; @0040                               trapnz v5, heap_oob
 ;; @0040                               v6 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0040                               v7 = iadd v6, v2
-;; @0040                               istore8 little region4 v3, v7
+;; @0040                               v8 = ireduce.i8 v3
+;; @0040                               store little region4 v8, v7
 ;; @0043                               jump block1
 ;;
 ;;                                 block1:
@@ -59,9 +60,10 @@
 ;; @0048                               trapnz v4, heap_oob
 ;; @0048                               v5 = load.i64 notrap aligned readonly can_move region2 v0+56
 ;; @0048                               v6 = iadd v5, v2
-;; @0048                               v7 = uload8.i32 little region4 v6
+;; @0048                               v7 = load.i8 little region4 v6
+;; @0048                               v8 = uextend.i32 v7
 ;; @004b                               jump block1
 ;;
 ;;                                 block1:
-;; @004b                               return v7
+;; @004b                               return v8
 ;; }
diff --git a/tests/disas/load-store/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
index dd668aace62c..e8830929fec4 100644
--- a/tests/disas/load-store/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -37,7 +37,8 @@
 ;; @0040                               v7 = iadd v6, v2
 ;; @0040                               v8 = iconst.i64 4096
 ;; @0040                               v9 = iadd v7, v8  ; v8 = 4096
-;; @0040                               istore8 little region4 v3, v9
+;; @0040                               v10 = ireduce.i8 v3
+;; @0040                               store little region4 v10, v9
 ;; @0044                               jump block1
 ;;
 ;;                                 block1:
@@ -63,9 +64,10 @@
 ;; @0049                               v6 = iadd v5, v2
 ;; @0049                               v7 = iconst.i64 4096
 ;; @0049                               v8 = iadd v6, v7  ; v7 = 4096
-;; @0049                               v9 = uload8.i32 little region4 v8
+;; @0049                               v9 = load.i8 little region4 v8
+;; @0049                               v10 = uextend.i32 v9
 ;; @004d                               jump block1
 ;;
 ;;                                 block1:
-;; @004d                               return v9
+;; @004d                               return v10
 ;; }
diff --git a/tests/disas/load-store/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index fc3ca45ece88..04878d957fca 100644
--- a/tests/disas/load-store/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -37,7 +37,8 @@
 ;; @0040                               v7 = iadd v6, v2
 ;; @0040                               v8 = iconst.i64 0xffff_0000
 ;; @0040                               v9 = iadd v7, v8  ; v8 = 0xffff_0000
-;; @0040                               istore8 little region4 v3, v9
+;; @0040                               v10 = ireduce.i8 v3
+;; @0040                               store little region4 v10, v9
 ;; @0047                               jump block1
 ;;
 ;;                                 block1:
@@ -63,9 +64,10 @@
 ;; @004c                               v6 = iadd v5, v2
 ;; @004c                               v7 = iconst.i64 0xffff_0000
 ;; @004c                               v8 = iadd v6, v7  ; v7 = 0xffff_0000
-;; @004c                               v9 = uload8.i32 little region4 v8
+;; @004c                               v9 = load.i8 little region4 v8
+;; @004c                               v10 = uextend.i32 v9
 ;; @0053                               jump block1
 ;;
 ;;                                 block1:
-;; @0053                               return v9
+;; @0053                               return v10
 ;; }
diff --git a/tests/disas/load-store/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index 748ef00c7f8b..3802d80895a5 100644
--- a/tests/disas/load-store/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -36,7 +36,8 @@
 ;; @0040                               v7 = iadd v6, v2
 ;; @0040                               v8 = iconst.i64 0
 ;; @0040                               v9 = select_spectre_guard v5, v8, v7  ; v8 = 0
-;; @0040                               istore8 little region4 v3, v9
+;; @0040                               v10 = ireduce.i8 v3
+;; @0040                               store little region4 v10, v9
 ;; @0043                               jump block1
 ;;
 ;;                                 block1:
@@ -61,9 +62,10 @@
 ;; @0048                               v6 = iadd v5, v2
 ;; @0048                               v7 = iconst.i64 0
 ;; @0048                               v8 = select_spectre_guard v4, v7, v6  ; v7 = 0
-;; @0048                               v9 = uload8.i32 little region4 v8
+;; @0048                               v9 = load.i8 little region4 v8
+;; @0048                               v10 = uextend.i32 v9
 ;; @004b                               jump block1
 ;;
 ;;                                 block1:
-;; @004b                               return v9
+;; @004b                               return v10
 ;; }
diff --git a/tests/disas/load-store/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index ca8b58e5807b..9a1c0848d2fa 100644
--- a/tests/disas/load-store/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -38,7 +38,8 @@
 ;; @0040                               v9 = iadd v7, v8  ; v8 = 4096
 ;; @0040                               v10 = iconst.i64 0
 ;; @0040                               v11 = select_spectre_guard v5, v10, v9  ; v10 = 0
-;; @0040                               istore8 little region4 v3, v11
+;; @0040                               v12 = ireduce.i8 v3
+;; @0040                               store little region4 v12, v11
 ;; @0044                               jump block1
 ;;
 ;;                                 block1:
@@ -65,9 +66,10 @@
 ;; @0049                               v8 = iadd v6, v7  ; v7 = 4096
 ;; @0049                               v9 = iconst.i64 0
 ;; @0049                               v10 = select_spectre_guard v4, v9, v8  ; v9 = 0
-;; @0049                               v11 = uload8.i32 little region4 v10
+;; @0049                               v11 = load.i8 little region4 v10
+;; @0049                               v12 = uextend.i32 v11
 ;; @004d                               jump block1
 ;;
 ;;                                 block1:
-;; @004d                               return v11
+;; @004d                               return v12
 ;; }
diff --git a/tests/disas/load-store/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 4956df8b43e4..5895254da8c7 100644
--- a/tests/disas/load-store/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -38,7 +38,8 @@
 ;; @0040                               v9 = iadd v7, v8  ; v8 = 0xffff_0000
 ;; @0040                               v10 = iconst.i64 0
 ;; @0040                               v11 = select_spectre_guard v5, v10, v9  ; v10 = 0
-;; @0040                               istore8 little region4 v3, v11
+;; @0040                               v12 = ireduce.i8 v3
+;; @0040                               store little region4 v12, v11
 ;; @0047                               jump block1
 ;;
 ;;                                 block1:
@@ -65,9 +66,10 @@
 ;; @004c                               v8 = iadd v6, v7  ; v7 = 0xffff_0000
 ;; @004c                               v9 = iconst.i64 0
 ;; @004c                               v10 = select_spectre_guard v4, v9, v8  ; v9 = 0
-;; @004c                               v11 = uload8.i32 little region4 v10
+;; @004c                               v11 = load.i8 little region4 v10
+;; @004c                               v12 = uextend.i32 v11
 ;; @0053                               jump block1
 ;;
 ;;                                 block1:
-;; @0053                               return v11
+;; @0053                               return v12
 ;; }
diff --git a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
index a3bd06af9ef0..29ffe07a532b 100644
--- a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
@@ -48,7 +48,8 @@
 ;;       .byte   0x00, 0x00, 0x00, 0x00
 ;;       ld      a0, 0x38(a0)
 ;;       add     a0, a0, a2
-;;       lbu     a0, 0(a0)
+;;       lb      a0, 0(a0)
+;;       andi    a0, a0, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
index 8daf6bb2a48a..4405caf6af14 100644
--- a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -46,19 +46,20 @@
 ;;       sd      ra, 8(sp)
 ;;       sd      s0, 0(sp)
 ;;       mv      s0, sp
-;;       ld      a1, 0x40(a0)
-;;       slli    a2, a2, 0x20
-;;       srli    a2, a2, 0x20
-;;       lui     a3, 1
-;;       addi    a3, a3, 1
-;;       sub     a1, a1, a3
-;;       bgeu    a1, a2, 8
+;;       ld      a4, 0x40(a0)
+;;       slli    a1, a2, 0x20
+;;       srli    a3, a1, 0x20
+;;       lui     a1, 1
+;;       addi    a5, a1, 1
+;;       sub     a2, a4, a5
+;;       bgeu    a2, a3, 8
 ;;       .byte   0x00, 0x00, 0x00, 0x00
-;;       ld      a3, 0x38(a0)
-;;       add     a2, a3, a2
+;;       ld      a4, 0x38(a0)
+;;       add     a3, a4, a3
 ;;       lui     t6, 1
-;;       add     t6, t6, a2
-;;       lbu     a0, 0(t6)
+;;       add     t6, t6, a3
+;;       lb      a3, 0(t6)
+;;       andi    a0, a3, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index c2c1bdeef847..9029137daf08 100644
--- a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -51,25 +51,27 @@
 ;;       sd      ra, 8(sp)
 ;;       sd      s0, 0(sp)
 ;;       mv      s0, sp
-;;       slli    a2, a2, 0x20
-;;       srli    a4, a2, 0x20
-;;       auipc   a3, 0
-;;       ld      a3, 0x48(a3)
-;;       add     a3, a4, a3
-;;       bgeu    a3, a4, 8
+;;       slli    a3, a2, 0x20
+;;       srli    a5, a3, 0x20
+;;       auipc   a4, 0
+;;       ld      a4, 0x50(a4)
+;;       add     a4, a5, a4
+;;       bgeu    a4, a5, 8
 ;;       .byte   0x00, 0x00, 0x00, 0x00
-;;       ld      a5, 0x40(a0)
-;;       bgeu    a5, a3, 8
+;;       ld      a1, 0x40(a0)
+;;       bgeu    a1, a4, 8
 ;;       .byte   0x00, 0x00, 0x00, 0x00
-;;       ld      a5, 0x38(a0)
-;;       add     a5, a5, a4
-;;       lui     a4, 0xffff
-;;       slli    a0, a4, 4
-;;       add     a5, a5, a0
-;;       lbu     a0, 0(a5)
+;;       ld      a0, 0x38(a0)
+;;       add     a0, a0, a5
+;;       lui     a5, 0xffff
+;;       slli    a1, a5, 4
+;;       add     a0, a0, a1
+;;       lb      a0, 0(a0)
+;;       andi    a0, a0, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
 ;;       ret
+;;       .byte   0x00, 0x00, 0x00, 0x00
 ;;       .byte   0x01, 0x00, 0xff, 0xff
 ;;       .byte   0x00, 0x00, 0x00, 0x00
diff --git a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 0e3b4d265439..ca6319a0c732 100644
--- a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -44,17 +44,18 @@
 ;;       sd      ra, 8(sp)
 ;;       sd      s0, 0(sp)
 ;;       mv      s0, sp
-;;       ld      a4, 0x40(a0)
-;;       ld      a3, 0x38(a0)
-;;       slli    a2, a2, 0x20
-;;       srli    a5, a2, 0x20
-;;       sltu    a2, a5, a4
-;;       xori    a4, a2, 1
-;;       add     a3, a3, a5
-;;       neg     a1, a4
-;;       not     a4, a1
-;;       and     a5, a3, a4
-;;       lbu     a0, 0(a5)
+;;       ld      a5, 0x40(a0)
+;;       ld      a4, 0x38(a0)
+;;       slli    a3, a2, 0x20
+;;       srli    a0, a3, 0x20
+;;       sltu    a3, a0, a5
+;;       xori    a5, a3, 1
+;;       add     a4, a4, a0
+;;       neg     a2, a5
+;;       not     a5, a2
+;;       and     a0, a4, a5
+;;       lb      a4, 0(a0)
+;;       andi    a0, a4, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index f83e0d069978..4c158aede85c 100644
--- a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -59,10 +59,11 @@
 ;;       add     a0, a0, a2
 ;;       lui     a2, 1
 ;;       add     a0, a0, a2
-;;       neg     a5, a1
-;;       not     a1, a5
+;;       neg     a1, a1
+;;       not     a1, a1
 ;;       and     a0, a0, a1
-;;       lbu     a0, 0(a0)
+;;       lb      a0, 0(a0)
+;;       andi    a0, a0, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 924ca2c55163..80e1a8fbf874 100644
--- a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -73,11 +73,11 @@
 ;;       neg     a1, a1
 ;;       not     a1, a1
 ;;       and     a0, a0, a1
-;;       lbu     a0, 0(a0)
+;;       lb      a0, 0(a0)
+;;       andi    a0, a0, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
 ;;       ret
-;;       .byte   0x00, 0x00, 0x00, 0x00
 ;;       .byte   0x01, 0x00, 0xff, 0xff
 ;;       .byte   0x00, 0x00, 0x00, 0x00
diff --git a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
index 6847b10d4116..14623df02bf6 100644
--- a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
@@ -48,7 +48,8 @@
 ;;       .byte   0x00, 0x00, 0x00, 0x00
 ;;       ld      a0, 0x38(a0)
 ;;       add     a0, a0, a2
-;;       lbu     a0, 0(a0)
+;;       lb      a0, 0(a0)
+;;       andi    a0, a0, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
index 85ba452cd620..d3ad0a6d29f3 100644
--- a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -52,7 +52,8 @@
 ;;       add     a0, a0, a2
 ;;       lui     t6, 1
 ;;       add     t6, t6, a0
-;;       lbu     a0, 0(t6)
+;;       lb      a0, 0(t6)
+;;       andi    a0, a0, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 1bc6bbeeaa35..cd7f8a22d7af 100644
--- a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -44,17 +44,18 @@
 ;;       sd      ra, 8(sp)
 ;;       sd      s0, 0(sp)
 ;;       mv      s0, sp
-;;       ld      a1, 0x40(a0)
-;;       slli    a2, a2, 0x20
-;;       srli    a2, a2, 0x20
-;;       bgeu    a1, a2, 8
+;;       ld      a4, 0x40(a0)
+;;       slli    a1, a2, 0x20
+;;       srli    a3, a1, 0x20
+;;       bgeu    a4, a3, 8
 ;;       .byte   0x00, 0x00, 0x00, 0x00
-;;       ld      a3, 0x38(a0)
-;;       add     a2, a3, a2
-;;       lui     a1, 0xffff
-;;       slli    a3, a1, 4
-;;       add     a2, a2, a3
-;;       lbu     a0, 0(a2)
+;;       ld      a4, 0x38(a0)
+;;       add     a3, a4, a3
+;;       lui     a2, 0xffff
+;;       slli    a4, a2, 4
+;;       add     a3, a3, a4
+;;       lb      a3, 0(a3)
+;;       andi    a0, a3, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index 9d5d60581f96..9679361ea288 100644
--- a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -44,17 +44,18 @@
 ;;       sd      ra, 8(sp)
 ;;       sd      s0, 0(sp)
 ;;       mv      s0, sp
-;;       ld      a4, 0x40(a0)
-;;       ld      a3, 0x38(a0)
-;;       slli    a2, a2, 0x20
-;;       srli    a5, a2, 0x20
-;;       sltu    a2, a5, a4
-;;       xori    a4, a2, 1
-;;       add     a3, a3, a5
-;;       neg     a1, a4
-;;       not     a4, a1
-;;       and     a5, a3, a4
-;;       lbu     a0, 0(a5)
+;;       ld      a5, 0x40(a0)
+;;       ld      a4, 0x38(a0)
+;;       slli    a3, a2, 0x20
+;;       srli    a0, a3, 0x20
+;;       sltu    a3, a0, a5
+;;       xori    a5, a3, 1
+;;       add     a4, a4, a0
+;;       neg     a2, a5
+;;       not     a5, a2
+;;       and     a0, a4, a5
+;;       lb      a4, 0(a0)
+;;       andi    a0, a4, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index 99e8c709eb33..24d80d151ce6 100644
--- a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -45,18 +45,19 @@
 ;;       sd      ra, 8(sp)
 ;;       sd      s0, 0(sp)
 ;;       mv      s0, sp
-;;       ld      a4, 0x40(a0)
-;;       ld      a5, 0x38(a0)
-;;       slli    a3, a2, 0x20
-;;       srli    a0, a3, 0x20
-;;       sltu    a4, a4, a0
-;;       add     a5, a5, a0
-;;       lui     a0, 1
-;;       add     a5, a5, a0
-;;       neg     a2, a4
-;;       not     a4, a2
-;;       and     a0, a5, a4
-;;       lbu     a0, 0(a0)
+;;       ld      a5, 0x40(a0)
+;;       ld      a0, 0x38(a0)
+;;       slli    a4, a2, 0x20
+;;       srli    a1, a4, 0x20
+;;       sltu    a5, a5, a1
+;;       add     a0, a0, a1
+;;       lui     a1, 1
+;;       add     a0, a0, a1
+;;       neg     a3, a5
+;;       not     a5, a3
+;;       and     a0, a0, a5
+;;       lb      a5, 0(a0)
+;;       andi    a0, a5, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 2d687d207e4f..67f61006fd0c 100644
--- a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -46,19 +46,20 @@
 ;;       sd      ra, 8(sp)
 ;;       sd      s0, 0(sp)
 ;;       mv      s0, sp
-;;       ld      a5, 0x40(a0)
-;;       ld      a0, 0x38(a0)
-;;       slli    a4, a2, 0x20
-;;       srli    a1, a4, 0x20
-;;       sltu    a5, a5, a1
-;;       add     a0, a0, a1
-;;       lui     a4, 0xffff
-;;       slli    a1, a4, 4
-;;       add     a0, a0, a1
-;;       neg     a3, a5
-;;       not     a5, a3
-;;       and     a0, a0, a5
-;;       lbu     a0, 0(a0)
+;;       ld      a3, 0x40(a0)
+;;       ld      a1, 0x38(a0)
+;;       slli    a5, a2, 0x20
+;;       srli    a2, a5, 0x20
+;;       sltu    a0, a3, a2
+;;       add     a1, a1, a2
+;;       lui     a5, 0xffff
+;;       slli    a2, a5, 4
+;;       add     a1, a1, a2
+;;       neg     a4, a0
+;;       not     a0, a4
+;;       and     a0, a1, a0
+;;       lb      a0, 0(a0)
+;;       andi    a0, a0, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
index bf3af20e59bc..620ebe2c5b23 100644
--- a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
@@ -44,7 +44,8 @@
 ;;       .byte   0x00, 0x00, 0x00, 0x00
 ;;       ld      a0, 0x38(a0)
 ;;       add     a0, a0, a2
-;;       lbu     a0, 0(a0)
+;;       lb      a0, 0(a0)
+;;       andi    a0, a0, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
index 1ee992f61dba..81268df43bd8 100644
--- a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -50,11 +50,12 @@
 ;;       sub     a1, a1, a3
 ;;       bgeu    a1, a2, 8
 ;;       .byte   0x00, 0x00, 0x00, 0x00
-;;       ld      a0, 0x38(a0)
-;;       add     a0, a0, a2
+;;       ld      a1, 0x38(a0)
+;;       add     a1, a1, a2
 ;;       lui     t6, 1
-;;       add     t6, t6, a0
-;;       lbu     a0, 0(t6)
+;;       add     t6, t6, a1
+;;       lb      a1, 0(t6)
+;;       andi    a0, a1, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 0fe055ccd229..86f54e33ead3 100644
--- a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -49,23 +49,25 @@
 ;;       sd      ra, 8(sp)
 ;;       sd      s0, 0(sp)
 ;;       mv      s0, sp
-;;       auipc   a1, 0
-;;       ld      a1, 0x48(a1)
-;;       add     a1, a2, a1
-;;       bgeu    a1, a2, 8
+;;       auipc   a3, 0
+;;       ld      a3, 0x50(a3)
+;;       add     a3, a2, a3
+;;       bgeu    a3, a2, 8
 ;;       .byte   0x00, 0x00, 0x00, 0x00
-;;       ld      a3, 0x40(a0)
-;;       bgeu    a3, a1, 8
+;;       ld      a4, 0x40(a0)
+;;       bgeu    a4, a3, 8
 ;;       .byte   0x00, 0x00, 0x00, 0x00
-;;       ld      a3, 0x38(a0)
-;;       add     a3, a3, a2
-;;       lui     a2, 0xffff
-;;       slli    a4, a2, 4
-;;       add     a3, a3, a4
-;;       lbu     a0, 0(a3)
+;;       ld      a4, 0x38(a0)
+;;       add     a4, a4, a2
+;;       lui     a3, 0xffff
+;;       slli    a5, a3, 4
+;;       add     a4, a4, a5
+;;       lb      a4, 0(a4)
+;;       andi    a0, a4, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
 ;;       ret
+;;       .byte   0x00, 0x00, 0x00, 0x00
 ;;       .byte   0x01, 0x00, 0xff, 0xff
 ;;       .byte   0x00, 0x00, 0x00, 0x00
diff --git a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 0f23cece3ac9..7e7b26d883cc 100644
--- a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -42,15 +42,16 @@
 ;;       sd      ra, 8(sp)
 ;;       sd      s0, 0(sp)
 ;;       mv      s0, sp
-;;       ld      a3, 0x40(a0)
-;;       ld      a1, 0x38(a0)
-;;       sltu    a0, a2, a3
-;;       xori    a3, a0, 1
-;;       add     a1, a1, a2
-;;       neg     a0, a3
-;;       not     a2, a0
-;;       and     a3, a1, a2
-;;       lbu     a0, 0(a3)
+;;       ld      a4, 0x40(a0)
+;;       ld      a3, 0x38(a0)
+;;       sltu    a1, a2, a4
+;;       xori    a4, a1, 1
+;;       add     a2, a3, a2
+;;       neg     a0, a4
+;;       not     a3, a0
+;;       and     a4, a2, a3
+;;       lb      a2, 0(a4)
+;;       andi    a0, a2, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index ffda43338d7c..2ead2efbe073 100644
--- a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -47,18 +47,19 @@
 ;;       sd      s0, 0(sp)
 ;;       mv      s0, sp
 ;;       ld      a1, 0x40(a0)
-;;       ld      a5, 0x38(a0)
-;;       lui     a4, 1
-;;       addi    a0, a4, 1
-;;       sub     a0, a1, a0
-;;       sltu    a0, a0, a2
-;;       add     a5, a5, a2
-;;       lui     a1, 1
-;;       add     a5, a5, a1
-;;       neg     a3, a0
-;;       not     a0, a3
-;;       and     a0, a5, a0
-;;       lbu     a0, 0(a0)
+;;       ld      a0, 0x38(a0)
+;;       lui     a5, 1
+;;       addi    a3, a5, 1
+;;       sub     a1, a1, a3
+;;       sltu    a1, a1, a2
+;;       add     a0, a0, a2
+;;       lui     a2, 1
+;;       add     a0, a0, a2
+;;       neg     a4, a1
+;;       not     a1, a4
+;;       and     a0, a0, a1
+;;       lb      a0, 0(a0)
+;;       andi    a0, a0, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index e2b8f3b5508e..5cb3d98f0731 100644
--- a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -51,25 +51,27 @@
 ;;       sd      ra, 8(sp)
 ;;       sd      s0, 0(sp)
 ;;       mv      s0, sp
-;;       auipc   a5, 0
-;;       ld      a5, 0x50(a5)
-;;       add     a5, a2, a5
-;;       bgeu    a5, a2, 8
+;;       auipc   a1, 0
+;;       ld      a1, 0x58(a1)
+;;       add     a1, a2, a1
+;;       bgeu    a1, a2, 8
 ;;       .byte   0x00, 0x00, 0x00, 0x00
-;;       ld      a1, 0x40(a0)
-;;       ld      a3, 0x38(a0)
-;;       sltu    a0, a1, a5
-;;       add     a1, a3, a2
-;;       lui     a5, 0xffff
-;;       slli    a2, a5, 4
+;;       ld      a3, 0x40(a0)
+;;       ld      a4, 0x38(a0)
+;;       sltu    a0, a3, a1
+;;       add     a1, a4, a2
+;;       lui     a2, 0xffff
+;;       slli    a2, a2, 4
 ;;       add     a1, a1, a2
-;;       neg     a4, a0
-;;       not     a0, a4
+;;       neg     a5, a0
+;;       not     a0, a5
 ;;       and     a0, a1, a0
-;;       lbu     a0, 0(a0)
+;;       lb      a0, 0(a0)
+;;       andi    a0, a0, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
 ;;       ret
+;;       .byte   0x00, 0x00, 0x00, 0x00
 ;;       .byte   0x01, 0x00, 0xff, 0xff
 ;;       .byte   0x00, 0x00, 0x00, 0x00
diff --git a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
index cfe3097b43d4..d02f2d0248bc 100644
--- a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
@@ -44,7 +44,8 @@
 ;;       .byte   0x00, 0x00, 0x00, 0x00
 ;;       ld      a0, 0x38(a0)
 ;;       add     a0, a0, a2
-;;       lbu     a0, 0(a0)
+;;       lb      a0, 0(a0)
+;;       andi    a0, a0, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
index 097f02b7b836..d0b65f3ac91b 100644
--- a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -48,7 +48,8 @@
 ;;       add     a0, a0, a2
 ;;       lui     t6, 1
 ;;       add     t6, t6, a0
-;;       lbu     a0, 0(t6)
+;;       lb      a0, 0(t6)
+;;       andi    a0, a0, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 0dd426c1226d..a2cd13c8d931 100644
--- a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -45,12 +45,13 @@
 ;;       ld      a1, 0x40(a0)
 ;;       bgeu    a1, a2, 8
 ;;       .byte   0x00, 0x00, 0x00, 0x00
-;;       ld      a0, 0x38(a0)
-;;       add     a0, a0, a2
-;;       lui     a1, 0xffff
-;;       slli    a1, a1, 4
-;;       add     a0, a0, a1
-;;       lbu     a0, 0(a0)
+;;       ld      a1, 0x38(a0)
+;;       add     a1, a1, a2
+;;       lui     a0, 0xffff
+;;       slli    a2, a0, 4
+;;       add     a1, a1, a2
+;;       lb      a1, 0(a1)
+;;       andi    a0, a1, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index 1f68e34e19d2..82d581e3573a 100644
--- a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -42,15 +42,16 @@
 ;;       sd      ra, 8(sp)
 ;;       sd      s0, 0(sp)
 ;;       mv      s0, sp
-;;       ld      a3, 0x40(a0)
-;;       ld      a1, 0x38(a0)
-;;       sltu    a0, a2, a3
-;;       xori    a3, a0, 1
-;;       add     a1, a1, a2
-;;       neg     a0, a3
-;;       not     a2, a0
-;;       and     a3, a1, a2
-;;       lbu     a0, 0(a3)
+;;       ld      a4, 0x40(a0)
+;;       ld      a3, 0x38(a0)
+;;       sltu    a1, a2, a4
+;;       xori    a4, a1, 1
+;;       add     a2, a3, a2
+;;       neg     a0, a4
+;;       not     a3, a0
+;;       and     a4, a2, a3
+;;       lb      a2, 0(a4)
+;;       andi    a0, a2, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index 918a374b48dd..465b8e4830fb 100644
--- a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -46,13 +46,14 @@
 ;;       ld      a3, 0x40(a0)
 ;;       ld      a4, 0x38(a0)
 ;;       sltu    a3, a3, a2
-;;       add     a2, a4, a2
-;;       lui     a4, 1
-;;       add     a2, a2, a4
-;;       neg     a0, a3
-;;       not     a3, a0
-;;       and     a4, a2, a3
-;;       lbu     a0, 0(a4)
+;;       add     a4, a4, a2
+;;       lui     a5, 1
+;;       add     a4, a4, a5
+;;       neg     a1, a3
+;;       not     a3, a1
+;;       and     a5, a4, a3
+;;       lb      a3, 0(a5)
+;;       andi    a0, a3, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 40f25d638755..5ed8342b01a5 100644
--- a/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -44,17 +44,18 @@
 ;;       sd      ra, 8(sp)
 ;;       sd      s0, 0(sp)
 ;;       mv      s0, sp
-;;       ld      a3, 0x40(a0)
-;;       ld      a4, 0x38(a0)
-;;       sltu    a3, a3, a2
-;;       add     a4, a4, a2
-;;       lui     a2, 0xffff
-;;       slli    a5, a2, 4
-;;       add     a4, a4, a5
-;;       neg     a1, a3
-;;       not     a3, a1
-;;       and     a5, a4, a3
-;;       lbu     a0, 0(a5)
+;;       ld      a4, 0x40(a0)
+;;       ld      a5, 0x38(a0)
+;;       sltu    a4, a4, a2
+;;       add     a5, a5, a2
+;;       lui     a3, 0xffff
+;;       slli    a0, a3, 4
+;;       add     a5, a5, a0
+;;       neg     a2, a4
+;;       not     a4, a2
+;;       and     a0, a5, a4
+;;       lb      a4, 0(a0)
+;;       andi    a0, a4, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
index a15e1c651ad8..9a6a44d2a7ed 100644
--- a/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
@@ -42,7 +42,8 @@
 ;;       slli    a1, a2, 0x20
 ;;       srli    a1, a1, 0x20
 ;;       add     a0, a0, a1
-;;       lbu     a0, 0(a0)
+;;       lb      a0, 0(a0)
+;;       andi    a0, a0, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
index 38e851bc9cd7..e3d0aa515afe 100644
--- a/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -57,11 +57,11 @@
 ;;       add     a0, a0, a1
 ;;       lui     t6, 1
 ;;       add     t6, t6, a0
-;;       lbu     a0, 0(t6)
+;;       lb      a0, 0(t6)
+;;       andi    a0, a0, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
 ;;       ret
-;;       .byte   0x00, 0x00, 0x00, 0x00
 ;;       .byte   0xff, 0xef, 0xff, 0xff
 ;;       .byte   0x00, 0x00, 0x00, 0x00
diff --git a/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index b5ab03f110b4..44b7e25f6177 100644
--- a/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -45,18 +45,19 @@
 ;;       sd      ra, 8(sp)
 ;;       sd      s0, 0(sp)
 ;;       mv      s0, sp
-;;       slli    a1, a2, 0x20
-;;       srli    a3, a1, 0x20
-;;       lui     a1, 0x10
-;;       addi    a4, a1, -1
-;;       bgeu    a4, a3, 8
+;;       slli    a2, a2, 0x20
+;;       srli    a4, a2, 0x20
+;;       lui     a2, 0x10
+;;       addi    a5, a2, -1
+;;       bgeu    a5, a4, 8
 ;;       .byte   0x00, 0x00, 0x00, 0x00
-;;       ld      a4, 0x38(a0)
-;;       add     a3, a4, a3
-;;       lui     a2, 0xffff
-;;       slli    a4, a2, 4
-;;       add     a3, a3, a4
-;;       lbu     a0, 0(a3)
+;;       ld      a5, 0x38(a0)
+;;       add     a4, a5, a4
+;;       lui     a3, 0xffff
+;;       slli    a5, a3, 4
+;;       add     a4, a4, a5
+;;       lb      a4, 0(a4)
+;;       andi    a0, a4, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 4ed12a84d7bb..153bcf174b10 100644
--- a/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -42,7 +42,8 @@
 ;;       slli    a1, a2, 0x20
 ;;       srli    a1, a1, 0x20
 ;;       add     a0, a0, a1
-;;       lbu     a0, 0(a0)
+;;       lb      a0, 0(a0)
+;;       andi    a0, a0, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 7cf01f6ddb8e..6f759a827ebd 100644
--- a/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -49,23 +49,23 @@
 ;;       sd      ra, 8(sp)
 ;;       sd      s0, 0(sp)
 ;;       mv      s0, sp
-;;       slli    a3, a2, 0x20
-;;       srli    a5, a3, 0x20
-;;       auipc   a4, 0
-;;       ld      a4, 0x40(a4)
-;;       sltu    a4, a4, a5
+;;       slli    a4, a2, 0x20
+;;       srli    a1, a4, 0x20
+;;       auipc   a5, 0
+;;       ld      a5, 0x40(a5)
+;;       sltu    a5, a5, a1
 ;;       ld      a0, 0x38(a0)
-;;       add     a5, a0, a5
-;;       lui     a0, 1
-;;       add     a5, a5, a0
-;;       neg     a2, a4
-;;       not     a4, a2
-;;       and     a0, a5, a4
-;;       lbu     a0, 0(a0)
+;;       add     a0, a0, a1
+;;       lui     a1, 1
+;;       add     a0, a0, a1
+;;       neg     a3, a5
+;;       not     a5, a3
+;;       and     a0, a0, a5
+;;       lb      a5, 0(a0)
+;;       andi    a0, a5, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
 ;;       ret
-;;       .byte   0x00, 0x00, 0x00, 0x00
 ;;       .byte   0xff, 0xef, 0xff, 0xff
 ;;       .byte   0x00, 0x00, 0x00, 0x00
diff --git a/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 906d2a950e04..3fff2067fd73 100644
--- a/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -50,21 +50,22 @@
 ;;       sd      s0, 0(sp)
 ;;       mv      s0, sp
 ;;       mv      a3, a0
-;;       slli    a5, a2, 0x20
-;;       srli    a1, a5, 0x20
-;;       lui     a5, 0x10
-;;       addi    a0, a5, -1
+;;       slli    a0, a2, 0x20
+;;       srli    a1, a0, 0x20
+;;       lui     a0, 0x10
+;;       addi    a0, a0, -1
 ;;       sltu    a0, a0, a1
 ;;       mv      a2, a3
 ;;       ld      a2, 0x38(a2)
 ;;       add     a1, a2, a1
-;;       lui     a5, 0xffff
-;;       slli    a2, a5, 4
+;;       lui     a2, 0xffff
+;;       slli    a2, a2, 4
 ;;       add     a1, a1, a2
-;;       neg     a4, a0
-;;       not     a0, a4
+;;       neg     a5, a0
+;;       not     a0, a5
 ;;       and     a0, a1, a0
-;;       lbu     a0, 0(a0)
+;;       lb      a0, 0(a0)
+;;       andi    a0, a0, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
index b96f03eb82f9..62a7fd65947a 100644
--- a/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
@@ -42,7 +42,8 @@
 ;;       slli    a1, a2, 0x20
 ;;       srli    a1, a1, 0x20
 ;;       add     a0, a0, a1
-;;       lbu     a0, 0(a0)
+;;       lb      a0, 0(a0)
+;;       andi    a0, a0, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
index 5e5f42b6a4b5..4171ada8ba26 100644
--- a/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -46,7 +46,8 @@
 ;;       add     a0, a0, a1
 ;;       lui     t6, 1
 ;;       add     t6, t6, a0
-;;       lbu     a0, 0(t6)
+;;       lb      a0, 0(t6)
+;;       andi    a0, a0, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 5cc7c66e1acc..c44f5e2a9af9 100644
--- a/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -41,14 +41,15 @@
 ;;       sd      ra, 8(sp)
 ;;       sd      s0, 0(sp)
 ;;       mv      s0, sp
-;;       ld      a0, 0x38(a0)
-;;       slli    a1, a2, 0x20
-;;       srli    a1, a1, 0x20
-;;       add     a0, a0, a1
-;;       lui     a1, 0xffff
-;;       slli    a1, a1, 4
-;;       add     a0, a0, a1
-;;       lbu     a0, 0(a0)
+;;       ld      a1, 0x38(a0)
+;;       slli    a0, a2, 0x20
+;;       srli    a2, a0, 0x20
+;;       add     a1, a1, a2
+;;       lui     a0, 0xffff
+;;       slli    a2, a0, 4
+;;       add     a1, a1, a2
+;;       lb      a1, 0(a1)
+;;       andi    a0, a1, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index 0671cdc17a69..b8284d738223 100644
--- a/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -42,7 +42,8 @@
 ;;       slli    a1, a2, 0x20
 ;;       srli    a1, a1, 0x20
 ;;       add     a0, a0, a1
-;;       lbu     a0, 0(a0)
+;;       lb      a0, 0(a0)
+;;       andi    a0, a0, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index ecd3b838db4f..afbb2105c8c5 100644
--- a/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -46,7 +46,8 @@
 ;;       add     a0, a0, a1
 ;;       lui     t6, 1
 ;;       add     t6, t6, a0
-;;       lbu     a0, 0(t6)
+;;       lb      a0, 0(t6)
+;;       andi    a0, a0, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 80b5af74bcc5..9cce70f908e9 100644
--- a/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -41,14 +41,15 @@
 ;;       sd      ra, 8(sp)
 ;;       sd      s0, 0(sp)
 ;;       mv      s0, sp
-;;       ld      a0, 0x38(a0)
-;;       slli    a1, a2, 0x20
-;;       srli    a1, a1, 0x20
-;;       add     a0, a0, a1
-;;       lui     a1, 0xffff
-;;       slli    a1, a1, 4
-;;       add     a0, a0, a1
-;;       lbu     a0, 0(a0)
+;;       ld      a1, 0x38(a0)
+;;       slli    a0, a2, 0x20
+;;       srli    a2, a0, 0x20
+;;       add     a1, a1, a2
+;;       lui     a0, 0xffff
+;;       slli    a2, a0, 4
+;;       add     a1, a1, a2
+;;       lb      a1, 0(a1)
+;;       andi    a0, a1, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
index b31486bb1ef2..e3e870ee9684 100644
--- a/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
@@ -49,11 +49,11 @@
 ;;       .byte   0x00, 0x00, 0x00, 0x00
 ;;       ld      a0, 0x38(a0)
 ;;       add     a0, a0, a2
-;;       lbu     a0, 0(a0)
+;;       lb      a0, 0(a0)
+;;       andi    a0, a0, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
 ;;       ret
-;;       .byte   0x00, 0x00, 0x00, 0x00
 ;;       .byte   0xff, 0xff, 0xff, 0xff
 ;;       .byte   0x00, 0x00, 0x00, 0x00
diff --git a/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
index c47cc77f06f6..fcf9ba25561e 100644
--- a/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -53,11 +53,11 @@
 ;;       add     a0, a0, a2
 ;;       lui     t6, 1
 ;;       add     t6, t6, a0
-;;       lbu     a0, 0(t6)
+;;       lb      a0, 0(t6)
+;;       andi    a0, a0, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
 ;;       ret
-;;       .byte   0x00, 0x00, 0x00, 0x00
 ;;       .byte   0xff, 0xef, 0xff, 0xff
 ;;       .byte   0x00, 0x00, 0x00, 0x00
diff --git a/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 984f57973490..508259beb4c4 100644
--- a/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -44,15 +44,16 @@
 ;;       sd      s0, 0(sp)
 ;;       mv      s0, sp
 ;;       lui     a1, 0x10
-;;       addi    a1, a1, -1
-;;       bgeu    a1, a2, 8
+;;       addi    a3, a1, -1
+;;       bgeu    a3, a2, 8
 ;;       .byte   0x00, 0x00, 0x00, 0x00
-;;       ld      a1, 0x38(a0)
-;;       add     a1, a1, a2
-;;       lui     a0, 0xffff
-;;       slli    a2, a0, 4
-;;       add     a1, a1, a2
-;;       lbu     a0, 0(a1)
+;;       ld      a3, 0x38(a0)
+;;       add     a2, a3, a2
+;;       lui     a1, 0xffff
+;;       slli    a3, a1, 4
+;;       add     a2, a2, a3
+;;       lb      a2, 0(a2)
+;;       andi    a0, a2, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 68c53e17b233..7db3c5c3e25c 100644
--- a/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -45,16 +45,16 @@
 ;;       sd      ra, 8(sp)
 ;;       sd      s0, 0(sp)
 ;;       mv      s0, sp
-;;       mv      a3, a0
-;;       auipc   a0, 0
-;;       ld      a0, 0x34(a0)
-;;       sltu    a0, a0, a2
-;;       ld      a1, 0x38(a3)
-;;       add     a1, a1, a2
-;;       neg     a0, a0
-;;       not     a0, a0
-;;       and     a2, a1, a0
-;;       lbu     a0, 0(a2)
+;;       auipc   a1, 0
+;;       ld      a1, 0x38(a1)
+;;       sltu    a1, a1, a2
+;;       ld      a3, 0x38(a0)
+;;       add     a2, a3, a2
+;;       neg     a0, a1
+;;       not     a1, a0
+;;       and     a3, a2, a1
+;;       lb      a1, 0(a3)
+;;       andi    a0, a1, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index cd3217bb9e14..fe3ce5cfa102 100644
--- a/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -51,17 +51,17 @@
 ;;       ld      a3, 0x40(a3)
 ;;       sltu    a3, a3, a2
 ;;       ld      a4, 0x38(a0)
-;;       add     a2, a4, a2
-;;       lui     a4, 1
-;;       add     a2, a2, a4
-;;       neg     a0, a3
-;;       not     a3, a0
-;;       and     a4, a2, a3
-;;       lbu     a0, 0(a4)
+;;       add     a4, a4, a2
+;;       lui     a5, 1
+;;       add     a4, a4, a5
+;;       neg     a1, a3
+;;       not     a3, a1
+;;       and     a5, a4, a3
+;;       lb      a3, 0(a5)
+;;       andi    a0, a3, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
 ;;       ret
-;;       .byte   0x00, 0x00, 0x00, 0x00
 ;;       .byte   0xff, 0xef, 0xff, 0xff
 ;;       .byte   0x00, 0x00, 0x00, 0x00
diff --git a/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 9cce641a6ec5..e1b021d558c2 100644
--- a/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -45,18 +45,19 @@
 ;;       sd      ra, 8(sp)
 ;;       sd      s0, 0(sp)
 ;;       mv      s0, sp
-;;       lui     a3, 0x10
-;;       addi    a5, a3, -1
-;;       sltu    a4, a5, a2
-;;       ld      a5, 0x38(a0)
-;;       add     a5, a5, a2
-;;       lui     a3, 0xffff
-;;       slli    a0, a3, 4
-;;       add     a5, a5, a0
-;;       neg     a2, a4
-;;       not     a4, a2
-;;       and     a0, a5, a4
-;;       lbu     a0, 0(a0)
+;;       lui     a4, 0x10
+;;       addi    a1, a4, -1
+;;       sltu    a5, a1, a2
+;;       ld      a0, 0x38(a0)
+;;       add     a0, a0, a2
+;;       lui     a4, 0xffff
+;;       slli    a1, a4, 4
+;;       add     a0, a0, a1
+;;       neg     a3, a5
+;;       not     a5, a3
+;;       and     a0, a0, a5
+;;       lb      a5, 0(a0)
+;;       andi    a0, a5, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
index a103da674c5c..d04fd2d647e6 100644
--- a/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
@@ -49,11 +49,11 @@
 ;;       .byte   0x00, 0x00, 0x00, 0x00
 ;;       ld      a0, 0x38(a0)
 ;;       add     a0, a0, a2
-;;       lbu     a0, 0(a0)
+;;       lb      a0, 0(a0)
+;;       andi    a0, a0, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
 ;;       ret
-;;       .byte   0x00, 0x00, 0x00, 0x00
 ;;       .byte   0xff, 0xff, 0xff, 0xff
 ;;       .byte   0x00, 0x00, 0x00, 0x00
diff --git a/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
index 5f63f7cee4c4..2f1c74fda532 100644
--- a/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -53,11 +53,11 @@
 ;;       add     a0, a0, a2
 ;;       lui     t6, 1
 ;;       add     t6, t6, a0
-;;       lbu     a0, 0(t6)
+;;       lb      a0, 0(t6)
+;;       andi    a0, a0, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
 ;;       ret
-;;       .byte   0x00, 0x00, 0x00, 0x00
 ;;       .byte   0xff, 0xef, 0xff, 0xff
 ;;       .byte   0x00, 0x00, 0x00, 0x00
diff --git a/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 06453f0efd46..1f6b255e537c 100644
--- a/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -44,15 +44,16 @@
 ;;       sd      s0, 0(sp)
 ;;       mv      s0, sp
 ;;       lui     a1, 0x10
-;;       addi    a1, a1, -1
-;;       bgeu    a1, a2, 8
+;;       addi    a3, a1, -1
+;;       bgeu    a3, a2, 8
 ;;       .byte   0x00, 0x00, 0x00, 0x00
-;;       ld      a1, 0x38(a0)
-;;       add     a1, a1, a2
-;;       lui     a0, 0xffff
-;;       slli    a2, a0, 4
-;;       add     a1, a1, a2
-;;       lbu     a0, 0(a1)
+;;       ld      a3, 0x38(a0)
+;;       add     a2, a3, a2
+;;       lui     a1, 0xffff
+;;       slli    a3, a1, 4
+;;       add     a2, a2, a3
+;;       lb      a2, 0(a2)
+;;       andi    a0, a2, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index 752beb8d24c2..8215404cf5d3 100644
--- a/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -45,16 +45,16 @@
 ;;       sd      ra, 8(sp)
 ;;       sd      s0, 0(sp)
 ;;       mv      s0, sp
-;;       mv      a3, a0
-;;       auipc   a0, 0
-;;       ld      a0, 0x34(a0)
-;;       sltu    a0, a0, a2
-;;       ld      a1, 0x38(a3)
-;;       add     a1, a1, a2
-;;       neg     a0, a0
-;;       not     a0, a0
-;;       and     a2, a1, a0
-;;       lbu     a0, 0(a2)
+;;       auipc   a1, 0
+;;       ld      a1, 0x38(a1)
+;;       sltu    a1, a1, a2
+;;       ld      a3, 0x38(a0)
+;;       add     a2, a3, a2
+;;       neg     a0, a1
+;;       not     a1, a0
+;;       and     a3, a2, a1
+;;       lb      a1, 0(a3)
+;;       andi    a0, a1, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index 478c81d08358..cf2355392342 100644
--- a/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -51,17 +51,17 @@
 ;;       ld      a3, 0x40(a3)
 ;;       sltu    a3, a3, a2
 ;;       ld      a4, 0x38(a0)
-;;       add     a2, a4, a2
-;;       lui     a4, 1
-;;       add     a2, a2, a4
-;;       neg     a0, a3
-;;       not     a3, a0
-;;       and     a4, a2, a3
-;;       lbu     a0, 0(a4)
+;;       add     a4, a4, a2
+;;       lui     a5, 1
+;;       add     a4, a4, a5
+;;       neg     a1, a3
+;;       not     a3, a1
+;;       and     a5, a4, a3
+;;       lb      a3, 0(a5)
+;;       andi    a0, a3, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
 ;;       ret
-;;       .byte   0x00, 0x00, 0x00, 0x00
 ;;       .byte   0xff, 0xef, 0xff, 0xff
 ;;       .byte   0x00, 0x00, 0x00, 0x00
diff --git a/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 504198f4c47e..8bb3c74f0399 100644
--- a/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/riscv64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -45,18 +45,19 @@
 ;;       sd      ra, 8(sp)
 ;;       sd      s0, 0(sp)
 ;;       mv      s0, sp
-;;       lui     a3, 0x10
-;;       addi    a5, a3, -1
-;;       sltu    a4, a5, a2
-;;       ld      a5, 0x38(a0)
-;;       add     a5, a5, a2
-;;       lui     a3, 0xffff
-;;       slli    a0, a3, 4
-;;       add     a5, a5, a0
-;;       neg     a2, a4
-;;       not     a4, a2
-;;       and     a0, a5, a4
-;;       lbu     a0, 0(a0)
+;;       lui     a4, 0x10
+;;       addi    a1, a4, -1
+;;       sltu    a5, a1, a2
+;;       ld      a0, 0x38(a0)
+;;       add     a0, a0, a2
+;;       lui     a4, 0xffff
+;;       slli    a1, a4, 4
+;;       add     a0, a0, a1
+;;       neg     a3, a5
+;;       not     a5, a3
+;;       and     a0, a0, a5
+;;       lb      a5, 0(a0)
+;;       andi    a0, a5, 0xff
 ;;       ld      ra, 8(sp)
 ;;       ld      s0, 0(sp)
 ;;       addi    sp, sp, 0x10
diff --git a/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
index ae3d14588385..2da5a3216288 100644
--- a/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
@@ -45,11 +45,12 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       lg      %r7, 0x40(%r2)
-;;       llgfr   %r6, %r4
-;;       clgr    %r6, %r7
+;;       lg      %r3, 0x40(%r2)
+;;       llgfr   %r7, %r4
+;;       clgr    %r7, %r3
 ;;       jghe    0x88
 ;;       lg      %r2, 0x38(%r2)
-;;       llc     %r2, 0(%r6, %r2)
+;;       llc     %r2, 0(%r7, %r2)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
index c28dce417ead..5eef0821b5b2 100644
--- a/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -48,12 +48,13 @@
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
 ;;       lg      %r3, 0x40(%r2)
-;;       llgfr   %r6, %r4
+;;       llgfr   %r7, %r4
 ;;       aghi    %r3, -0x1001
-;;       clgr    %r6, %r3
+;;       clgr    %r7, %r3
 ;;       jgh     0x94
-;;       ag      %r6, 0x38(%r2)
+;;       ag      %r7, 0x38(%r2)
 ;;       lghi    %r2, 0x1000
-;;       llc     %r2, 0(%r2, %r6)
+;;       llc     %r2, 0(%r2, %r7)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 018b4d914ec7..041d9bdb619a 100644
--- a/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -49,15 +49,16 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       llgfr   %r5, %r4
+;;       llgfr   %r6, %r4
 ;;       llilf   %r3, 0xffff0001
 ;;       algfr   %r3, %r4
 ;;       jgnle   0x9c
 ;;       lg      %r4, 0x40(%r2)
 ;;       clgr    %r3, %r4
 ;;       jgh     0xac
-;;       ag      %r5, 0x38(%r2)
+;;       ag      %r6, 0x38(%r2)
 ;;       llilh   %r2, 0xffff
-;;       llc     %r2, 0(%r2, %r5)
+;;       llc     %r2, 0(%r2, %r6)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 947ccb123ea4..271d2569a4cf 100644
--- a/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -50,10 +50,11 @@
 ;;       lg      %r3, 0x40(%r2)
 ;;       llgfr   %r5, %r4
 ;;       lghi    %r4, 0
-;;       lgr     %r7, %r5
-;;       ag      %r7, 0x38(%r2)
+;;       lgr     %r6, %r5
+;;       ag      %r6, 0x38(%r2)
 ;;       clgr    %r5, %r3
-;;       locgrhe %r7, %r4
-;;       llc     %r2, 0(%r7)
+;;       locgrhe %r6, %r4
+;;       llc     %r2, 0(%r6)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 9c3a9f6d2a68..132f49378d15 100644
--- a/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -61,5 +61,6 @@
 ;;       clgr    %r3, %r5
 ;;       locgrh  %r2, %r4
 ;;       llc     %r2, 0(%r2)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 4097a5e53e65..a2a10d8d5f68 100644
--- a/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -53,19 +53,20 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       lgr     %r3, %r2
-;;       llgfr   %r7, %r4
+;;       lgr     %r5, %r2
+;;       llgfr   %r3, %r4
 ;;       llilf   %r2, 0xffff0001
 ;;       algfr   %r2, %r4
 ;;       jgnle   0xac
-;;       lgr     %r5, %r3
-;;       lg      %r4, 0x40(%r5)
-;;       lghi    %r3, 0
-;;       ag      %r7, 0x38(%r5)
-;;       llilh   %r5, 0xffff
-;;       agrk    %r5, %r7, %r5
-;;       clgr    %r2, %r4
-;;       locgrh  %r5, %r3
-;;       llc     %r2, 0(%r5)
+;;       lgr     %r6, %r5
+;;       lg      %r5, 0x40(%r6)
+;;       lghi    %r4, 0
+;;       ag      %r3, 0x38(%r6)
+;;       llilh   %r6, 0xffff
+;;       agr     %r3, %r6
+;;       clgr    %r2, %r5
+;;       locgrh  %r3, %r4
+;;       llc     %r2, 0(%r3)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
index 82f549ee8a69..98db1b9db855 100644
--- a/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
@@ -45,11 +45,12 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       lg      %r7, 0x40(%r2)
-;;       llgfr   %r6, %r4
-;;       clgr    %r6, %r7
+;;       lg      %r3, 0x40(%r2)
+;;       llgfr   %r7, %r4
+;;       clgr    %r7, %r3
 ;;       jghe    0x88
 ;;       lg      %r2, 0x38(%r2)
-;;       llc     %r2, 0(%r6, %r2)
+;;       llc     %r2, 0(%r7, %r2)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
index 2ba47791c56e..700f11263e0a 100644
--- a/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -46,12 +46,13 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       lg      %r7, 0x40(%r2)
-;;       llgfr   %r6, %r4
-;;       clgr    %r6, %r7
+;;       lg      %r3, 0x40(%r2)
+;;       llgfr   %r7, %r4
+;;       clgr    %r7, %r3
 ;;       jgh     0x8c
-;;       ag      %r6, 0x38(%r2)
+;;       ag      %r7, 0x38(%r2)
 ;;       lghi    %r2, 0x1000
-;;       llc     %r2, 0(%r2, %r6)
+;;       llc     %r2, 0(%r2, %r7)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 0176c1bcca5f..5259cdad171a 100644
--- a/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -46,12 +46,13 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       lg      %r7, 0x40(%r2)
-;;       llgfr   %r6, %r4
-;;       clgr    %r6, %r7
+;;       lg      %r3, 0x40(%r2)
+;;       llgfr   %r7, %r4
+;;       clgr    %r7, %r3
 ;;       jgh     0x8c
-;;       ag      %r6, 0x38(%r2)
+;;       ag      %r7, 0x38(%r2)
 ;;       llilh   %r2, 0xffff
-;;       llc     %r2, 0(%r2, %r6)
+;;       llc     %r2, 0(%r2, %r7)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index 0cfa47715727..3c2e59fe2d86 100644
--- a/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -50,10 +50,11 @@
 ;;       lg      %r3, 0x40(%r2)
 ;;       llgfr   %r5, %r4
 ;;       lghi    %r4, 0
-;;       lgr     %r7, %r5
-;;       ag      %r7, 0x38(%r2)
+;;       lgr     %r6, %r5
+;;       ag      %r6, 0x38(%r2)
 ;;       clgr    %r5, %r3
-;;       locgrhe %r7, %r4
-;;       llc     %r2, 0(%r7)
+;;       locgrhe %r6, %r4
+;;       llc     %r2, 0(%r6)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index 57bfa481b1f0..f2e1e59d7ae4 100644
--- a/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -57,5 +57,6 @@
 ;;       clgr    %r5, %r6
 ;;       locgrh  %r2, %r3
 ;;       llc     %r2, 0(%r2)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index ce77cf7a0c98..1767c4d374a1 100644
--- a/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -59,5 +59,6 @@
 ;;       clgr    %r4, %r5
 ;;       locgrh  %r2, %r3
 ;;       llc     %r2, 0(%r2)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
index e61d1b4ff808..5b922cf25cd7 100644
--- a/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
@@ -44,10 +44,11 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       lg      %r5, 0x40(%r2)
-;;       clgr    %r4, %r5
+;;       lg      %r6, 0x40(%r2)
+;;       clgr    %r4, %r6
 ;;       jghe    0x80
-;;       lg      %r7, 0x38(%r2)
-;;       llc     %r2, 0(%r4, %r7)
+;;       lg      %r2, 0x38(%r2)
+;;       llc     %r2, 0(%r4, %r2)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
index b6a6866f2a76..9ab3098fe588 100644
--- a/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -46,12 +46,13 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       lg      %r7, 0x40(%r2)
-;;       aghi    %r7, -0x1001
-;;       clgr    %r4, %r7
+;;       lg      %r3, 0x40(%r2)
+;;       aghi    %r3, -0x1001
+;;       clgr    %r4, %r3
 ;;       jgh     0x8c
 ;;       ag      %r4, 0x38(%r2)
 ;;       lghi    %r2, 0x1000
 ;;       llc     %r2, 0(%r2, %r4)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 114ba3315523..48aa6b98586b 100644
--- a/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -48,14 +48,15 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       lgr     %r7, %r4
-;;       algfi   %r7, 0xffff0001
+;;       lgr     %r3, %r4
+;;       algfi   %r3, 0xffff0001
 ;;       jgnle   0x94
-;;       lg      %r3, 0x40(%r2)
-;;       clgr    %r7, %r3
+;;       lg      %r5, 0x40(%r2)
+;;       clgr    %r3, %r5
 ;;       jgh     0xa4
 ;;       ag      %r4, 0x38(%r2)
 ;;       llilh   %r2, 0xffff
 ;;       llc     %r2, 0(%r2, %r4)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 229aa053de80..0ed1e22b6341 100644
--- a/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -46,12 +46,13 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       lg      %r3, 0x40(%r2)
-;;       lghi    %r7, 0
-;;       lgr     %r6, %r4
-;;       ag      %r6, 0x38(%r2)
-;;       clgr    %r4, %r3
-;;       locgrhe %r6, %r7
-;;       llc     %r2, 0(%r6)
+;;       lg      %r5, 0x40(%r2)
+;;       lghi    %r3, 0
+;;       lgr     %r7, %r4
+;;       ag      %r7, 0x38(%r2)
+;;       clgr    %r4, %r5
+;;       locgrhe %r7, %r3
+;;       llc     %r2, 0(%r7)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 0097c9fa759c..7192849723e4 100644
--- a/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -57,5 +57,6 @@
 ;;       clgr    %r4, %r5
 ;;       locgrh  %r2, %r3
 ;;       llc     %r2, 0(%r2)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 7d9c0ac17a07..f264d0b3df1c 100644
--- a/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -61,5 +61,6 @@
 ;;       clgr    %r5, %r6
 ;;       locgrh  %r2, %r3
 ;;       llc     %r2, 0(%r2)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
index 3a25bd59ee7f..90f0adef7c4b 100644
--- a/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
@@ -44,10 +44,11 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       lg      %r5, 0x40(%r2)
-;;       clgr    %r4, %r5
+;;       lg      %r6, 0x40(%r2)
+;;       clgr    %r4, %r6
 ;;       jghe    0x80
-;;       lg      %r7, 0x38(%r2)
-;;       llc     %r2, 0(%r4, %r7)
+;;       lg      %r2, 0x38(%r2)
+;;       llc     %r2, 0(%r4, %r2)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
index f40e2f313fb3..5808663a3baf 100644
--- a/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -45,11 +45,12 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       lg      %r6, 0x40(%r2)
-;;       clgr    %r4, %r6
+;;       lg      %r7, 0x40(%r2)
+;;       clgr    %r4, %r7
 ;;       jgh     0x84
 ;;       ag      %r4, 0x38(%r2)
 ;;       lghi    %r2, 0x1000
 ;;       llc     %r2, 0(%r2, %r4)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 4b1ac6e38d08..5c0ad5f7a98f 100644
--- a/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -45,11 +45,12 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       lg      %r6, 0x40(%r2)
-;;       clgr    %r4, %r6
+;;       lg      %r7, 0x40(%r2)
+;;       clgr    %r4, %r7
 ;;       jgh     0x84
 ;;       ag      %r4, 0x38(%r2)
 ;;       llilh   %r2, 0xffff
 ;;       llc     %r2, 0(%r2, %r4)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index 3dd1887fb4d2..99e34bac40e1 100644
--- a/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -46,12 +46,13 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       lg      %r3, 0x40(%r2)
-;;       lghi    %r7, 0
-;;       lgr     %r6, %r4
-;;       ag      %r6, 0x38(%r2)
-;;       clgr    %r4, %r3
-;;       locgrhe %r6, %r7
-;;       llc     %r2, 0(%r6)
+;;       lg      %r5, 0x40(%r2)
+;;       lghi    %r3, 0
+;;       lgr     %r7, %r4
+;;       ag      %r7, 0x38(%r2)
+;;       clgr    %r4, %r5
+;;       locgrhe %r7, %r3
+;;       llc     %r2, 0(%r7)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index 811e88375fab..08224203ef43 100644
--- a/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -51,9 +51,10 @@
 ;;       lghi    %r5, 0
 ;;       lgr     %r6, %r4
 ;;       ag      %r6, 0x38(%r2)
-;;       aghik   %r7, %r6, 0x1000
+;;       aghik   %r2, %r6, 0x1000
 ;;       clgr    %r4, %r3
-;;       locgrh  %r7, %r5
-;;       llc     %r2, 0(%r7)
+;;       locgrh  %r2, %r5
+;;       llc     %r2, 0(%r2)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index b234605b2837..b83ab36b013c 100644
--- a/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -57,5 +57,6 @@
 ;;       clgr    %r4, %r3
 ;;       locgrh  %r2, %r5
 ;;       llc     %r2, 0(%r2)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
index 3c545cecab8c..d86e0bc7181a 100644
--- a/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
@@ -42,8 +42,9 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       lg      %r5, 0x38(%r2)
-;;       llgfr   %r6, %r4
-;;       llc     %r2, 0(%r6, %r5)
+;;       lg      %r6, 0x38(%r2)
+;;       llgfr   %r7, %r4
+;;       llc     %r6, 0(%r7, %r6)
+;;       llcr    %r2, %r6
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
index 630a93fa9231..f242d3e724af 100644
--- a/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -45,11 +45,12 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       llgfr   %r5, %r4
-;;       clgfi   %r5, 0xffffefff
+;;       llgfr   %r6, %r4
+;;       clgfi   %r6, 0xffffefff
 ;;       jgh     0x84
-;;       ag      %r5, 0x38(%r2)
+;;       ag      %r6, 0x38(%r2)
 ;;       lghi    %r2, 0x1000
-;;       llc     %r2, 0(%r2, %r5)
+;;       llc     %r2, 0(%r2, %r6)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index a739b86a9655..6412f488aeab 100644
--- a/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -45,11 +45,12 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       llgfr   %r5, %r4
-;;       clgfi   %r5, 0xffff
+;;       llgfr   %r6, %r4
+;;       clgfi   %r6, 0xffff
 ;;       jgh     0x84
-;;       ag      %r5, 0x38(%r2)
+;;       ag      %r6, 0x38(%r2)
 ;;       llilh   %r2, 0xffff
-;;       llc     %r2, 0(%r2, %r5)
+;;       llc     %r2, 0(%r2, %r6)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
index a79a0bc9dce4..679d4e2e029a 100644
--- a/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -42,8 +42,9 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       lg      %r5, 0x38(%r2)
-;;       llgfr   %r6, %r4
-;;       llc     %r2, 0(%r6, %r5)
+;;       lg      %r6, 0x38(%r2)
+;;       llgfr   %r7, %r4
+;;       llc     %r6, 0(%r7, %r6)
+;;       llcr    %r2, %r6
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 1664e500da16..d1d66371e8c9 100644
--- a/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -51,9 +51,10 @@
 ;;       lghi    %r4, 0
 ;;       lgr     %r5, %r3
 ;;       ag      %r5, 0x38(%r2)
-;;       aghik   %r7, %r5, 0x1000
+;;       aghik   %r2, %r5, 0x1000
 ;;       clgfi   %r3, 0xffffefff
-;;       locgrh  %r7, %r4
-;;       llc     %r2, 0(%r7)
+;;       locgrh  %r2, %r4
+;;       llc     %r2, 0(%r2)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 9dab79a09370..d03d7bff1a4b 100644
--- a/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -57,5 +57,6 @@
 ;;       clgfi   %r3, 0xffff
 ;;       locgrh  %r2, %r4
 ;;       llc     %r2, 0(%r2)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
index 4b09dfa79502..554c70566425 100644
--- a/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
@@ -42,8 +42,9 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       lg      %r5, 0x38(%r2)
-;;       llgfr   %r6, %r4
-;;       llc     %r2, 0(%r6, %r5)
+;;       lg      %r6, 0x38(%r2)
+;;       llgfr   %r7, %r4
+;;       llc     %r6, 0(%r7, %r6)
+;;       llcr    %r2, %r6
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
index 032bc28e3f59..57b599ef87b1 100644
--- a/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -43,9 +43,10 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       llgfr   %r5, %r4
-;;       ag      %r5, 0x38(%r2)
-;;       lghi    %r6, 0x1000
-;;       llc     %r2, 0(%r6, %r5)
+;;       llgfr   %r6, %r4
+;;       ag      %r6, 0x38(%r2)
+;;       lghi    %r7, 0x1000
+;;       llc     %r7, 0(%r7, %r6)
+;;       llcr    %r2, %r7
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 4c00180be48d..15c50535f8fd 100644
--- a/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -43,9 +43,10 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       llgfr   %r5, %r4
-;;       ag      %r5, 0x38(%r2)
-;;       llilh   %r6, 0xffff
-;;       llc     %r2, 0(%r6, %r5)
+;;       llgfr   %r6, %r4
+;;       ag      %r6, 0x38(%r2)
+;;       llilh   %r7, 0xffff
+;;       llc     %r7, 0(%r7, %r6)
+;;       llcr    %r2, %r7
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index 8082a99b4ef9..7a4102870f89 100644
--- a/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -42,8 +42,9 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       lg      %r5, 0x38(%r2)
-;;       llgfr   %r6, %r4
-;;       llc     %r2, 0(%r6, %r5)
+;;       lg      %r6, 0x38(%r2)
+;;       llgfr   %r7, %r4
+;;       llc     %r6, 0(%r7, %r6)
+;;       llcr    %r2, %r6
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index df93df83f3a2..d7ec62d5f573 100644
--- a/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -43,9 +43,10 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       llgfr   %r5, %r4
-;;       ag      %r5, 0x38(%r2)
-;;       lghi    %r6, 0x1000
-;;       llc     %r2, 0(%r6, %r5)
+;;       llgfr   %r6, %r4
+;;       ag      %r6, 0x38(%r2)
+;;       lghi    %r7, 0x1000
+;;       llc     %r7, 0(%r7, %r6)
+;;       llcr    %r2, %r7
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index b181948e7dff..2cbf9a5ae6d6 100644
--- a/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -43,9 +43,10 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       llgfr   %r5, %r4
-;;       ag      %r5, 0x38(%r2)
-;;       llilh   %r6, 0xffff
-;;       llc     %r2, 0(%r6, %r5)
+;;       llgfr   %r6, %r4
+;;       ag      %r6, 0x38(%r2)
+;;       llilh   %r7, 0xffff
+;;       llc     %r7, 0(%r7, %r6)
+;;       llcr    %r2, %r7
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
index cd7c4730ad4f..8879737b0f2f 100644
--- a/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
@@ -45,7 +45,8 @@
 ;;       stg     %r1, 0(%r15)
 ;;       clgfi   %r4, 0xffffffff
 ;;       jgh     0x78
-;;       lg      %r6, 0x38(%r2)
-;;       llc     %r2, 0(%r4, %r6)
+;;       lg      %r7, 0x38(%r2)
+;;       llc     %r7, 0(%r4, %r7)
+;;       llcr    %r2, %r7
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
index 60caa78cf929..40f7425d2c4b 100644
--- a/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -47,7 +47,8 @@
 ;;       clgfi   %r4, 0xffffefff
 ;;       jgh     0x7c
 ;;       ag      %r4, 0x38(%r2)
-;;       lghi    %r7, 0x1000
-;;       llc     %r2, 0(%r7, %r4)
+;;       lghi    %r2, 0x1000
+;;       llc     %r2, 0(%r2, %r4)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index c90862aec147..2f426fa500e1 100644
--- a/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -47,7 +47,8 @@
 ;;       clgfi   %r4, 0xffff
 ;;       jgh     0x7c
 ;;       ag      %r4, 0x38(%r2)
-;;       llilh   %r7, 0xffff
-;;       llc     %r2, 0(%r7, %r4)
+;;       llilh   %r2, 0xffff
+;;       llc     %r2, 0(%r2, %r4)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 0864c43320f4..6ea91ed2d6d3 100644
--- a/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -45,11 +45,12 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       lghi    %r6, 0
-;;       lgr     %r5, %r4
-;;       ag      %r5, 0x38(%r2)
+;;       lghi    %r7, 0
+;;       lgr     %r6, %r4
+;;       ag      %r6, 0x38(%r2)
 ;;       clgfi   %r4, 0xffffffff
-;;       locgrh  %r5, %r6
-;;       llc     %r2, 0(%r5)
+;;       locgrh  %r6, %r7
+;;       llc     %r2, 0(%r6)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 1f8f2cfcae42..6c1919086364 100644
--- a/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -46,12 +46,13 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       lghi    %r7, 0
-;;       lgr     %r3, %r4
-;;       ag      %r3, 0x38(%r2)
-;;       aghik   %r6, %r3, 0x1000
+;;       lghi    %r3, 0
+;;       lgr     %r5, %r4
+;;       ag      %r5, 0x38(%r2)
+;;       aghik   %r7, %r5, 0x1000
 ;;       clgfi   %r4, 0xffffefff
-;;       locgrh  %r6, %r7
-;;       llc     %r2, 0(%r6)
+;;       locgrh  %r7, %r3
+;;       llc     %r2, 0(%r7)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index dff360de8e10..06369737feff 100644
--- a/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -47,13 +47,14 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       lghi    %r3, 0
-;;       lgr     %r5, %r4
-;;       ag      %r5, 0x38(%r2)
+;;       lghi    %r5, 0
+;;       lgr     %r3, %r4
+;;       ag      %r3, 0x38(%r2)
 ;;       llilh   %r2, 0xffff
-;;       agrk    %r7, %r5, %r2
+;;       agr     %r3, %r2
 ;;       clgfi   %r4, 0xffff
-;;       locgrh  %r7, %r3
-;;       llc     %r2, 0(%r7)
+;;       locgrh  %r3, %r5
+;;       llc     %r2, 0(%r3)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
index 690e5a4bd5d5..010a9a8d266c 100644
--- a/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
@@ -45,7 +45,8 @@
 ;;       stg     %r1, 0(%r15)
 ;;       clgfi   %r4, 0xffffffff
 ;;       jgh     0x78
-;;       lg      %r6, 0x38(%r2)
-;;       llc     %r2, 0(%r4, %r6)
+;;       lg      %r7, 0x38(%r2)
+;;       llc     %r7, 0(%r4, %r7)
+;;       llcr    %r2, %r7
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
index f6ab577c9e60..d557b44a8079 100644
--- a/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -47,7 +47,8 @@
 ;;       clgfi   %r4, 0xffffefff
 ;;       jgh     0x7c
 ;;       ag      %r4, 0x38(%r2)
-;;       lghi    %r7, 0x1000
-;;       llc     %r2, 0(%r7, %r4)
+;;       lghi    %r2, 0x1000
+;;       llc     %r2, 0(%r2, %r4)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index db2fe252a60c..0470a951bff2 100644
--- a/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -47,7 +47,8 @@
 ;;       clgfi   %r4, 0xffff
 ;;       jgh     0x7c
 ;;       ag      %r4, 0x38(%r2)
-;;       llilh   %r7, 0xffff
-;;       llc     %r2, 0(%r7, %r4)
+;;       llilh   %r2, 0xffff
+;;       llc     %r2, 0(%r2, %r4)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index 22ad5a12aead..7cb47297289b 100644
--- a/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -45,11 +45,12 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       lghi    %r6, 0
-;;       lgr     %r5, %r4
-;;       ag      %r5, 0x38(%r2)
+;;       lghi    %r7, 0
+;;       lgr     %r6, %r4
+;;       ag      %r6, 0x38(%r2)
 ;;       clgfi   %r4, 0xffffffff
-;;       locgrh  %r5, %r6
-;;       llc     %r2, 0(%r5)
+;;       locgrh  %r6, %r7
+;;       llc     %r2, 0(%r6)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index c3ab3e384b12..b9f79415038d 100644
--- a/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -46,12 +46,13 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       lghi    %r7, 0
-;;       lgr     %r3, %r4
-;;       ag      %r3, 0x38(%r2)
-;;       aghik   %r6, %r3, 0x1000
+;;       lghi    %r3, 0
+;;       lgr     %r5, %r4
+;;       ag      %r5, 0x38(%r2)
+;;       aghik   %r7, %r5, 0x1000
 ;;       clgfi   %r4, 0xffffefff
-;;       locgrh  %r6, %r7
-;;       llc     %r2, 0(%r6)
+;;       locgrh  %r7, %r3
+;;       llc     %r2, 0(%r7)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 04dccafa52c3..5acdf204329f 100644
--- a/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/s390x/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -47,13 +47,14 @@
 ;;       lgr     %r1, %r15
 ;;       aghi    %r15, -0xa0
 ;;       stg     %r1, 0(%r15)
-;;       lghi    %r3, 0
-;;       lgr     %r5, %r4
-;;       ag      %r5, 0x38(%r2)
+;;       lghi    %r5, 0
+;;       lgr     %r3, %r4
+;;       ag      %r3, 0x38(%r2)
 ;;       llilh   %r2, 0xffff
-;;       agrk    %r7, %r5, %r2
+;;       agr     %r3, %r2
 ;;       clgfi   %r4, 0xffff
-;;       locgrh  %r7, %r3
-;;       llc     %r2, 0(%r7)
+;;       locgrh  %r3, %r5
+;;       llc     %r2, 0(%r3)
+;;       llcr    %r2, %r2
 ;;       lmg     %r14, %r15, 0x110(%r15)
 ;;       br      %r14
diff --git a/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
index d6451d6a98a1..3b77078ee79c 100644
--- a/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
@@ -36,10 +36,11 @@
 ;;       movq    %rsp, %rbp
 ;;       movl    %edx, %esi
 ;;       cmpq    0x40(%rdi), %rsi
-;;       jae     0x3e
-;;   30: movq    0x38(%rdi), %rdi
-;;       movzbq  (%rdi, %rsi), %rax
+;;       jae     0x42
+;;   30: movq    0x38(%rdi), %r8
+;;       movzbq  (%r8, %rsi), %r8
+;;       movzbl  %r8b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   3e: ud2
+;;   42: ud2
diff --git a/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
index 6fde4b25259f..67d0b8038135 100644
--- a/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -40,10 +40,11 @@
 ;;       movl    %edx, %r8d
 ;;       subq    $0x1001, %rsi
 ;;       cmpq    %rsi, %r8
-;;       ja      0x6d
-;;   5b: movq    0x38(%rdi), %r9
-;;       movzbq  0x1000(%r9, %r8), %rax
+;;       ja      0x71
+;;   5b: movq    0x38(%rdi), %r10
+;;       movzbq  0x1000(%r10, %r8), %r10
+;;       movzbl  %r10b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   6d: ud2
+;;   71: ud2
diff --git a/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index c46bdd18f671..a0a98dab679f 100644
--- a/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -45,16 +45,19 @@
 ;;       movq    %rsp, %rbp
 ;;       movl    %edx, %esi
 ;;       movq    %rsi, %r8
-;;       addq    0x28(%rip), %r8
-;;       jb      0x74
+;;       addq    0x30(%rip), %r8
+;;       jb      0x78
 ;;   56: cmpq    0x40(%rdi), %r8
-;;       ja      0x76
+;;       ja      0x7a
 ;;   60: addq    0x38(%rdi), %rsi
-;;       movl    $0xffff0000, %r10d
-;;       movzbq  (%rsi, %r10), %rax
+;;       movl    $0xffff0000, %r11d
+;;       movzbq  (%rsi, %r11), %r11
+;;       movzbl  %r11b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   74: ud2
-;;   76: ud2
-;;   78: addl    %eax, (%rax)
+;;   78: ud2
+;;   7a: ud2
+;;   7c: addb    %al, (%rax)
+;;   7e: addb    %al, (%rax)
+;;   80: addl    %eax, (%rax)
diff --git a/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 7e1864503007..a3fe052305bc 100644
--- a/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -36,14 +36,15 @@
 ;; wasm[0]::function[1]:
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
-;;       movq    0x40(%rdi), %r9
-;;       movl    %edx, %r11d
-;;       xorq    %r10, %r10
-;;       movq    %r11, %r8
-;;       addq    0x38(%rdi), %r8
-;;       cmpq    %r9, %r11
-;;       cmovaeq %r10, %r8
-;;       movzbq  (%r8), %rax
+;;       movq    0x40(%rdi), %r10
+;;       movl    %edx, %eax
+;;       xorq    %r11, %r11
+;;       movq    %rax, %r9
+;;       addq    0x38(%rdi), %r9
+;;       cmpq    %r10, %rax
+;;       cmovaeq %r11, %r9
+;;       movzbq  (%r9), %r11
+;;       movzbl  %r11b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
diff --git a/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 6c3e21af44ec..f200f54af07e 100644
--- a/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -37,15 +37,16 @@
 ;; wasm[0]::function[1]:
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
-;;       movq    0x40(%rdi), %r8
-;;       movq    0x38(%rdi), %r11
-;;       movl    %edx, %eax
-;;       subq    $0x1001, %r8
-;;       xorq    %rcx, %rcx
-;;       leaq    0x1000(%r11, %rax), %r10
-;;       cmpq    %r8, %rax
-;;       cmovaq  %rcx, %r10
-;;       movzbq  (%r10), %rax
+;;       movq    0x40(%rdi), %r9
+;;       movq    0x38(%rdi), %rax
+;;       movl    %edx, %ecx
+;;       subq    $0x1001, %r9
+;;       xorq    %rdx, %rdx
+;;       leaq    0x1000(%rax, %rcx), %r11
+;;       cmpq    %r9, %rcx
+;;       cmovaq  %rdx, %r11
+;;       movzbq  (%r11), %rax
+;;       movzbl  %al, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
diff --git a/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index eaa4144b7115..afaafdf58ecf 100644
--- a/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -44,28 +44,24 @@
 ;; wasm[0]::function[1]:
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
-;;       movq    %rdi, %rcx
-;;       movl    %edx, %edi
-;;       movq    %rdi, %rax
-;;       addq    0x35(%rip), %rax
-;;       jb      0x9f
-;;   79: movq    %rcx, %rsi
-;;       movq    0x40(%rsi), %rdx
+;;       movl    %edx, %r8d
+;;       movq    %r8, %rax
+;;       addq    0x2f(%rip), %rax
+;;       jb      0x9d
+;;   77: movq    0x40(%rdi), %rdx
 ;;       xorq    %rcx, %rcx
-;;       addq    0x38(%rsi), %rdi
+;;       addq    0x38(%rdi), %r8
 ;;       movl    $0xffff0000, %esi
-;;       addq    %rdi, %rsi
+;;       addq    %r8, %rsi
 ;;       cmpq    %rdx, %rax
 ;;       cmovaq  %rcx, %rsi
 ;;       movzbq  (%rsi), %rax
+;;       movzbl  %al, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   9f: ud2
-;;   a1: addb    %al, (%rax)
-;;   a3: addb    %al, (%rax)
+;;   9d: ud2
+;;   9f: addb    %al, (%rcx)
+;;   a1: addb    %bh, %bh
+;;   a3: incl    (%rax)
 ;;   a5: addb    %al, (%rax)
-;;   a7: addb    %al, (%rcx)
-;;   a9: addb    %bh, %bh
-;;   ab: incl    (%rax)
-;;   ad: addb    %al, (%rax)
diff --git a/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
index 4dd57842c3af..d8080a1c6189 100644
--- a/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
@@ -36,10 +36,11 @@
 ;;       movq    %rsp, %rbp
 ;;       movl    %edx, %esi
 ;;       cmpq    0x40(%rdi), %rsi
-;;       jae     0x3e
-;;   30: movq    0x38(%rdi), %rdi
-;;       movzbq  (%rdi, %rsi), %rax
+;;       jae     0x42
+;;   30: movq    0x38(%rdi), %r8
+;;       movzbq  (%r8, %rsi), %r8
+;;       movzbl  %r8b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   3e: ud2
+;;   42: ud2
diff --git a/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
index 10754921fa46..5f1126894314 100644
--- a/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -36,10 +36,11 @@
 ;;       movq    %rsp, %rbp
 ;;       movl    %edx, %esi
 ;;       cmpq    0x40(%rdi), %rsi
-;;       ja      0x62
-;;   50: movq    0x38(%rdi), %rdi
-;;       movzbq  0x1000(%rdi, %rsi), %rax
+;;       ja      0x66
+;;   50: movq    0x38(%rdi), %r8
+;;       movzbq  0x1000(%r8, %rsi), %r8
+;;       movzbl  %r8b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   62: ud2
+;;   66: ud2
diff --git a/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 40d17e4aa409..c864ff32d2a4 100644
--- a/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -37,11 +37,12 @@
 ;;       movq    %rsp, %rbp
 ;;       movl    %edx, %esi
 ;;       cmpq    0x40(%rdi), %rsi
-;;       ja      0x64
+;;       ja      0x68
 ;;   50: addq    0x38(%rdi), %rsi
-;;       movl    $0xffff0000, %r8d
-;;       movzbq  (%rsi, %r8), %rax
+;;       movl    $0xffff0000, %r9d
+;;       movzbq  (%rsi, %r9), %r9
+;;       movzbl  %r9b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   64: ud2
+;;   68: ud2
diff --git a/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index b65829a1f3c6..7a1b0f9aab1f 100644
--- a/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -36,14 +36,15 @@
 ;; wasm[0]::function[1]:
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
-;;       movq    0x40(%rdi), %r9
-;;       movl    %edx, %r11d
-;;       xorq    %r10, %r10
-;;       movq    %r11, %r8
-;;       addq    0x38(%rdi), %r8
-;;       cmpq    %r9, %r11
-;;       cmovaeq %r10, %r8
-;;       movzbq  (%r8), %rax
+;;       movq    0x40(%rdi), %r10
+;;       movl    %edx, %eax
+;;       xorq    %r11, %r11
+;;       movq    %rax, %r9
+;;       addq    0x38(%rdi), %r9
+;;       cmpq    %r10, %rax
+;;       cmovaeq %r11, %r9
+;;       movzbq  (%r9), %r11
+;;       movzbl  %r11b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
diff --git a/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index e216a9dfd10f..c176618ce1b3 100644
--- a/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -36,14 +36,15 @@
 ;; wasm[0]::function[1]:
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
-;;       movq    0x40(%rdi), %r10
-;;       movq    0x38(%rdi), %rax
-;;       movl    %edx, %ecx
-;;       xorq    %r11, %r11
-;;       leaq    0x1000(%rax, %rcx), %r9
-;;       cmpq    %r10, %rcx
-;;       cmovaq  %r11, %r9
-;;       movzbq  (%r9), %rax
+;;       movq    0x40(%rdi), %r11
+;;       movq    0x38(%rdi), %rcx
+;;       movl    %edx, %edx
+;;       xorq    %rax, %rax
+;;       leaq    0x1000(%rcx, %rdx), %r10
+;;       cmpq    %r11, %rdx
+;;       cmovaq  %rax, %r10
+;;       movzbq  (%r10), %rax
+;;       movzbl  %al, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
diff --git a/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index b86151c596bb..f59ca91e7f95 100644
--- a/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -38,16 +38,17 @@
 ;; wasm[0]::function[1]:
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
-;;       movq    0x40(%rdi), %r11
-;;       movl    %edx, %ecx
-;;       xorq    %rax, %rax
-;;       movq    %rcx, %rdx
-;;       addq    0x38(%rdi), %rdx
-;;       movl    $0xffff0000, %esi
-;;       leaq    (%rdx, %rsi), %r10
-;;       cmpq    %r11, %rcx
-;;       cmovaq  %rax, %r10
-;;       movzbq  (%r10), %rax
+;;       movq    0x40(%rdi), %rax
+;;       movl    %edx, %edx
+;;       xorq    %rcx, %rcx
+;;       movq    %rdx, %rsi
+;;       addq    0x38(%rdi), %rsi
+;;       movl    $0xffff0000, %edi
+;;       leaq    (%rsi, %rdi), %r11
+;;       cmpq    %rax, %rdx
+;;       cmovaq  %rcx, %r11
+;;       movzbq  (%r11), %rax
+;;       movzbl  %al, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
diff --git a/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
index 977669f1d23d..0b1c8eb0b6fa 100644
--- a/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
@@ -34,10 +34,11 @@
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
 ;;       cmpq    0x40(%rdi), %rdx
-;;       jae     0x3c
-;;   2e: movq    0x38(%rdi), %rsi
-;;       movzbq  (%rsi, %rdx), %rax
+;;       jae     0x40
+;;   2e: movq    0x38(%rdi), %rdi
+;;       movzbq  (%rdi, %rdx), %rdi
+;;       movzbl  %dil, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   3c: ud2
+;;   40: ud2
diff --git a/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
index b5d1bbb55eb5..0af01b93c075 100644
--- a/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -38,10 +38,11 @@
 ;;       movq    0x40(%rdi), %rsi
 ;;       subq    $0x1001, %rsi
 ;;       cmpq    %rsi, %rdx
-;;       ja      0x6a
-;;   58: movq    0x38(%rdi), %r8
-;;       movzbq  0x1000(%r8, %rdx), %rax
+;;       ja      0x6e
+;;   58: movq    0x38(%rdi), %r9
+;;       movzbq  0x1000(%r9, %rdx), %r9
+;;       movzbl  %r9b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   6a: ud2
+;;   6e: ud2
diff --git a/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 6e7979f01710..e4463e87c547 100644
--- a/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -43,18 +43,21 @@
 ;; wasm[0]::function[1]:
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
-;;       movq    %rdx, %rsi
-;;       addq    0x2a(%rip), %rsi
-;;       jb      0x72
-;;   54: cmpq    0x40(%rdi), %rsi
-;;       ja      0x74
+;;       movq    %rdx, %r8
+;;       addq    0x32(%rip), %r8
+;;       jb      0x76
+;;   54: cmpq    0x40(%rdi), %r8
+;;       ja      0x78
 ;;   5e: addq    0x38(%rdi), %rdx
-;;       movl    $0xffff0000, %r9d
-;;       movzbq  (%rdx, %r9), %rax
+;;       movl    $0xffff0000, %r10d
+;;       movzbq  (%rdx, %r10), %r10
+;;       movzbl  %r10b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   72: ud2
-;;   74: ud2
-;;   76: addb    %al, (%rax)
-;;   78: addl    %eax, (%rax)
+;;   76: ud2
+;;   78: ud2
+;;   7a: addb    %al, (%rax)
+;;   7c: addb    %al, (%rax)
+;;   7e: addb    %al, (%rax)
+;;   80: addl    %eax, (%rax)
diff --git a/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 3ec0f8333416..8d5a279337d6 100644
--- a/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -35,13 +35,14 @@
 ;; wasm[0]::function[1]:
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
-;;       movq    0x40(%rdi), %r9
-;;       xorq    %r8, %r8
-;;       movq    %rdx, %r10
-;;       addq    0x38(%rdi), %r10
-;;       cmpq    %r9, %rdx
-;;       cmovaeq %r8, %r10
-;;       movzbq  (%r10), %rax
+;;       movq    0x40(%rdi), %r10
+;;       xorq    %r9, %r9
+;;       movq    %rdx, %r8
+;;       addq    0x38(%rdi), %r8
+;;       cmpq    %r10, %rdx
+;;       cmovaeq %r9, %r8
+;;       movzbq  (%r8), %r10
+;;       movzbl  %r10b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
diff --git a/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index f948fd3b4d65..2aa1dfbf39d2 100644
--- a/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -36,14 +36,15 @@
 ;; wasm[0]::function[1]:
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
-;;       movq    0x40(%rdi), %r8
-;;       movq    0x38(%rdi), %r11
-;;       subq    $0x1001, %r8
-;;       xorq    %r10, %r10
-;;       leaq    0x1000(%r11, %rdx), %r9
-;;       cmpq    %r8, %rdx
-;;       cmovaq  %r10, %r9
-;;       movzbq  (%r9), %rax
+;;       movq    0x40(%rdi), %r9
+;;       movq    0x38(%rdi), %rax
+;;       subq    $0x1001, %r9
+;;       xorq    %r11, %r11
+;;       leaq    0x1000(%rax, %rdx), %r10
+;;       cmpq    %r9, %rdx
+;;       cmovaq  %r11, %r10
+;;       movzbq  (%r10), %rax
+;;       movzbl  %al, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
diff --git a/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index f5a1d6641718..460fbaf875f5 100644
--- a/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -44,25 +44,22 @@
 ;; wasm[0]::function[1]:
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
-;;       movq    %rdx, %r11
-;;       addq    0x32(%rip), %r11
-;;       jb      0x77
-;;   54: movq    0x40(%rdi), %rcx
-;;       xorq    %rax, %rax
+;;       movq    %rdx, %rax
+;;       addq    0x32(%rip), %rax
+;;       jb      0x7a
+;;   54: movq    0x40(%rdi), %rsi
+;;       xorq    %rcx, %rcx
 ;;       addq    0x38(%rdi), %rdx
-;;       movl    $0xffff0000, %esi
-;;       addq    %rsi, %rdx
-;;       cmpq    %rcx, %r11
-;;       cmovaq  %rax, %rdx
+;;       movl    $0xffff0000, %edi
+;;       addq    %rdi, %rdx
+;;       cmpq    %rsi, %rax
+;;       cmovaq  %rcx, %rdx
 ;;       movzbq  (%rdx), %rax
+;;       movzbl  %al, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   77: ud2
-;;   79: addb    %al, (%rax)
-;;   7b: addb    %al, (%rax)
-;;   7d: addb    %al, (%rax)
-;;   7f: addb    %al, (%rcx)
-;;   81: addb    %bh, %bh
-;;   83: incl    (%rax)
-;;   85: addb    %al, (%rax)
+;;   7a: ud2
+;;   7c: addb    %al, (%rax)
+;;   7e: addb    %al, (%rax)
+;;   80: addl    %eax, (%rax)
diff --git a/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
index d8472853a757..0ee628279fef 100644
--- a/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
@@ -34,10 +34,11 @@
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
 ;;       cmpq    0x40(%rdi), %rdx
-;;       jae     0x3c
-;;   2e: movq    0x38(%rdi), %rsi
-;;       movzbq  (%rsi, %rdx), %rax
+;;       jae     0x40
+;;   2e: movq    0x38(%rdi), %rdi
+;;       movzbq  (%rdi, %rdx), %rdi
+;;       movzbl  %dil, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   3c: ud2
+;;   40: ud2
diff --git a/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
index bf4700df796c..f1a588e8c2c3 100644
--- a/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -34,10 +34,11 @@
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
 ;;       cmpq    0x40(%rdi), %rdx
-;;       ja      0x40
-;;   2e: movq    0x38(%rdi), %rsi
-;;       movzbq  0x1000(%rsi, %rdx), %rax
+;;       ja      0x44
+;;   2e: movq    0x38(%rdi), %rdi
+;;       movzbq  0x1000(%rdi, %rdx), %rdi
+;;       movzbl  %dil, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   40: ud2
+;;   44: ud2
diff --git a/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index de7e2c28aad3..8d7630d8b854 100644
--- a/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -35,11 +35,12 @@
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
 ;;       cmpq    0x40(%rdi), %rdx
-;;       ja      0x61
+;;       ja      0x66
 ;;   4e: addq    0x38(%rdi), %rdx
-;;       movl    $0xffff0000, %edi
-;;       movzbq  (%rdx, %rdi), %rax
+;;       movl    $0xffff0000, %r8d
+;;       movzbq  (%rdx, %r8), %r8
+;;       movzbl  %r8b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   61: ud2
+;;   66: ud2
diff --git a/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index 269e328cd11c..14e0d2585382 100644
--- a/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -35,13 +35,14 @@
 ;; wasm[0]::function[1]:
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
-;;       movq    0x40(%rdi), %r9
-;;       xorq    %r8, %r8
-;;       movq    %rdx, %r10
-;;       addq    0x38(%rdi), %r10
-;;       cmpq    %r9, %rdx
-;;       cmovaeq %r8, %r10
-;;       movzbq  (%r10), %rax
+;;       movq    0x40(%rdi), %r10
+;;       xorq    %r9, %r9
+;;       movq    %rdx, %r8
+;;       addq    0x38(%rdi), %r8
+;;       cmpq    %r10, %rdx
+;;       cmovaeq %r9, %r8
+;;       movzbq  (%r8), %r10
+;;       movzbl  %r10b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
diff --git a/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index 7005f734a5db..c9e6eade7881 100644
--- a/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -35,13 +35,14 @@
 ;; wasm[0]::function[1]:
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
-;;       movq    0x40(%rdi), %r9
-;;       movq    0x38(%rdi), %r11
-;;       xorq    %r10, %r10
-;;       leaq    0x1000(%r11, %rdx), %r8
-;;       cmpq    %r9, %rdx
-;;       cmovaq  %r10, %r8
-;;       movzbq  (%r8), %rax
+;;       movq    0x40(%rdi), %r10
+;;       movq    0x38(%rdi), %rax
+;;       xorq    %r11, %r11
+;;       leaq    0x1000(%rax, %rdx), %r9
+;;       cmpq    %r10, %rdx
+;;       cmovaq  %r11, %r9
+;;       movzbq  (%r9), %r11
+;;       movzbl  %r11b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
diff --git a/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index f3cc89850b00..06105d950d98 100644
--- a/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -37,15 +37,16 @@
 ;; wasm[0]::function[1]:
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
-;;       movq    0x40(%rdi), %r11
-;;       xorq    %r10, %r10
-;;       movq    %rdx, %rax
-;;       addq    0x38(%rdi), %rax
-;;       movl    $0xffff0000, %ecx
-;;       leaq    (%rax, %rcx), %r9
-;;       cmpq    %r11, %rdx
-;;       cmovaq  %r10, %r9
-;;       movzbq  (%r9), %rax
+;;       movq    0x40(%rdi), %rax
+;;       xorq    %r11, %r11
+;;       movq    %rdx, %rcx
+;;       addq    0x38(%rdi), %rcx
+;;       movl    $0xffff0000, %esi
+;;       leaq    (%rcx, %rsi), %r10
+;;       cmpq    %rax, %rdx
+;;       cmovaq  %r11, %r10
+;;       movzbq  (%r10), %rax
+;;       movzbl  %al, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
diff --git a/tests/disas/load-store/x64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/x64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
index 2e1baa117538..0645121c2686 100644
--- a/tests/disas/load-store/x64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/x64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
@@ -33,7 +33,8 @@
 ;;       movq    %rsp, %rbp
 ;;       movq    0x38(%rdi), %rsi
 ;;       movl    %edx, %edi
-;;       movzbq  (%rsi, %rdi), %rax
+;;       movzbq  (%rsi, %rdi), %rsi
+;;       movzbl  %sil, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
diff --git a/tests/disas/load-store/x64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/x64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
index 3ed0eb9837d4..f6bed8be170d 100644
--- a/tests/disas/load-store/x64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -38,13 +38,16 @@
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
 ;;       movl    %edx, %esi
-;;       cmpq    0x1b(%rip), %rsi
-;;       ja      0x65
-;;   53: movq    0x38(%rdi), %rdi
-;;       movzbq  0x1000(%rdi, %rsi), %rax
+;;       cmpq    0x23(%rip), %rsi
+;;       ja      0x69
+;;   53: movq    0x38(%rdi), %r8
+;;       movzbq  0x1000(%r8, %rsi), %r8
+;;       movzbl  %r8b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   65: ud2
-;;   67: addb    %bh, %bh
-;;   69: outl    %eax, %dx
+;;   69: ud2
+;;   6b: addb    %al, (%rax)
+;;   6d: addb    %al, (%rax)
+;;   6f: addb    %bh, %bh
+;;   71: outl    %eax, %dx
diff --git a/tests/disas/load-store/x64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/x64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index e8c5efb72968..8df9db9420bf 100644
--- a/tests/disas/load-store/x64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -37,11 +37,12 @@
 ;;       movq    %rsp, %rbp
 ;;       movl    %edx, %esi
 ;;       cmpq    $0xffff, %rsi
-;;       ja      0x67
+;;       ja      0x6b
 ;;   53: addq    0x38(%rdi), %rsi
-;;       movl    $0xffff0000, %r8d
-;;       movzbq  (%rsi, %r8), %rax
+;;       movl    $0xffff0000, %r9d
+;;       movzbq  (%rsi, %r9), %r9
+;;       movzbl  %r9b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   67: ud2
+;;   6b: ud2
diff --git a/tests/disas/load-store/x64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/x64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
index f748aee725e6..2dd8bf6d389b 100644
--- a/tests/disas/load-store/x64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/x64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -33,7 +33,8 @@
 ;;       movq    %rsp, %rbp
 ;;       movq    0x38(%rdi), %rsi
 ;;       movl    %edx, %edi
-;;       movzbq  (%rsi, %rdi), %rax
+;;       movzbq  (%rsi, %rdi), %rsi
+;;       movzbl  %sil, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
diff --git a/tests/disas/load-store/x64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/x64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 3a996fce707f..4e4b5c14c8c7 100644
--- a/tests/disas/load-store/x64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -40,16 +40,15 @@
 ;; wasm[0]::function[1]:
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
-;;       movl    %edx, %r10d
-;;       xorq    %r9, %r9
-;;       movq    0x38(%rdi), %r11
-;;       leaq    0x1000(%r11, %r10), %r8
-;;       cmpq    0x13(%rip), %r10
-;;       cmovaq  %r9, %r8
-;;       movzbq  (%r8), %rax
+;;       movl    %edx, %r11d
+;;       xorq    %r10, %r10
+;;       movq    0x38(%rdi), %rax
+;;       leaq    0x1000(%rax, %r11), %r9
+;;       cmpq    0x13(%rip), %r11
+;;       cmovaq  %r10, %r9
+;;       movzbq  (%r9), %r11
+;;       movzbl  %r11b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   6a: addb    %al, (%rax)
-;;   6c: addb    %al, (%rax)
 ;;   6e: addb    %al, (%rax)
diff --git a/tests/disas/load-store/x64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/x64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 6c9be967ee0f..f275181e4d7e 100644
--- a/tests/disas/load-store/x64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -37,15 +37,16 @@
 ;; wasm[0]::function[1]:
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
-;;       movl    %edx, %r11d
-;;       xorq    %r10, %r10
-;;       movq    %r11, %rax
-;;       addq    0x38(%rdi), %rax
-;;       movl    $0xffff0000, %ecx
-;;       leaq    (%rax, %rcx), %r9
-;;       cmpq    $0xffff, %r11
-;;       cmovaq  %r10, %r9
-;;       movzbq  (%r9), %rax
+;;       movl    %edx, %eax
+;;       xorq    %r11, %r11
+;;       movq    %rax, %rcx
+;;       addq    0x38(%rdi), %rcx
+;;       movl    $0xffff0000, %edx
+;;       leaq    (%rcx, %rdx), %r10
+;;       cmpq    $0xffff, %rax
+;;       cmovaq  %r11, %r10
+;;       movzbq  (%r10), %rax
+;;       movzbl  %al, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
diff --git a/tests/disas/load-store/x64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/x64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
index dfe372fcf148..7a183f485259 100644
--- a/tests/disas/load-store/x64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/x64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
@@ -33,7 +33,8 @@
 ;;       movq    %rsp, %rbp
 ;;       movq    0x38(%rdi), %rsi
 ;;       movl    %edx, %edi
-;;       movzbq  (%rsi, %rdi), %rax
+;;       movzbq  (%rsi, %rdi), %rsi
+;;       movzbl  %sil, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
diff --git a/tests/disas/load-store/x64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/x64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
index f6ab3b83deb8..96385d7e2105 100644
--- a/tests/disas/load-store/x64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -33,7 +33,8 @@
 ;;       movq    %rsp, %rbp
 ;;       movq    0x38(%rdi), %rsi
 ;;       movl    %edx, %edi
-;;       movzbq  0x1000(%rsi, %rdi), %rax
+;;       movzbq  0x1000(%rsi, %rdi), %rsi
+;;       movzbl  %sil, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
diff --git a/tests/disas/load-store/x64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/x64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index d19090c1cc3c..c9a948372974 100644
--- a/tests/disas/load-store/x64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -35,7 +35,8 @@
 ;;       movl    %edx, %esi
 ;;       addq    0x38(%rdi), %rsi
 ;;       movl    $0xffff0000, %edi
-;;       movzbq  (%rsi, %rdi), %rax
+;;       movzbq  (%rsi, %rdi), %rdi
+;;       movzbl  %dil, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
diff --git a/tests/disas/load-store/x64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/x64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index 5a4a97b70ecd..dc962ff6656b 100644
--- a/tests/disas/load-store/x64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/x64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -33,7 +33,8 @@
 ;;       movq    %rsp, %rbp
 ;;       movq    0x38(%rdi), %rsi
 ;;       movl    %edx, %edi
-;;       movzbq  (%rsi, %rdi), %rax
+;;       movzbq  (%rsi, %rdi), %rsi
+;;       movzbl  %sil, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
diff --git a/tests/disas/load-store/x64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/x64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index 8320af5b5016..d10e885ea4ae 100644
--- a/tests/disas/load-store/x64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -33,7 +33,8 @@
 ;;       movq    %rsp, %rbp
 ;;       movq    0x38(%rdi), %rsi
 ;;       movl    %edx, %edi
-;;       movzbq  0x1000(%rsi, %rdi), %rax
+;;       movzbq  0x1000(%rsi, %rdi), %rsi
+;;       movzbl  %sil, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
diff --git a/tests/disas/load-store/x64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/x64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 2feb9b7846c1..837cfcc4428b 100644
--- a/tests/disas/load-store/x64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -35,7 +35,8 @@
 ;;       movl    %edx, %esi
 ;;       addq    0x38(%rdi), %rsi
 ;;       movl    $0xffff0000, %edi
-;;       movzbq  (%rsi, %rdi), %rax
+;;       movzbq  (%rsi, %rdi), %rdi
+;;       movzbl  %dil, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
diff --git a/tests/disas/load-store/x64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/x64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
index 6c3359fbd293..6f1ca9ae061f 100644
--- a/tests/disas/load-store/x64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/x64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
@@ -35,14 +35,13 @@
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
 ;;       cmpq    0x1d(%rip), %rdx
-;;       ja      0x5f
-;;   51: movq    0x38(%rdi), %rsi
-;;       movzbq  (%rsi, %rdx), %rax
+;;       ja      0x63
+;;   51: movq    0x38(%rdi), %rdi
+;;       movzbq  (%rdi, %rdx), %rdi
+;;       movzbl  %dil, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   5f: ud2
-;;   61: addb    %al, (%rax)
-;;   63: addb    %al, (%rax)
+;;   63: ud2
 ;;   65: addb    %al, (%rax)
 ;;   67: addb    %bh, %bh
diff --git a/tests/disas/load-store/x64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/x64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
index d16cc8e7ec1c..86a4b3db2cd3 100644
--- a/tests/disas/load-store/x64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -37,14 +37,17 @@
 ;; wasm[0]::function[1]:
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
-;;       cmpq    0x1d(%rip), %rdx
-;;       ja      0x63
-;;   51: movq    0x38(%rdi), %rsi
-;;       movzbq  0x1000(%rsi, %rdx), %rax
+;;       cmpq    0x25(%rip), %rdx
+;;       ja      0x67
+;;   51: movq    0x38(%rdi), %rdi
+;;       movzbq  0x1000(%rdi, %rdx), %rdi
+;;       movzbl  %dil, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   63: ud2
-;;   65: addb    %al, (%rax)
-;;   67: addb    %bh, %bh
-;;   69: outl    %eax, %dx
+;;   67: ud2
+;;   69: addb    %al, (%rax)
+;;   6b: addb    %al, (%rax)
+;;   6d: addb    %al, (%rax)
+;;   6f: addb    %bh, %bh
+;;   71: outl    %eax, %dx
diff --git a/tests/disas/load-store/x64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/x64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 172e764fb57f..e14aad9d59c1 100644
--- a/tests/disas/load-store/x64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -35,11 +35,12 @@
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
 ;;       cmpq    $0xffff, %rdx
-;;       ja      0x64
+;;       ja      0x69
 ;;   51: addq    0x38(%rdi), %rdx
-;;       movl    $0xffff0000, %edi
-;;       movzbq  (%rdx, %rdi), %rax
+;;       movl    $0xffff0000, %r8d
+;;       movzbq  (%rdx, %r8), %r8
+;;       movzbl  %r8b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   64: ud2
+;;   69: ud2
diff --git a/tests/disas/load-store/x64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/x64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 6b5ce1034600..8ef5643e016a 100644
--- a/tests/disas/load-store/x64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/x64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -37,14 +37,14 @@
 ;; wasm[0]::function[1]:
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
-;;       movq    %rdi, %r8
-;;       xorq    %rdi, %rdi
-;;       movq    %r8, %r10
-;;       movq    %rdx, %rsi
-;;       addq    0x38(%r10), %rsi
-;;       cmpq    0xd(%rip), %rdx
-;;       cmovaq  %rdi, %rsi
-;;       movzbq  (%rsi), %rax
+;;       xorq    %r8, %r8
+;;       movq    %rdx, %r9
+;;       addq    0x38(%rdi), %r9
+;;       cmpq    0x13(%rip), %rdx
+;;       cmovaq  %r8, %r9
+;;       movzbq  (%r9), %r9
+;;       movzbl  %r9b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
+;;   66: addb    %al, (%rax)
diff --git a/tests/disas/load-store/x64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/x64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 80f2ef057a55..bfb045283dd4 100644
--- a/tests/disas/load-store/x64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -37,14 +37,17 @@
 ;; wasm[0]::function[1]:
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
-;;       xorq    %r8, %r8
-;;       movq    0x38(%rdi), %r9
-;;       leaq    0x1000(%r9, %rdx), %rdi
-;;       cmpq    0xe(%rip), %rdx
-;;       cmovaq  %r8, %rdi
-;;       movzbq  (%rdi), %rax
+;;       xorq    %r9, %r9
+;;       movq    0x38(%rdi), %r10
+;;       leaq    0x1000(%r10, %rdx), %r8
+;;       cmpq    0x16(%rip), %rdx
+;;       cmovaq  %r9, %r8
+;;       movzbq  (%r8), %r10
+;;       movzbl  %r10b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   67: addb    %bh, %bh
-;;   69: outl    %eax, %dx
+;;   6b: addb    %al, (%rax)
+;;   6d: addb    %al, (%rax)
+;;   6f: addb    %bh, %bh
+;;   71: outl    %eax, %dx
diff --git a/tests/disas/load-store/x64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/x64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 501f2011d3bb..ab7f114da538 100644
--- a/tests/disas/load-store/x64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -36,14 +36,15 @@
 ;; wasm[0]::function[1]:
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
-;;       xorq    %r9, %r9
-;;       movq    %rdx, %r10
-;;       addq    0x38(%rdi), %r10
-;;       movl    $0xffff0000, %r11d
-;;       leaq    (%r10, %r11), %r8
+;;       xorq    %r10, %r10
+;;       movq    %rdx, %r11
+;;       addq    0x38(%rdi), %r11
+;;       movl    $0xffff0000, %eax
+;;       leaq    (%r11, %rax), %r9
 ;;       cmpq    $0xffff, %rdx
-;;       cmovaq  %r9, %r8
-;;       movzbq  (%r8), %rax
+;;       cmovaq  %r10, %r9
+;;       movzbq  (%r9), %r11
+;;       movzbl  %r11b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
diff --git a/tests/disas/load-store/x64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat b/tests/disas/load-store/x64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
index ecbbd649aff7..7a1f3758b7b8 100644
--- a/tests/disas/load-store/x64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/x64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
@@ -35,14 +35,13 @@
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
 ;;       cmpq    0x1d(%rip), %rdx
-;;       ja      0x5f
-;;   51: movq    0x38(%rdi), %rsi
-;;       movzbq  (%rsi, %rdx), %rax
+;;       ja      0x63
+;;   51: movq    0x38(%rdi), %rdi
+;;       movzbq  (%rdi, %rdx), %rdi
+;;       movzbl  %dil, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   5f: ud2
-;;   61: addb    %al, (%rax)
-;;   63: addb    %al, (%rax)
+;;   63: ud2
 ;;   65: addb    %al, (%rax)
 ;;   67: addb    %bh, %bh
diff --git a/tests/disas/load-store/x64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/x64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
index b46f6f89b1d2..85d207b7e4a9 100644
--- a/tests/disas/load-store/x64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -37,14 +37,17 @@
 ;; wasm[0]::function[1]:
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
-;;       cmpq    0x1d(%rip), %rdx
-;;       ja      0x63
-;;   51: movq    0x38(%rdi), %rsi
-;;       movzbq  0x1000(%rsi, %rdx), %rax
+;;       cmpq    0x25(%rip), %rdx
+;;       ja      0x67
+;;   51: movq    0x38(%rdi), %rdi
+;;       movzbq  0x1000(%rdi, %rdx), %rdi
+;;       movzbl  %dil, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   63: ud2
-;;   65: addb    %al, (%rax)
-;;   67: addb    %bh, %bh
-;;   69: outl    %eax, %dx
+;;   67: ud2
+;;   69: addb    %al, (%rax)
+;;   6b: addb    %al, (%rax)
+;;   6d: addb    %al, (%rax)
+;;   6f: addb    %bh, %bh
+;;   71: outl    %eax, %dx
diff --git a/tests/disas/load-store/x64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/x64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index d50cbcc90752..7c54abf8bb40 100644
--- a/tests/disas/load-store/x64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -35,11 +35,12 @@
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
 ;;       cmpq    $0xffff, %rdx
-;;       ja      0x64
+;;       ja      0x69
 ;;   51: addq    0x38(%rdi), %rdx
-;;       movl    $0xffff0000, %edi
-;;       movzbq  (%rdx, %rdi), %rax
+;;       movl    $0xffff0000, %r8d
+;;       movzbq  (%rdx, %r8), %r8
+;;       movzbl  %r8b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   64: ud2
+;;   69: ud2
diff --git a/tests/disas/load-store/x64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/tests/disas/load-store/x64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index 82848d5099a9..50de3957cdee 100644
--- a/tests/disas/load-store/x64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/tests/disas/load-store/x64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -37,14 +37,14 @@
 ;; wasm[0]::function[1]:
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
-;;       movq    %rdi, %r8
-;;       xorq    %rdi, %rdi
-;;       movq    %r8, %r10
-;;       movq    %rdx, %rsi
-;;       addq    0x38(%r10), %rsi
-;;       cmpq    0xd(%rip), %rdx
-;;       cmovaq  %rdi, %rsi
-;;       movzbq  (%rsi), %rax
+;;       xorq    %r8, %r8
+;;       movq    %rdx, %r9
+;;       addq    0x38(%rdi), %r9
+;;       cmpq    0x13(%rip), %rdx
+;;       cmovaq  %r8, %r9
+;;       movzbq  (%r9), %r9
+;;       movzbl  %r9b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
+;;   66: addb    %al, (%rax)
diff --git a/tests/disas/load-store/x64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/tests/disas/load-store/x64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index 0a1cf839eab2..ad3e367adf8e 100644
--- a/tests/disas/load-store/x64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -37,14 +37,17 @@
 ;; wasm[0]::function[1]:
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
-;;       xorq    %r8, %r8
-;;       movq    0x38(%rdi), %r9
-;;       leaq    0x1000(%r9, %rdx), %rdi
-;;       cmpq    0xe(%rip), %rdx
-;;       cmovaq  %r8, %rdi
-;;       movzbq  (%rdi), %rax
+;;       xorq    %r9, %r9
+;;       movq    0x38(%rdi), %r10
+;;       leaq    0x1000(%r10, %rdx), %r8
+;;       cmpq    0x16(%rip), %rdx
+;;       cmovaq  %r9, %r8
+;;       movzbq  (%r8), %r10
+;;       movzbl  %r10b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   67: addb    %bh, %bh
-;;   69: outl    %eax, %dx
+;;   6b: addb    %al, (%rax)
+;;   6d: addb    %al, (%rax)
+;;   6f: addb    %bh, %bh
+;;   71: outl    %eax, %dx
diff --git a/tests/disas/load-store/x64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/tests/disas/load-store/x64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 46bc33c20659..f1c333207e9a 100644
--- a/tests/disas/load-store/x64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/tests/disas/load-store/x64/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -36,14 +36,15 @@
 ;; wasm[0]::function[1]:
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
-;;       xorq    %r9, %r9
-;;       movq    %rdx, %r10
-;;       addq    0x38(%rdi), %r10
-;;       movl    $0xffff0000, %r11d
-;;       leaq    (%r10, %r11), %r8
+;;       xorq    %r10, %r10
+;;       movq    %rdx, %r11
+;;       addq    0x38(%rdi), %r11
+;;       movl    $0xffff0000, %eax
+;;       leaq    (%r11, %rax), %r9
 ;;       cmpq    $0xffff, %rdx
-;;       cmovaq  %r9, %r8
-;;       movzbq  (%r8), %rax
+;;       cmovaq  %r10, %r9
+;;       movzbq  (%r9), %r11
+;;       movzbl  %r11b, %eax
 ;;       movq    %rbp, %rsp
 ;;       popq    %rbp
 ;;       retq
diff --git a/tests/disas/non-fixed-size-memory.wat b/tests/disas/non-fixed-size-memory.wat
index 871c6a693ebf..2ce9e8f1a2b0 100644
--- a/tests/disas/non-fixed-size-memory.wat
+++ b/tests/disas/non-fixed-size-memory.wat
@@ -38,7 +38,8 @@
 ;; @0041                               trapnz v6, heap_oob
 ;; @0041                               v7 = load.i64 notrap aligned can_move region2 v0+56
 ;; @0041                               v8 = iadd v7, v4
-;; @0041                               istore8 little region4 v3, v8
+;; @0041                               v9 = ireduce.i8 v3
+;; @0041                               store little region4 v9, v8
 ;; @0044                               jump block1
 ;;
 ;;                                 block1:
@@ -63,9 +64,10 @@
 ;; @0049                               trapnz v5, heap_oob
 ;; @0049                               v6 = load.i64 notrap aligned can_move region2 v0+56
 ;; @0049                               v7 = iadd v6, v3
-;; @0049                               v8 = uload8.i32 little region4 v7
+;; @0049                               v8 = load.i8 little region4 v7
+;; @0049                               v9 = uextend.i32 v8
 ;; @004c                               jump block1
 ;;
 ;;                                 block1:
-;; @004c                               return v8
+;; @004c                               return v9
 ;; }
diff --git a/tests/disas/pulley/coremark-1.wat b/tests/disas/pulley/coremark-1.wat
index a1e637752111..83f0d3578d64 100644
--- a/tests/disas/pulley/coremark-1.wat
+++ b/tests/disas/pulley/coremark-1.wat
@@ -70,28 +70,30 @@
   (func $other)
 )
 ;; wasm[0]::function[0]:
-;;       push_frame_save 16, x24
+;;       push_frame_save 16, x26
 ;;       xzero x6
 ;;       xload64le_o32 x1, x0, 56
 ;;       xload64le_o32 x8, x0, 64
 ;;       xload16le_u32_g32 x7, x1, x8, x2, 0
 ;;       xload16le_u32_g32 x8, x1, x8, x3, 0
 ;;       xsub32_u8 x4, x4, 1
+;;       zext16 x7, x7
+;;       zext16 x8, x8
 ;;       xmul32 x7, x7, x8
 ;;       xshr32_u_u6 x8, x7, 2
 ;;       xband32_s8 x8, x8, 15
 ;;       xshr32_u_u6 x7, x7, 5
 ;;       xband32_s8 x7, x7, 127
 ;;       xmadd32 x6, x8, x7, x6
-;;       xmov x24, x6
+;;       xmov x26, x6
 ;;       xadd32 x2, x2, x5
 ;;       xadd32_u8 x3, x3, 2
-;;       br_if_not32 x4, 0xe    // target = 0x53
-;;   4b: xmov x6, x24
-;;       jump -0x40    // target = 0xe
-;;   53: call2 x0, x0, 0x10    // target = 0x63
-;;       xmov x0, x24
-;;       pop_frame_restore 16, x24
+;;       br_if_not32 x4, 0xe    // target = 0x59
+;;   51: xmov x6, x26
+;;       jump -0x46    // target = 0xe
+;;   59: call2 x0, x0, 0x10    // target = 0x69
+;;       xmov x0, x26
+;;       pop_frame_restore 16, x26
 ;;       ret
 ;;
 ;; wasm[0]::function[1]::other:
diff --git a/tests/disas/pulley/pulley32_memory32.wat b/tests/disas/pulley/pulley32_memory32.wat
index 6f96521d5ae4..c497dafea34b 100644
--- a/tests/disas/pulley/pulley32_memory32.wat
+++ b/tests/disas/pulley/pulley32_memory32.wat
@@ -54,17 +54,19 @@
 )
 ;; wasm[0]::function[0]::load8:
 ;;       push_frame
-;;       xload32le_o32 x5, x0, 32
-;;       xload32le_o32 x6, x0, 28
-;;       xload8_u32_g32 x0, x6, x5, x2, 0
+;;       xload32le_o32 x6, x0, 32
+;;       xload32le_o32 x7, x0, 28
+;;       xload8_u32_g32 x6, x7, x6, x2, 0
+;;       zext8 x0, x6
 ;;       pop_frame
 ;;       ret
 ;;
 ;; wasm[0]::function[1]::load16:
 ;;       push_frame
-;;       xload32le_o32 x5, x0, 32
-;;       xload32le_o32 x6, x0, 28
-;;       xload16le_u32_g32 x0, x6, x5, x2, 0
+;;       xload32le_o32 x6, x0, 32
+;;       xload32le_o32 x7, x0, 28
+;;       xload16le_u32_g32 x6, x7, x6, x2, 0
+;;       zext16 x0, x6
 ;;       pop_frame
 ;;       ret
 ;;
@@ -118,17 +120,19 @@
 ;;
 ;; wasm[0]::function[8]::load8_offset:
 ;;       push_frame
-;;       xload32le_o32 x5, x0, 32
-;;       xload32le_o32 x6, x0, 28
-;;       xload8_u32_g32 x0, x6, x5, x2, 32
+;;       xload32le_o32 x6, x0, 32
+;;       xload32le_o32 x7, x0, 28
+;;       xload8_u32_g32 x6, x7, x6, x2, 32
+;;       zext8 x0, x6
 ;;       pop_frame
 ;;       ret
 ;;
 ;; wasm[0]::function[9]::load16_offset:
 ;;       push_frame
-;;       xload32le_o32 x5, x0, 32
-;;       xload32le_o32 x6, x0, 28
-;;       xload16le_u32_g32 x0, x6, x5, x2, 32
+;;       xload32le_o32 x6, x0, 32
+;;       xload32le_o32 x7, x0, 28
+;;       xload16le_u32_g32 x6, x7, x6, x2, 32
+;;       zext16 x0, x6
 ;;       pop_frame
 ;;       ret
 ;;
diff --git a/tests/disas/pulley/pulley64_memory32.wat b/tests/disas/pulley/pulley64_memory32.wat
index ee5d2c39049b..4dd536f6ad68 100644
--- a/tests/disas/pulley/pulley64_memory32.wat
+++ b/tests/disas/pulley/pulley64_memory32.wat
@@ -59,20 +59,22 @@
 )
 ;; wasm[0]::function[0]::load8:
 ;;       push_frame
-;;       xload64le_o32 x5, x0, 64
+;;       xload64le_o32 x6, x0, 64
 ;;       ╰─╼ addrmap: 0x47
-;;       xload64le_o32 x6, x0, 56
-;;       xload8_u32_g32 x0, x6, x5, x2, 0
+;;       xload64le_o32 x7, x0, 56
+;;       xload8_u32_g32 x6, x7, x6, x2, 0
+;;       zext8 x0, x6
 ;;       pop_frame
 ;;       ╰─╼ addrmap: 0x4a
 ;;       ret
 ;;
 ;; wasm[0]::function[1]::load16:
 ;;       push_frame
-;;       xload64le_o32 x5, x0, 64
+;;       xload64le_o32 x6, x0, 64
 ;;       ╰─╼ addrmap: 0x4f
-;;       xload64le_o32 x6, x0, 56
-;;       xload16le_u32_g32 x0, x6, x5, x2, 0
+;;       xload64le_o32 x7, x0, 56
+;;       xload16le_u32_g32 x6, x7, x6, x2, 0
+;;       zext16 x0, x6
 ;;       pop_frame
 ;;       ╰─╼ addrmap: 0x52
 ;;       ret
@@ -139,20 +141,22 @@
 ;;
 ;; wasm[0]::function[8]::load8_offset:
 ;;       push_frame
-;;       xload64le_o32 x5, x0, 64
+;;       xload64le_o32 x6, x0, 64
 ;;       ╰─╼ addrmap: 0x8f
-;;       xload64le_o32 x6, x0, 56
-;;       xload8_u32_g32 x0, x6, x5, x2, 32
+;;       xload64le_o32 x7, x0, 56
+;;       xload8_u32_g32 x6, x7, x6, x2, 32
+;;       zext8 x0, x6
 ;;       pop_frame
 ;;       ╰─╼ addrmap: 0x92
 ;;       ret
 ;;
 ;; wasm[0]::function[9]::load16_offset:
 ;;       push_frame
-;;       xload64le_o32 x5, x0, 64
+;;       xload64le_o32 x6, x0, 64
 ;;       ╰─╼ addrmap: 0x97
-;;       xload64le_o32 x6, x0, 56
-;;       xload16le_u32_g32 x0, x6, x5, x2, 32
+;;       xload64le_o32 x7, x0, 56
+;;       xload16le_u32_g32 x6, x7, x6, x2, 32
+;;       zext16 x0, x6
 ;;       pop_frame
 ;;       ╰─╼ addrmap: 0x9a
 ;;       ret
@@ -219,11 +223,15 @@
 ;;
 ;; wasm[0]::function[16]::load16_two:
 ;;       push_frame
-;;       xload64le_o32 x7, x0, 64
+;;       xload64le_o32 x9, x0, 64
+;;       ╰─╼ addrmap: 0xd7
+;;       xload64le_o32 x11, x0, 56
+;;       xload16le_u32_g32 x10, x11, x9, x2, 0
+;;       xload16le_u32_g32 x9, x11, x9, x3, 0
+;;       ╰─╼ addrmap: 0xdc
+;;       zext16 x0, x10
 ;;       ╰─╼ addrmap: 0xd7
-;;       xload64le_o32 x8, x0, 56
-;;       xload16le_u32_g32 x0, x8, x7, x2, 0
-;;       xload16le_u32_g32 x1, x8, x7, x3, 0
+;;       zext16 x1, x9
 ;;       ╰─╼ addrmap: 0xdc
 ;;       pop_frame
 ;;       ╰─╼ addrmap: 0xdf
diff --git a/tests/disas/x64-simple-load.wat b/tests/disas/x64-simple-load.wat
index 6e4cdb812a2d..3cfac87ec068 100644
--- a/tests/disas/x64-simple-load.wat
+++ b/tests/disas/x64-simple-load.wat
@@ -13,14 +13,18 @@
 ;; wasm[0]::function[0]::load8:
 ;;       pushq   %rbp
 ;;       movq    %rsp, %rbp
-;;       movq    0x38(%rdi), %rsi
+;;       movq    0x38(%rdi), %r8
 ;;       ╰─╼ addrmap: 0x21
-;;       movl    %edx, %edi
-;;       movzbq  (%rsi, %rdi), %rax
+;;       movl    %edx, %r10d
+;;       movzbq  (%r8, %r10), %r9
 ;;       ╰─╼ trap: Normal(MemoryOutOfBounds)
-;;       movzbq  4(%rsi, %rdi), %rcx
+;;       movzbq  4(%r8, %r10), %r8
 ;;       ├─╼ addrmap: 0x26
 ;;       ╰─╼ trap: Normal(MemoryOutOfBounds)
+;;       movzbl  %r9b, %eax
+;;       ╰─╼ addrmap: 0x21
+;;       movzbl  %r8b, %ecx
+;;       ╰─╼ addrmap: 0x26
 ;;       movq    %rbp, %rsp
 ;;       ╰─╼ addrmap: 0x29
 ;;       popq    %rbp